阅读说明：本技术 一种半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 李建财 张傲峰 于 2020-05-12 设计创作，主要内容包括：本发明公开一种半导体结构及其制备方法,所述制备方法包括：提供一基板,基板上包括互连层、与互连层连接的第一导电体和覆盖互连层及第一导电体的钝化层；在钝化层中形成连接互连层的第二导电体,第二导电体的表面与钝化层的表面齐平；刻蚀钝化层,形成第一沟槽,第一沟槽暴露第一导电体；在钝化层上形成具有第一通孔和第二通孔的第一阻挡层,第一通孔和第二通孔分别对应第一导电体和第二导电体的位置,其中第一通孔与第一沟槽连通,第二通孔暴露第二导电体；在第二通孔内形成导电凸起,且使导电凸起与第二导电体连接。本发明解决了现有的半导体基板制备过程复杂,极大的耗费生产成本的问题。(The invention discloses a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, wherein the substrate comprises an interconnection layer, a first conductor connected with the interconnection layer and a passivation layer covering the interconnection layer and the first conductor; forming a second electrical conductor in the passivation layer, the second electrical conductor having a surface flush with a surface of the passivation layer, the second electrical conductor connecting to the interconnect layer; etching the passivation layer to form a first groove, wherein the first groove exposes the first conductor; forming a first barrier layer with a first through hole and a second through hole on the passivation layer, wherein the first through hole and the second through hole respectively correspond to the positions of the first conductor and the second conductor, the first through hole is communicated with the first groove, and the second through hole exposes the second conductor; and forming a conductive bump in the second through hole, and connecting the conductive bump with the second conductor. The invention solves the problems of complex preparation process and great production cost consumption of the existing semiconductor substrate.)

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an interconnection layer, a first conductor connected with the interconnection layer and a passivation layer covering the interconnection layer and the first conductor, and the surface of the first conductor is lower than the surface of the passivation layer;

forming a second electrical conductor in the passivation layer connecting the interconnect layer, the second electrical conductor having a surface flush with a surface of the passivation layer;

etching the passivation layer to form a first groove, wherein the first groove exposes the first conductor;

forming a first barrier layer having a first via hole and a second via hole on the passivation layer, the first via hole and the second via hole corresponding to positions of the first conductor and the second conductor, respectively, wherein the first via hole is communicated with the first trench and exposes the first conductor, and the second via hole exposes the second conductor;

and forming a conductive bump in the second through hole, and connecting the conductive bump with the second conductor.

2. The method of claim 1, wherein the second conductive material is the same as the interconnect layer.

3. The method of claim 1, wherein the first barrier layer is polyimide.

4. The method of claim 1, wherein the forming of the second conductive body comprises:

patterning the passivation layer to form a second trench communicated with the interconnection layer;

depositing a conductive material on the passivation layer to fill the second trench;

and removing the redundant conductive material to enable the surface of the conductive material to be flush with the surface of the passivation layer.

5. The method of claim 1, wherein the step of forming the first via and the second via in the first barrier layer comprises laser etching.

6. The method of claim 1, wherein the step of forming the first barrier layer having the first via and the second via comprises:

forming a first barrier layer on the passivation layer, wherein the first barrier layer fills the first trench;

and etching the first barrier layer corresponding to the first conductor and the second conductor to form the first through hole and the second through hole, so that the first through hole is communicated with the first groove and exposes the first conductor, and the second through hole exposes the second conductor.

7. The method of claim 1, wherein the step of forming the first barrier layer further comprises the steps of:

forming a liquid first barrier layer on the passivation layer;

and heating the liquid first barrier layer to obtain the solidified first barrier layer.

8. The method of claim 1, wherein the forming of the second conductive body further comprises:

forming a first barrier layer on the passivation layer;

etching the first barrier layer and the passivation layer to form a third groove communicated with the interconnection layer;

depositing a conductive material on the first barrier layer to fill the third trench;

and removing the redundant conductive material to enable the surface of the conductive material to be flush with the surface of the first barrier layer.

9. The method of claim 8, wherein the forming of the first conductive body further comprises:

and etching the position, corresponding to the first conductor, on the first barrier layer downwards to form a first through hole and a first groove which are communicated, wherein the first conductor is exposed by the first groove.

10. A semiconductor structure, comprising:

a substrate including an interconnect layer and a passivation layer thereon covering the interconnect layer;

a first electrical conductor in the passivation layer and connected to the interconnect layer, the first electrical conductor having a surface lower than a surface of the passivation layer;

a first trench in the passivation layer corresponding to a position of the first conductive body and exposing the first conductive body;

a second electrical conductor in the passivation layer and connected to the interconnect layer, the second electrical conductor having a surface that is flush with a surface of the passivation layer;

the first barrier layer is positioned on the passivation layer, a first through hole and a second through hole are respectively formed in the positions, corresponding to the first conductor and the second conductor, of the first barrier layer, the first through hole is communicated with the first groove and exposes the first conductor, and the second through hole exposes the second conductor;

and the conductive protrusion is positioned in the second through hole and is connected with the second conductor.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a semiconductor structure and a preparation method thereof.

Background

High performance semiconductor devices are often electrically interconnected to other semiconductor devices using solder bumps, for example, integrated circuit chips may be electrically connected to a circuit board or other next level package substrate using solder bumps, a technique known as flip-chip technology. The flip chip technology does not need lead bonding, forms a shortest circuit, reduces resistance, and simultaneously adopts solder bump connection to reduce the packaging size of the device. In the flip-chip technology, a built-in/out conductor is formed on a substrate, the built-in conductor serves as an input/output terminal, and the out conductor is electrically connected to an integrated circuit chip through a solder bump, thereby forming a working circuit. However, in the actual process, multiple photolithography steps are required for preparing the built-in/external conductor, the process is extremely complex, and the production cost is greatly consumed.

Disclosure of Invention

The invention aims to provide a semiconductor structure, a preparation method and application thereof, and solves the problems that the existing substrate preparation process is complex and the production cost is greatly consumed.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention provides a preparation method of a semiconductor structure, which comprises the following steps:

providing a substrate, wherein the substrate comprises an interconnection layer, a first conductor connected with the interconnection layer and a passivation layer covering the interconnection layer and the first conductor;

forming a second electrical conductor in the passivation layer connecting the interconnect layer, the second electrical conductor having a surface flush with a surface of the passivation layer;

etching the passivation layer to form a first groove, wherein the first groove exposes the first conductor;

forming a first barrier layer having a first via hole and a second via hole on the passivation layer, the first via hole and the second via hole corresponding to positions of the first conductor and the second conductor, respectively, wherein the first via hole is communicated with the first trench and exposes the first conductor, and the second via hole exposes the second conductor;

and forming a conductive bump in the second through hole, and connecting the conductive bump with the second conductor.

In one embodiment of the invention, the second electrical conductor is the same material as the interconnect layer.

In one embodiment of the present invention, the first barrier layer is made of polyimide.

In one embodiment of the present invention, the forming process of the second electrical conductor comprises the steps of:

patterning the passivation layer to form a second trench communicated with the interconnection layer;

depositing a conductive material on the passivation layer to fill the second trench;

and removing the redundant conductive material to enable the surface of the conductive material to be flush with the surface of the passivation layer.

In one embodiment of the present invention, the method of forming the first via and the second via in the first barrier layer includes using laser etching.

In one embodiment of the present invention, a method of forming the first barrier layer having the first via and the second via includes:

forming a first barrier layer on the passivation layer, wherein the first barrier layer fills the first trench;

and etching the first barrier layer corresponding to the first conductor and the second conductor to form the first through hole and the second through hole, so that the first through hole is communicated with the first groove and exposes the first conductor, and the second through hole exposes the second conductor.

In one embodiment of the present invention, the process of forming the first barrier layer further comprises the steps of:

forming a liquid first barrier layer on the passivation layer;

and heating the liquid first barrier layer to obtain the solidified first barrier layer.

In an embodiment of the present invention, the forming process of the second conductive body may further include the steps of:

forming a first barrier layer on the passivation layer;

etching the first barrier layer and the passivation layer to form a third through hole communicated with the interconnection layer;

depositing a conductive material on the first barrier layer to fill the third via;

and removing the redundant conductive material to enable the surface of the conductive material to be flush with the surface of the first barrier layer.

In an embodiment of the present invention, the forming process of the first conductive body may further include the steps of:

and etching the position, corresponding to the first conductor, on the first barrier layer downwards to form a first through hole and a first groove which are communicated, wherein the first conductor is exposed by the first groove.

The present invention is also a semiconductor structure, comprising:

a substrate including an interconnect layer and a passivation layer thereon covering the interconnect layer;

a first electrical conductor in the passivation layer and connected to the interconnect layer, the first electrical conductor having a surface lower than a surface of the passivation layer;

a first trench in the passivation layer corresponding to a position of the first conductive body and exposing the first conductive body;

a second electrical conductor in the passivation layer and connected to the interconnect layer, the second electrical conductor having a surface that is flush with a surface of the passivation layer;

the first barrier layer is positioned on the passivation layer, a first through hole and a second through hole are respectively formed in the positions, corresponding to the first conductor and the second conductor, of the first barrier layer, the first through hole is communicated with the first groove and exposes the first conductor, and the second through hole exposes the second conductor;

and the conductive protrusion is positioned in the second through hole and is connected with the second conductor.

The invention solves the problems of complex preparation process and great consumption of production cost of the existing substrate. Specifically, the high-hardness polymer is used as the first barrier layer, etching operation can be directly carried out on the first barrier layer, and the built-in/external conductor is exposed. In addition, the second conductor and the interconnection layer are made of the same material, and the second conductor can be formed in one step by directly etching the first barrier layer, so that the steps of generating an intermediate connection conductor and a plurality of photoetching processes are avoided, and the cost is saved.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a semiconductor device;

FIG. 2 is a flow chart of a method for fabricating the first semiconductor structure of FIG. 1;

FIG. 3 is a schematic structural diagram corresponding to step S1 in FIG. 2;

fig. 4 to 8 are schematic structural diagrams corresponding to step S2 in fig. 2;

FIG. 9 is a schematic structural diagram corresponding to step S3 in FIG. 2;

fig. 10 to 11 correspond to the schematic structural diagram of step S4;

fig. 12 is a schematic structural diagram corresponding to step S5 in fig. 2;

FIG. 13 is a flow chart of another method for fabricating a first semiconductor structure according to the present invention;

FIG. 14 is a schematic structural diagram of step R2 in FIG. 13;

fig. 15 to 18 are schematic structural views corresponding to step R3 in fig. 13;

fig. 19 is a schematic structural diagram corresponding to step R4 in fig. 13.

Description of the drawings:

001 a first semiconductor structure; 002 a second semiconductor structure; 010 a substrate; 011 an interconnect layer; 012 a first electrical conductor; 013 a passivation layer; 014 a second barrier layer; 015 second trenches; 016 a first trench; 017 first through holes; 018 a second through hole; 019 a third groove; 020 a second electrical conductor; 030 a first barrier layer; 040 conductive bumps; 060 a first patterned photoresist layer; 061 second patterned photoresist layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 2 and fig. 3, the present invention provides a semiconductor device, including: a first semiconductor structure 001 and a second semiconductor structure 002. Wherein the first semiconductor structure 001 comprises: substrate 010, first conductor 012, second conductor 020, first barrier layer 030, and conductive bump 040. The substrate 010 may include an interconnect layer 011 thereon, the interconnect layer 011 may provide an electrical and/or mechanical connection to another substrate through a conductive material, and the interconnect layer 011 may include, for example, a conductive metal such as copper, aluminum, etc. The second semiconductor structure 002 may be the same as the first semiconductor structure 001 or different from the first semiconductor structure 001, for example, the second semiconductor structure 002 may be another integrated circuit semiconductor device or a printed circuit board, and the second semiconductor structure 002 may also include an integrated circuit chip. The first semiconductor structure 001 and the second semiconductor structure 002 are electrically/mechanically coupled through a circuit path formed between the interconnection layer 011, the second conductor 020 and the conductive bump 040, and the first conductor 012 serves as an input/output terminal, so that a circuit can be formed between the first semiconductor structure 001 and the second semiconductor structure 002.

Referring to fig. 1, 2 and 3, the present invention provides a semiconductor structure, such as a first semiconductor structure 001, including: substrate 010, first conductor 012, second conductor 020, first barrier layer 030, and conductive bump 040.

Referring to fig. 1, 2, and 3, the substrate 010 may include a semiconductor substrate, such as a silicon, gallium arsenide, gallium nitride, and/or silicon carbide substrate, which may include electronic devices thereon, such as transistors, diodes, resistors, capacitors, and/or inductors. The substrate herein may refer to a wafer having a plurality of semiconductor structures thereon, or may refer to an integrated circuit chip having a single semiconductor structure thereon. In this embodiment, the substrate may be a substrate including a metal-oxide-semiconductor field effect transistor (MOS transistor).

Referring to fig. 1, 2 and 3, in the present embodiment, the substrate 010 may include an interconnection layer 011, an exposed first conductive body 012 and a passivation layer 013, wherein the interconnection layer 011 can provide an electrical and/or mechanical connection to another substrate through a conductive material. The interconnect layer 011 may include, for example, a conductive metal such as copper or aluminum. The first conductor 012 can be located on the interconnect layer 011, or can be led out from the same metal layer as the interconnect layer 011, the first conductor 012 is connected to the interconnect layer 011, the surface of the first conductor 012 is lower than the surface of the passivation layer 013, specifically, the first conductor 012 can include a conductive metal such as aluminum, the first conductor 012 can be directly electrically connected to the substrate through the interconnect layer 011, the first conductor 012 can be used for input/output of an electronic device including the substrate, in some embodiments first conductive body 012 can be used as a pad for subsequent soldering, and in other embodiments first conductive body 012 can also be provided with a fuse, which can be obtained by mechanical means or cutting with a laser, which can provide coupling/decoupling for redundant circuits on the substrate, in other embodiments, first conductor 012 may also provide a pad for testing circuitry on a substrate. In this embodiment, the first conductor 012 is used as a connection terminal for inputting/outputting to/from an electronic device including a substrate. The passivation layer 013 may include an inorganic material such as silicon dioxide and/or silicon nitride, and the passivation layer 013 may also include an organic material such as tetraethoxysilane, and a first groove 016 is provided in the passivation layer 013 at a position corresponding to the first electric conductor 012, and the first groove 016 exposes the first electric conductor 012. In other embodiments, a second barrier layer 014 may also be formed on the surface of the interconnect layer 011.

Referring to fig. 1, a passivation layer 013 is provided with a second conductive body 020 connected to the substrate interconnect layer 011, a surface of the second conductive body 020 is flush with a surface of the passivation layer 013, and a material of the second conductive body 020 may be the same as a material of the interconnect layer 011, for example, a conductive metal such as copper, aluminum, or the like. The second conductor 020 is connected to the interconnect layer 011, and the second conductor 020 can electrically transmit a signal to the substrate.

Referring to fig. 1, a first barrier layer 030 is disposed on a passivation layer 013, the first barrier layer 030 is formed by curing liquid polyimide, and a first via 017 and a second via 018 are disposed on the first barrier layer 030, wherein the first via 017 is communicated with the first trench 016 and exposes the first conductor 012, and the second via 018 exposes the second conductor 020.

Referring to fig. 1, the conductive protrusion 040 is disposed in the second through hole 018 and connected to the second conductive body, the conductive protrusion 040 may have various shapes, in this embodiment, the conductive protrusion 040 is, for example, a ball shape, the conductive protrusion 040 includes, for example, solder containing tin, in other embodiments, the conductive protrusion 040 may further include nickel, gold, and/or copper, and in this embodiment, the conductive protrusion 040 uses solder containing tin. The conductive bump 040, the second conductor 020 and the first conductor 012 form a conductive path to connect with the interconnect layer 011, so as to realize electrical coupling with the substrate.

Referring to fig. 1, in the condition where the first conductive body 012 is exposed, the conductive bump 040 can be used to electrically and/or mechanically couple with another substrate, such as another integrated circuit semiconductor device and/or a printed circuit board. After the conductive bump 040 is formed and/or the conductive bump 040 is soldered to another substrate in this manner, the first conductor 012 may be used as an input/output terminal, or the first conductor 012 may be burned, cut, inspected, and/or soldered. As shown in fig. 8 to 12, in some other embodiments, the substrate 010 may include a first conductor 012 and a plurality of conductive bumps 040 and second conductor 020 to form a plurality of conductive paths connected to the interconnect layer 011, so as to achieve electrical coupling between the semiconductor devices.

Referring to fig. 1 to 12, the present invention further provides a method for fabricating a semiconductor structure, which comprises the following steps:

s1, providing a substrate 010, wherein the substrate 010 comprises an interconnection layer 011, a first conductor 012 connected to the interconnection layer 011, and a passivation layer 013 covering the interconnection layer 011 and the first conductor 012, and the surface of the first conductor 012 is lower than the surface of the passivation layer 013;

s2, forming a second electric conductor 020 connected to the interconnect layer 011 in the passivation layer 013, wherein the surface of the second electric conductor 020 is flush with the surface of the passivation layer 013;

s3, etching the passivation layer 013 to form a first trench 016, wherein the first trench 016 exposes the first conductor 012;

s4, forming a first barrier layer 030 with a first via 017 and a second via 018 on the passivation layer 013, the first via 017 and the second via 018 corresponding to the positions of the first conductor 012 and the second conductor 020 respectively, wherein the first via 017 communicates with the first trench 016 and exposes the first conductor 012, and the second via 018 exposes the second conductor 020;

s5, forming a conductive bump 040 in the second through hole 018, and connecting the conductive bump 040 to the second conductor 020.

Specifically, each step of the method for manufacturing a semiconductor structure is described in detail below with reference to fig. 1 to 12.

Referring to fig. 3, first, in step S1, the substrate 010 may include a semiconductor substrate, such as a silicon, gallium arsenide, gallium nitride, and/or silicon carbide substrate, which may include electronic devices thereon, such as transistors, diodes, resistors, capacitors, and/or inductors. The substrate herein may refer to a wafer having a plurality of semiconductor structures thereon, or may refer to an integrated circuit chip having a single semiconductor structure thereon. In this embodiment, the substrate may be a substrate including a metal-oxide-semiconductor field effect transistor (MOS transistor). The substrate 010 further includes an interconnection layer 011, a first electrical conductor 012, and a passivation layer 013 covering the interconnection layer 011 and the first electrical conductor 012, wherein the interconnection layer 011 can be electrically and/or mechanically connected to another substrate through a conductive material. The interconnect layer 011 may include, for example, a conductive metal such as copper or aluminum. The first conductor 012 may be formed on the interconnect layer 011, or may be led out from the same metal layer as the interconnect layer 011, in this embodiment, the first conductor 012 is formed on a part of the interconnect layer 011, in connection with the interconnect layer 011, the first conductor 012 can include a conductive metal such as aluminum, the first conductor 012 can be electrically connected to the substrate directly or through the interconnect layer 011, the first conductor 012 can be used for input/output of an electronic device including the substrate, in some embodiments first conductive body 012 can be used as a pad for subsequent soldering, and in other embodiments first conductive body 012 can also be provided with a fuse, which can be obtained by mechanical means or cutting with a laser, which can provide coupling/decoupling for redundant circuits on the substrate, in other embodiments, first conductor 012 may also provide a pad for testing circuitry on a substrate. In this embodiment, the first conductor 012 is used as a connection terminal for inputting/outputting to/from an electronic device including a substrate. A passivation layer 013 can be formed on the interconnect layer 011 and the first conductive body 012 by sputtering, evaporation, and/or chemical vapor deposition, wherein the passivation layer 013 can include an inorganic material such as silicon dioxide and/or silicon nitride, the passivation layer 013 can also include an organic material such as tetraethoxysilane and/or polyimide, in this embodiment, the passivation layer 013 adopts tetraethoxysilane, specifically, phosphorus-doped tetraethoxysilane (PTEOS) or borophosphosilicate tetraethoxysilane (BPTEOS), and the passivation layer 013 covers the interconnect layer 011 and the first conductive body 012.

Referring to fig. 4 to 8, in step S2, a second conductor 020 connected to the interconnect layer 011 is formed in the passivation layer 013, a surface of the second conductor 020 is flush with a surface of the passivation layer 013, a material of the second conductor 020 may be the same as a material of the interconnect layer 011, for example, a conductive metal including copper, aluminum, etc., and in this embodiment, a copper-containing metal is used for both the interconnect layer 011 and the second conductor 020. The specific process for preparing the second electric conductor 020 can include the following steps: a second trench 015 communicating with the interconnect layer 011 is formed on the passivation layer 013 by dry etching, and specifically, in this embodiment, a first patterned photoresist layer 060 may be formed on the passivation layer 013, the first patterned photoresist layer 060 exposes a portion of the passivation layer 013, and a position of the second conductor 020 is defined by the first patterned photoresist layer 060, and the position corresponds to the position of the interconnect layer 011. In this embodiment, the passivation layer 013 can be etched, e.g., using a reactive ion etching or plasma etching process, to expose the surface material of the interconnect layer 011.

Referring to fig. 4 to 8, in step S2, in some embodiments, a photoresist layer may be formed on the passivation layer 013 by, for example, a spin coating method, an exposure and development process is performed to form an opening on the photoresist layer to obtain a first patterned photoresist layer 060, the passivation layer 013 under the opening pattern is removed by using the first patterned photoresist layer 060 as a mask until the surface material of the interconnect layer 011 is exposed to form a second trench 015 communicating with the interconnect layer 011, and then the photoresist layer may be removed by ashing.

Referring to fig. 4 to 8, in step S2, a metal, such as a conductive metal including copper, aluminum, etc., is deposited on the surface of the passivation layer 013 by using a high density plasma chemical vapor deposition method to fill the second trench 015, and then the excess metal material is removed by, for example, chemical mechanical polishing, so that the upper surface of the metal material in the second trench 015 is flush with the upper surface of the passivation layer 013, thereby forming a second conductive body 020, in which the second trench 015 is filled with the same metal material as the interconnect layer 011, such as a metal containing copper.

Referring to fig. 9, in another embodiment, in step S3, a portion of the passivation layer 013 is etched away to expose the first conductor 012. Specifically, in this embodiment, a second patterned photoresist layer 061 may be formed on the passivation layer 013 and the second conductive body 020, where the second patterned photoresist layer 061 exposes a portion of the passivation layer 013, and a patterned region of the photoresist layer corresponds to a position of the first conductive body 012. In this embodiment, the passivation layer 013 may be etched, for example, by using a reactive ion etching or plasma etching process, to form the first trench 016, such that the surface material of the first conductive body 012 is exposed in the first trench 016.

Referring to fig. 9, in step S3, in some embodiments, a photoresist layer may be formed on the passivation layer 013 and the second conductive body 020 by, for example, a spin coating method, an exposure and development process is performed to form an opening on the photoresist layer to obtain a second patterned photoresist layer 061, the passivation layer 013 under the opening pattern is removed using the second patterned photoresist layer 061 as a mask until the surface material of the first conductive body 012 is exposed to form a first groove 016, such that the first groove 016 exposes the surface of the first conductive body 012, and then the photoresist layer may be removed by ashing, so that the first conductive body 012 can be used as an input/output terminal of an electronic device or as a solder pad. In other embodiments, when the first conductive body 012 is etched to form the first trench 016, the etching process is continued to a certain depth to ensure the quality of the later electrical connection of the first conductive body 012.

Referring to fig. 10 and 11, in step S4, a first barrier layer 030 having a first via 017 and a second via 018 are formed on a passivation layer 013, where the first via 017 and the second via 018 correspond to positions of a first conductor 012 and a second conductor 020, respectively, where the first via 017 communicates with a first trench 016 to expose the first conductor 012, and the second via 018 exposes the second conductor 020, where the first barrier layer 030 may be a high-hardness polymer, in this embodiment, the first barrier layer 030 may be made of, for example, a cured polyimide, specifically, in this embodiment, for example, a liquid polyimide layer is spin-coated on the passivation layer 013, the second conductor 020, and the first conductor 012, and at this time, the liquid polyimide fills the first trench 016 corresponding to the first conductor 012, the liquid polyimide layer is heated and dried at a temperature range of 150 ° -250 °, in the embodiment, for example, laser etching is used to etch the solid polyimide corresponding to the positions of the first conductor 012 and the second conductor 020 to form a first via 017 and a second via 018, where the first via 017 is communicated with the first trench 016 to expose the first conductor 012, and the second via 018 exposes the surface of the second conductor 020.

Referring to fig. 1 and 12, in step S5, a conductive bump 040 is formed in the second through hole 018 corresponding to the second conductor 020, and the conductive bump 040 is connected to the second conductor 020. In this embodiment, the conductive bump 040 can be connected to the second conductive body 020 by forming a conductive bump 040 in the second through hole 018 corresponding to the second conductive body 020 through maskless electroplating or other deposition techniques, the conductive bump 040 may be made of, for example, solder containing tin, in other embodiments, the conductive bump 040 may further contain nickel, gold, and/or copper, and in this embodiment, solder containing tin is used for the conductive bump 040. The conductive protrusion 040 may have various shapes, in this embodiment, a portion of the conductive protrusion 040 located in the groove is a cylinder, and a portion of the conductive protrusion 040 located outside the second through hole 018 is a sphere, and specifically, the formed conductive protrusion 040 may be formed into a sphere through steps of melting, reflowing, and the like. The conductive bump 040, the second conductor 020, and the first conductor 012 form a conductive path and are connected to the interconnect layer 011, thereby achieving electrical coupling with the substrate. In other embodiments, a protective layer may be formed on the second conductors 020 and the first conductors 012 to prevent the second conductors 020 and the first conductors 012 from being oxidized, and specifically, a resin layer may be formed on the second conductors 012 and the first conductors 020 by a method such as chemical coating or deposition to prevent the second conductors 012 and the first conductors 012 from being oxidized.

Referring to fig. 1 and 12, in step S5, under the condition that the first conductive body 012 is exposed, the conductive bump 040 can be used to realize electrical and/or mechanical coupling with another substrate, such as another integrated circuit semiconductor device and/or a printed circuit board. After the conductive bump 040 is formed and/or the conductive bump 040 is soldered to another substrate in this manner, the first conductor 012 may be used as an input/output terminal, or the first conductor 012 may be burned, cut, inspected, and/or soldered.

Referring to fig. 1 and 12, in step S1 to step S5, the present invention uses a high hardness polymer as the first barrier 030, and the etching operation can be performed directly on the first barrier 030 by dry etching to expose the internal/external conductors, such as the first conductor 012 and the second conductor 020, which has fewer process steps, simple method and low cost compared with the existing photolithography process. In addition, the second conductor 020 and the interconnection layer 011 are made of the same material, for example, copper-containing metal, and the first barrier layer 030 is directly etched by dry etching, so that the second conductor 020 can be formed in one step, intermediate connection conductors are prevented from being generated, a plurality of photoetching process steps are saved, and cost saving is facilitated.

Referring to fig. 13 to 19, in another embodiment, the present invention further provides a method for manufacturing a semiconductor structure, which includes the following steps:

r1, providing a substrate 010, wherein the substrate 010 comprises an interconnection layer 011, a first conductor 012 connected with the interconnection layer 011, and a passivation layer 013 covering the interconnection layer 011 and the first conductor 012;

r2, forming a first barrier layer 030 on the passivation layer 013;

r3, forming a third trench 019 in the first barrier layer 030 and the passivation layer 013;

r4, filling a conductive material in the third groove 019 to form a second conductor 020 connected to and exposed from the interconnect layer 011, wherein the surface of the second conductor 020 is flush with the surface of the first barrier layer 030;

r5, etching the first barrier layer 030 and the passivation layer 013, exposing the first electrical conductor 012;

r6, a conductive projection 040 is formed on the surface of the second conductor 020.

Referring to fig. 13, in step R1, a substrate 010 similar to that in step S1 is provided.

Referring to fig. 14, in step R2, a first barrier layer 030 is formed on a passivation layer 013, where the first barrier layer 030 may be a polymer layer with high hardness, and in this embodiment, the first barrier layer 030 may be made of, for example, cured polyimide, specifically, in this embodiment, a liquid polyimide layer is spin-coated on a surface of the passivation layer 013, and the liquid polyimide layer is heated and dried at a temperature ranging from 150 ° to 250 ° to form a solid polyimide layer.

Referring to fig. 15 to 18, in step R3 and step R4, in this embodiment, for example, a laser etching method is used to etch the surface of the solid polyimide layer, so as to form a third groove 019 penetrating through the first barrier layer 030, the passivation layer 013 and the interconnect layer 011, a conductive material is deposited on the surface of the first barrier layer 030, so as to fill the conductive material in the third groove 019, the conductive material is, for example, a conductive metal such as copper, aluminum, and the like, and then, for example, by chemical mechanical polishing, the excess conductive material is removed, so that the upper surface of the conductive material in the third groove 019 is flush with the upper surface of the first barrier layer 030, so as to form a second conductive body 020, in this embodiment, the same conductive material as the interconnect layer 011, for example, a copper-containing metal, is filled in the third groove 019.

Referring to fig. 19, in step R5, a laser etching method is also used to etch the first barrier layer 030 downward corresponding to the position of the first conductor 012, so as to form a first via 017 and a first trench 016 in communication with each other, so as to expose the first conductor 012.

Referring to fig. 12, in step R6, a conductive bump 040 is formed on the surface of the second conductive body 020. In this embodiment, the conductive bump 040 can be formed on the surface of the second conductive body 020 by maskless electroplating or other deposition techniques, for example, the conductive bump 040 includes solder containing tin, and in other embodiments, the conductive bump 040 can also include nickel, gold, and/or copper, and in this embodiment, the conductive bump 040 includes solder containing tin. The conductive protrusion 040 may have various shapes, and in this embodiment, the conductive protrusion 040 may be a sphere, and specifically, the formed conductive protrusion 040 may be formed into a sphere through steps of melting, reflowing, and the like. The conductive bump 040, the second conductor 020, and the first conductor 012 form a conductive path and are connected to the interconnect layer 011, thereby achieving electrical coupling with the substrate. In other embodiments, a protective layer may be formed on the second conductors 020 and the first conductors 012 to prevent the second conductors 020 and the first conductors 012 from being oxidized, and specifically, a resin layer may be formed on the second conductors 012 and the first conductors 020 by a method such as chemical coating or deposition to prevent the second conductors 012 and the first conductors 012 from being oxidized.

The above disclosure of selected embodiments of the invention is intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.