阅读说明：本技术 一种半导体结构的制备方法及其应用方法 (Preparation method and application method of semiconductor structure ) 是由 李建财 张傲峰 于 2020-05-12 设计创作，主要内容包括：本发明公开一种半导体结构的制备方法及其应用方法,属于集成电路技术领域。本发明的半导体结构的制备方法,其至少包括以下步骤：提供一基板,所述基板上包括互连层和覆盖所述互连层的钝化层；在所述钝化层上形成连接互连层的第一导电体,所述第一导电体的表面与所述钝化层的表面齐平；在所述第一导电体上形成第二导电体,所述第二导电体呈长柱状。本发明解决了由于半导体器件尺寸缩减导致的金属垫与导电凸起之间的结合力不好的问题。(The invention discloses a preparation method and an application method of a semiconductor structure, and belongs to the technical field of integrated circuits. The preparation method of the semiconductor structure at least comprises the following steps: providing a substrate, wherein the substrate comprises an interconnection layer and a passivation layer covering the interconnection layer; forming a first electric conductor connected with an interconnection layer on the passivation layer, wherein the surface of the first electric conductor is flush with the surface of the passivation layer; and forming a second conductor on the first conductor, wherein the second conductor is in a long column shape. The invention solves the problem of poor bonding force between the metal pad and the conductive bump caused by the size reduction of the semiconductor device.)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an interconnection layer and a passivation layer covering the interconnection layer;

forming a first electric conductor connected with an interconnection layer on the passivation layer, wherein the surface of the first electric conductor is flush with the surface of the passivation layer;

and forming a second conductor on the first conductor, wherein the second conductor is in a long column shape.

2. The method of claim 1, wherein the forming of the second conductive body comprises: and spin-coating a liquid polyimide layer on the passivation layer and the surface of the first conductor, and heating and drying to form a first barrier layer.

3. The method of claim 2, wherein the liquid polyimide layer is dried at a temperature in a range of 150 ℃ to 250 ℃.

4. The method of claim 2, wherein the forming of the second conductive body further comprises:

and etching the first barrier layer to form an opening at a position corresponding to the first conductor.

5. The method of claim 4, wherein the forming of the second conductive body further comprises:

depositing a conductive material on the first barrier layer to fill the opening.

6. The method of claim 5, wherein the forming of the second conductive body further comprises:

and removing the redundant conductive material to enable the surface of the conductive material to be flush with the surface of the first barrier layer.

7. The method of claim 6, wherein the forming of the second conductive body further comprises: and removing the first barrier layer by adopting a wet etching method.

8. The method of claim 1, wherein the diameter of the second conductor is 0.5 μm to 10 μm.

9. The method of claim 1, further comprising forming a third exposed conductor on the substrate and connected to the interconnect layer.

10. A semiconductor packaging method is characterized by at least comprising the following steps:

providing a first semiconductor structure, wherein the preparation method of the first semiconductor structure comprises the following steps:

providing a substrate, wherein the substrate comprises an interconnection layer and a passivation layer covering the interconnection layer;

forming a first electric conductor connected with an interconnection layer on the passivation layer, wherein the surface of the first electric conductor is flush with the surface of the passivation layer;

forming a second conductor on the first conductor, wherein the second conductor is in a long column shape; providing a second semiconductor structure electrically connected to the first semiconductor structure through the second electrical conductor.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a preparation method and an application method of a semiconductor structure.

Background

In order to improve the performance and cost performance of integrated circuits and systems, the feature size of semiconductor devices has been reduced because the operating speed has increased and the power consumption has decreased as the feature size of the devices has decreased. Meanwhile, more components can be manufactured on one chip, so that the integration level is improved, and the average price of unit functions is reduced.

The semiconductor structure is usually electrically connected to other semiconductor structures by using the conductive bump connected to the metal pad, but as the size of the semiconductor structure is reduced, the distance between the conductive bumps is also reduced, and the conventional metal pad needs to be reduced in order to be combined with the conductive bump, which may result in a reduced area of the metal pad and a poor combination force between the metal pad and the conductive bump.

Disclosure of Invention

The invention aims to provide a preparation method and an application method of a semiconductor structure, which solve the problem that the bonding force between a metal pad and a conductive bump is poor due to the reduction of the space and the area of the metal pad along with the size reduction of the semiconductor structure.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention provides a preparation method of a semiconductor structure, which at least comprises the following steps:

providing a substrate, wherein the substrate comprises an interconnection layer and a passivation layer covering the interconnection layer;

forming a first electric conductor connected with an interconnection layer on the passivation layer, wherein the surface of the first electric conductor is flush with the surface of the passivation layer;

and forming a second conductor on the first conductor, wherein the second conductor is in a long column shape.

In one embodiment of the present invention, the forming process of the second electrical conductor comprises the steps of: and spin-coating a liquid polyimide layer on the passivation layer and the surface of the first conductor, and heating and drying to form a first barrier layer.

In one embodiment of the present invention, the liquid polyimide layer is heated to a temperature in a range of 150 ℃ to 250 ℃.

In one embodiment of the present invention, the process of forming the second electrical conductor further comprises the steps of:

and etching the first barrier layer to form an opening at a position corresponding to the first conductor.

In one embodiment of the present invention, the process of forming the second electrical conductor further comprises the steps of:

depositing a conductive material on the first barrier layer to fill the opening.

In one embodiment of the present invention, the process of forming the second electrical conductor further comprises the steps of:

and removing the redundant conductive material to enable the surface of the conductive material to be flush with the surface of the first barrier layer.

In one embodiment of the present invention, the process of forming the second electrical conductor further comprises the steps of: and removing the first barrier layer by adopting a wet etching method.

In one embodiment of the invention, the diameter of the second electrical conductor obtained is between 0.5 μm and 10 μm.

In one embodiment of the present invention, the method for fabricating the semiconductor structure further includes forming a third conductive body on the substrate, which is connected to the interconnection layer and exposed.

The invention also provides a semiconductor packaging method, which at least comprises the following steps:

providing a first semiconductor structure, wherein the preparation method of the first semiconductor structure comprises the following steps:

providing a substrate, wherein the substrate comprises an interconnection layer and a passivation layer covering the interconnection layer;

forming a first electric conductor connected with an interconnection layer on the passivation layer, wherein the surface of the first electric conductor is flush with the surface of the passivation layer;

forming a second conductor on the first conductor, wherein the second conductor is in a long column shape;

providing a second semiconductor structure electrically connected to the first semiconductor structure through the second electrical conductor.

The second conductor with the long columnar structure replaces the existing metal pad structure, and the second conductor with the long columnar structure is inserted into the conductive protrusion for connection, so that the distance between the second conductors can be further reduced, the size reduction of a semiconductor device is facilitated, meanwhile, the contact area between the second conductors and the conductive protrusion can be increased, and the bonding force between the second conductors and the conductive protrusion is further improved.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a structural view of a semiconductor device obtained by applying the semiconductor structure of the present invention;

FIG. 2 is an enlarged view of a portion of FIG. 1;

FIG. 3 is a flow chart of a method for fabricating the first semiconductor structure of FIG. 1;

FIG. 4 is a schematic structural diagram corresponding to step S1 in FIG. 3;

fig. 5 and 6 are schematic structural diagrams corresponding to step S2 in fig. 3;

fig. 7 to 13 are schematic structural diagrams corresponding to step S3 in fig. 3.

Reference numerals

001 a first semiconductor structure; 002 a second semiconductor structure; 010 a substrate;

020 a first electrical conductor; 030 a first barrier layer; 040 second conductor;

050 conductive bumps; 060 a first patterned photoresist layer; 070 a second patterned photoresist layer;

011 an interconnect layer; 012 a third conductor; 013 a passivation layer; 014 second barrier layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 and 3, the present invention provides a semiconductor package structure, which includes: a first semiconductor structure 001 and a second semiconductor structure 002. Wherein the first semiconductor structure 001 comprises: substrate 010, first conductor 020, second conductor 040, third conductor 012, and conductive bump 050. The substrate 010 may include an interconnect layer 011 thereon, the interconnect layer 011 may provide an electrical and/or mechanical connection to another substrate through a conductive material, and the interconnect layer 011 may include, for example, a conductive metal such as copper, aluminum, etc. The second semiconductor structure 002 may be the same as the first semiconductor structure 001 or may be different from the first semiconductor structure 001, for example, the second semiconductor structure 002 may be another integrated circuit semiconductor device or may be a printed circuit board. The first semiconductor structure 001 and the second semiconductor structure 002 are electrically/mechanically coupled through a circuit path formed between the interconnection layer 011, the first conductor 020, the second conductor 040 and the conductive bump 050, and the third conductor 012 is used as an input/output end, so that a circuit can be formed between the first semiconductor structure 001 and the second semiconductor structure 002.

The invention also provides a semiconductor packaging method, which at least comprises the following steps: first, a first semiconductor structure 001 is provided, and then a second semiconductor structure 002 is provided to be connected to the first semiconductor structure 001. The preparation method of the first semiconductor structure 001 comprises the following steps: providing a substrate 010, wherein the substrate 010 comprises an interconnection layer 011 and a passivation layer 013 covering the interconnection layer 011, forming a first electric conductor 020 connected with the interconnection layer 011 on the passivation layer 013, wherein the surface of the first electric conductor 020 is flush with the surface of the passivation layer 013, then forming a second electric conductor 040 on the first electric conductor 020, and then forming a conductive bump 050 on the second electric conductor 040, wherein the second electric conductor 040 is inserted into the conductive bump 050.

Finally, the second semiconductor structure 002 is connected, for example soldered, to the conductive bumps 050 and then to the first semiconductor structure 001.

Referring to fig. 1 and 3, a semiconductor structure of the present invention includes: substrate 010, first conductor 020, second conductor 040, third conductor 012, and conductive bump 050.

Referring to fig. 1 and 3, the substrate 010 may include a semiconductor substrate, such as a silicon, gallium arsenide, gallium nitride, and/or silicon carbide substrate, which may include electronic devices thereon, such as transistors, diodes, resistors, capacitors, and/or inductors. The substrate herein may refer to a wafer having a plurality of semiconductor structures thereon, or may refer to an integrated circuit chip having a single semiconductor structure thereon. In this embodiment, the substrate may be a substrate including a metal-oxide-semiconductor field effect transistor (MOS transistor).

Referring to fig. 1 and 3, in the present embodiment, the substrate 010 may include an interconnection layer 011, an exposed third conductor 012 and a passivation layer 013, wherein the interconnection layer 011 can provide electrical and/or mechanical connection to another substrate through a conductive material. The interconnect layer 011 may include, for example, a conductive metal such as copper or aluminum. The third conductor 012 may be formed on the interconnect layer 011 or may be drawn out from the same metal layer as the interconnect layer 011, the third conductor 012 may include a conductive metal such as aluminum, and the height of the third conductor 012 may be, for example, 50 μm to 200 μm. The third conductive body 012 can be electrically connected to the substrate directly or through the interconnect layer 011, the third conductive body 012 can be used for inputting/outputting to an electronic device including the substrate, in some embodiments, the third conductive body 012 can be used as a pad for subsequent soldering, in other embodiments, the third conductive body 012 can further provide a fuse, the fuse can be obtained by mechanical method or cutting with laser, the fuse can provide coupling/decoupling for redundant circuits on the substrate, and in other embodiments, the third conductive body 012 can further provide a pad for detecting circuits on the substrate. In this embodiment, the third conductor 012 is used as a connection terminal for inputting/outputting to/from an electronic device including a substrate. The passivation layer 013 may include an inorganic material such as silicon dioxide and/or silicon nitride, and the passivation layer 013 may also include an organic material such as tetraethoxysilane and/or polyimide. The groove on the passivation layer 013 can partially expose the third conductor 012, and more specifically, the passivation layer 013 can be formed on the third conductor 012 and the interconnect layer 011 and then the portion of the passivation layer 013 can be selectively removed to expose a portion of the third conductor 012. by leaving a portion of the third conductor 012 exposed, the third conductor 012 can be used later as an input/output terminal of an electronic device or later used for inspection, cutting, and/or as a bonding pad. In other embodiments, a second barrier layer 014 may also be disposed on the interconnect layer.

Referring to fig. 1 and 3, a passivation layer 013 is etched to form a hole corresponding to a region except for the third conductor 012, the hole is connected to the substrate interconnect layer 011, a metal is filled into the hole to form a first conductor 020, a surface of the first conductor 020 is flush with a surface of the passivation layer 013, the first conductor 020 can be, for example, W, TiW, TiN and/or a combination thereof, and a diameter of the first conductor 020 is, for example, 0.5 μm to 10 μm. The number of the first conductors 020 may be one, and as shown in fig. 4 to 12, in another embodiment, the number of the first conductors 020 may be plural, and the pitch (distance between adjacent edges) of the adjacent first conductors 020 may be, for example, 1 μm to 5 μm.

Referring to fig. 1 and 3, a second conductor 040 is formed on a first conductor 020, the second conductor 040 is in the shape of a long column, the second conductor 040 may include copper, for example, and the diameter of the second conductor 040 may be equal to the diameter of the first conductor 020, and in some embodiments, the diameter of the second conductor 040 may be smaller than the diameter of the first conductor 020. The number of the second conductors 040 may be one, or may be plural as shown in fig. 5 to 9, or, as shown in fig. 10 to 12, when the diameter of the second conductors 040 is smaller than the diameter of the first conductors 020, the pitch (distance between adjacent edges) between the adjacent second conductors 040 is, for example, 2 μm to 10 μm.

In this embodiment, the second electric conductor 040 may have a columnar structure protruding from the surface of the passivation layer 013. The first conductor 020 can connect the second conductor 040 and the interconnect layer 011, and the first conductor 020 can also realize signal electrical transmission between the second conductor 040 and the substrate.

Referring to fig. 1 and 3, the conductive bump 050 is formed on the second conductor 040, and particularly, the cylindrical second conductor 040 is partially inserted into the conductive bump 050, where the conductive bump 050 can have various shapes, in this embodiment, the conductive bump 050 is, for example, a sphere, the conductive bump 050 is, for example, a solder containing tin, in other embodiments, the conductive bump 050 can also contain nickel, gold, and/or copper, and in this embodiment, the conductive bump 050 is a solder containing tin. The conductive bump 050, the second conductor 040 and the first conductor 020 form a conductive path to be connected with the interconnection layer 011, so that the conductive bump is electrically coupled with the substrate.

Referring to fig. 1 and 3, under the condition that the third conductive body 012 is exposed, the conductive bump 050 can realize the electrical and/or mechanical coupling with another substrate, such as another integrated circuit semiconductor device and/or a printed circuit board. After forming the conductive bumps 050 and/or soldering the conductive bumps 050 to another substrate in this way, the third conductor 012 may be used as an input/output terminal, or the third conductor 012 may be burned, cut, inspected, and/or soldered.

Referring to fig. 1 and 3, since the second conductive body 040 is in a long column shape and is connected to the conductive protrusion 050 by insertion, the distance between the second conductive bodies 040 is reduced, the contact area between the second conductive bodies 040 and the conductive protrusion 050 is not affected, and even the contact area between the second conductive bodies 040 and the conductive protrusion 050 can be further increased, so as to improve the bonding force between the conductive protrusion 050 and the second conductive bodies 040, and thus the performance of the semiconductor device is ensured under the condition of reducing the size of the semiconductor device. In other embodiments, the substrate 010 may include a third conductive body 012 and a plurality of conductive bumps 050, second conductive bodies 040, and first conductive bodies 020, which form a plurality of conductive paths connected to the interconnect layer 011, so as to realize electrical coupling between the semiconductor devices.

Referring to fig. 2, the present invention further provides a method for fabricating a semiconductor structure, which at least includes the following steps:

s1, providing a substrate 010, wherein the substrate 010 comprises an interconnection layer 011 and a passivation layer 013 covering the interconnection layer 011;

s2, forming a first electric conductor 020 connected to the interconnection layer 011 on the passivation layer 013, wherein the surface of the first electric conductor 020 is flush with the surface of the passivation layer 013;

s3, forming a second conductor 040 on the first conductor 020, the second conductor 040 having an elongated columnar shape.

Specifically, each step of the method for manufacturing a semiconductor structure is described in detail below with reference to fig. 1 to 13.

Referring to fig. 3, first, in step S1, the substrate 010 may include a semiconductor substrate, such as a silicon, gallium arsenide, gallium nitride, and/or silicon carbide substrate, which may include electronic devices thereon, such as transistors, diodes, resistors, capacitors, and/or inductors. The substrate herein may refer to a wafer having a plurality of semiconductor structures thereon, or may refer to an integrated circuit chip having a single semiconductor structure thereon. In this embodiment, the substrate may be a substrate including a metal-oxide-semiconductor field effect transistor (MOS transistor). The substrate 010 further includes an interconnect layer 011, a third electrical conductor 012, and a passivation layer 013 covering the interconnect layer 011 and the third electrical conductor 012, wherein the interconnect layer 011 can be electrically and/or mechanically connected to another substrate through a conductive material. The interconnect layer 011 may include, for example, a conductive metal such as copper or aluminum. The third conductor 012 may be formed on the interconnect layer 011 or may be led out from the same metal layer as the interconnect layer 011, in this embodiment, the third conductor 012 is formed on a part of the interconnect layer 011 and connected to the interconnect layer 011, the third conductor 012 may include a conductive metal such as aluminum, and the height of the third conductor 012 may be, for example, 50 μm to 200 μm. The third conductive body 012 can be electrically connected to the substrate directly or through the interconnect layer 011, the third conductive body 012 can be used for inputting/outputting to an electronic device including the substrate, in some embodiments, the third conductive body 012 can be used as a pad for subsequent soldering, in other embodiments, the third conductive body 012 can further provide a fuse, the fuse can be obtained by mechanical method or cutting with laser, the fuse can provide coupling/decoupling for redundant circuits on the substrate, and in other embodiments, the third conductive body 012 can further provide a pad for detecting circuits on the substrate. In this embodiment, the third conductor 012 is used as a connection terminal for inputting/outputting to/from an electronic device including a substrate. A passivation layer 013 can be formed on the interconnect layer 011 and the third conductive body 012 by sputtering, evaporation, and/or chemical vapor deposition, wherein the passivation layer 013 can include an inorganic material such as silicon dioxide and/or silicon nitride, the passivation layer 013 can also include an organic material such as tetraethoxysilane and/or polyimide, in this embodiment, the passivation layer 013 adopts tetraethoxysilane, specifically, phosphorus-doped tetraethoxysilane (PTEOS) or borophosphosilicate tetraethoxysilane (BPTEOS), and the passivation layer 013 covers the interconnect layer 011 and the third conductive body 012.

Referring to fig. 4 and 5, in step S2, a first conductive body 020 connected to the interconnect layer 011 is formed on the passivation layer 013, a surface of the first conductive body 020 is flush with a surface of the passivation layer 013, the first conductive body 020 can be, for example, W, TiW, TiN and/or a combination thereof, and a diameter of the first conductive body 020 is, for example, 0.5 μm to 10 μm. The number of the first conductors 020 may be one, and as shown in fig. 4 and 5, in another embodiment, the number of the first conductors 020 may be plural, and the pitch (distance between adjacent edges) of the adjacent first conductors 020 may be, for example, 1 μm to 5 μm.

The specific process for preparing the first electric conductor 020 can include the following steps: specifically, in this embodiment, a first patterned photoresist layer 060 may be formed on the passivation layer 013, the first patterned photoresist layer 060 exposes a portion of the passivation layer 013, and the position of the first electrical conductor 020 is defined by the first patterned photoresist layer 060, and the position corresponds to the position of the interconnect layer 011. In this embodiment, the passivation layer 013 can be etched, e.g., using a reactive ion etching or plasma etching process, to expose the surface material of the interconnect layer 011.

Referring to fig. 4 and 5, in step S2, in some embodiments, a photoresist layer may be formed on the passivation layer 013 by, for example, a spin coating method, an exposure and development process is performed to form an opening on the photoresist layer to obtain a first patterned photoresist layer 060, the passivation layer 013 under the opening pattern is removed by using the first patterned photoresist layer 060 as a mask until a surface material of the interconnect layer 011 is exposed to form a hole connected to the interconnect layer 011, and then the photoresist layer may be removed by an ashing method.

Referring to fig. 4 and 5, in step S2, a conductive material, such as W, TiW, TiN and/or a combination thereof, is deposited on the surface of the passivation layer 013 by using a high density plasma chemical vapor deposition method to fill the holes, and then the excess conductive material is removed, such as by chemical mechanical polishing, so that the upper surface of the conductive material in the holes is flush with the upper surface of the passivation layer 013, thereby forming a first conductive body 020.

Referring to fig. 6-12, in step S3, a second conductor 040 is formed over the first conductor 020, the second conductor 040 may include, for example, copper, the diameter of the second conductor 040 may be equal to the diameter of the first conductor 020, and in some embodiments, the diameter of the second conductor 040 may be smaller than the diameter of the first conductor 020. The number of the second conductors 040 may be one or plural, and as shown in fig. 10 to 12, when the diameter of the second conductors 040 is smaller than the diameter of the first conductors 020, the pitch between adjacent second conductors 040 (distance between adjacent edges) is, for example, 2 μm to 10 μm. The specific process for preparing the second electrical conductor 040 may include the steps of: coating a first barrier layer 030 on the surface of a passivation layer 013 and a first conductor 020, the first barrier layer 030 is, for example, a photosensitive material, specifically, in this embodiment, for example, a liquid polyimide layer is spin-coated on the surface of the passivation layer 013 and the surface of the first conductor 020, the liquid polyimide layer is heated and dried at a temperature ranging from 150 ° to 250 ° to form a solid polyimide layer, since the polyimide belongs to the photosensitive material, the solid polyimide layer can be directly dry etched without performing processes such as exposure, development, and the like, in this embodiment, for example, an opening is formed in the solid polyimide layer at a position corresponding to the first conductor 020 by using a laser etching method, and then a metal material is deposited on the solid polyimide layer by methods such as sputtering, evaporation, and/or chemical vapor deposition to fill the opening, in this embodiment, for example, a copper-containing metal is deposited on the solid polyimide layer by a high density plasma chemical vapor deposition method, the deposited copper-containing metal fills the opening, then, the excess copper-containing metal is removed by, for example, chemical mechanical polishing, so that the upper surface of the copper-containing metal in the opening is flush with the upper surface of the solid polyimide layer, the first barrier layer 030, i.e., the solid polyimide layer, is removed by wet etching until the passivation layer 013 is exposed, and the second electric conductor 040 protruding the passivation layer 013 is formed on the first electric conductor 020 by the above process, in this embodiment, the second electric conductor 040 having a columnar structure is formed by controlling the shape of the opening on the solid polyimide layer. The first conductor 020 formed in step S2 may connect the second conductor 040 to the interconnect layer 011, and the first conductor 020 may realize signal electrical transmission between the second conductor 040 and the substrate.

Referring to fig. 6 to 12, in step S3, a portion of the passivation layer 013 is removed to expose the third conductor 012. Specifically, in this embodiment, a second patterned photoresist layer 070 covering the second conductor 040 may be formed on the passivation layer 013 and the second conductor 040, and the second patterned photoresist layer 070 exposes a portion of the passivation layer 013, and the pattern of the photoresist layer corresponds to the position of the third conductor 012. In this embodiment, the passivation layer 013 may be etched by using a reactive ion etching or plasma etching process, for example, until the third conductive body 012 stops to expose the third conductive body 012, and in some embodiments, when the passivation layer is etched to the third conductive body 012, the passivation layer is continuously etched to a certain depth to ensure the quality of the later electrical connection of the third conductive body 012.

Referring to fig. 6 to 12, in step S3, in some embodiments, a photoresist layer may be formed on the passivation layer 013 by, for example, a spin coating method, a groove is formed on the photoresist layer through exposure and development processes to obtain a second patterned photoresist layer 070, the passivation layer 013 under the groove pattern is removed by using the second patterned photoresist layer 070 as a mask until the surface material of the third conductive body 012 is exposed, and then the photoresist layer may be removed by an ashing method. The recess in passivation layer 013 can expose a portion of third electrical conductor 012, which third electrical conductor 012 can be used later as an input/output terminal for an electronic device or later used for inspection, cutting, and/or as a bond pad.

Referring to fig. 13, in another step, a conductive bump 050 is formed over second conductor 040, and second conductor 040 is inserted into conductive bump 050. In this embodiment, conductive bumps 050 can be formed on the surfaces and the side surfaces of second conductor 040 by maskless electroplating or other deposition techniques, so that second conductor 040 can be inserted into conductive bumps 050, for example, the conductive bumps 050 can include tin solder, in other embodiments, the conductive bumps 050 can further include nickel, gold, and/or copper, and in this embodiment, the conductive bumps 050 can include tin solder. The conductive bumps 050 can have various shapes, in this embodiment, the conductive bumps 050 are, for example, spherical, and specifically, the formed conductive bumps 050 can be melted and reflowed to form spheres. The conductive bump 050, the second conductor 040 and the first conductor 020 form a conductive path to be connected with the interconnection layer 011, so that the conductive bump is electrically coupled with the substrate. In other embodiments, a protective layer may be formed on the third conductor 012 and the second conductor 040 to prevent the third conductor 012 and the second conductor 040 from being oxidized, and specifically, a resin layer may be formed on the third conductor 012 and the second conductor 040 by, for example, chemical coating or deposition to prevent the third conductor 012 and the second conductor 040 from being oxidized.

Referring to fig. 13, in step S4, under the condition that the third conductive body 012 is exposed, the conductive bumps 050 can be electrically and/or mechanically coupled to another substrate, such as another integrated circuit semiconductor device and/or a printed circuit board. After forming the conductive bumps 050 and/or soldering the conductive bumps 050 to another substrate in this way, the third conductor 012 may be used as an input/output terminal, or the third conductor 012 may be burned, cut, inspected, and/or soldered.

Referring to fig. 1 to 13, in step S1 to S4, the second conductive bodies 040 are in a cylindrical shape and are connected to the conductive bumps 050 in an inserting manner, so that the distance between the second conductive bodies 040 is reduced, the contact area between the second conductive bodies 040 and the conductive bumps 050 is not affected, the contact area between the second conductive bodies 040 and the conductive bumps 050 can be further increased, the bonding force between the conductive bumps 050 and the second conductive bodies 040 is increased, and the performance of the semiconductor device is ensured under the condition that the size of the semiconductor device is reduced.

The above disclosure of selected embodiments of the invention is intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.