阅读说明：本技术 一种层叠式半导体封装结构 (Laminated semiconductor packaging structure ) 是由 潘芹兰 于 2021-08-20 设计创作，主要内容包括：本发明公开了一种层叠式半导体封装结构,涉及半导体封装技术领域,针对半导体封装单元较多,在封装时不能满足小型化的需求,对装配半导体之后的使用可靠性不高,在装配时工作效率较低等问题,现提出如下方案,包括主基板,所述主基板的顶部焊接有多个支撑座,所述支撑座远离主基板的一端焊接有第一副基板,所述第一副基板的顶部焊接有多个支撑座。本发明设计巧妙,结构简单,提高工作效率,添加的连接垫可方便对半导体层叠之间的电连接,添加的焊垫可方便电子单元装配在基板上,添加的焊球可满足不同的电子单元在基板上的装配,添加的支撑座可对层叠的基板进行保护,防止损坏,该装置方便使用,实用性强,便于推广。(The invention discloses a laminated semiconductor packaging structure, relates to the technical field of semiconductor packaging, and aims at the problems that a plurality of semiconductor packaging units are available, the requirement for miniaturization cannot be met during packaging, the reliability of use after a semiconductor is assembled is not high, the working efficiency is low during assembly and the like. The semiconductor stacking device is ingenious in design, simple in structure and high in working efficiency, the added connecting pads can be used for conveniently electrically connecting semiconductor stacks, the added welding pads can be used for conveniently assembling electronic units on the substrate, the added welding balls can meet the requirements of assembling different electronic units on the substrate, the added supporting seat can be used for protecting the stacked substrates to prevent damage, and the semiconductor stacking device is convenient to use, high in practicability and convenient to popularize.)

1. The utility model provides a stacked semiconductor package structure, includes main substrate (1), the top welding of main substrate (1) has a plurality of supporting seats (2), the one end welding that main substrate (1) was kept away from in supporting seat (2) has first sub-base plate (4), the top welding of first sub-base plate (4) has a plurality of supporting seats (2), the top welding of supporting seat (2) has the sub-base plate of second (5), its characterized in that, main substrate (1) includes first main connecting pad (101), second main connecting pad (102), first main welding pad (103), first chip (104), second main welding pad (105), first main solder ball (106), first chip (104) welding is on first main welding pad (103), first main solder ball (106) welding is on second main welding pad (105).

2. The stacked semiconductor package structure of claim 1, wherein the first sub-substrate (4) comprises a first sub-bonding pad (401), a second sub-bonding pad (402), a first sub-bonding pad (403), a second chip (404), a third sub-bonding pad (405), a fourth sub-bonding pad (406), a second sub-solder ball (407), and a second sub-bonding pad (408), the second sub-solder ball (407) is bonded on the second sub-bonding pad (408), and the second chip (404) is bonded on the first sub-bonding pad (403).

3. The stacked semiconductor package structure of claim 1, wherein the main substrate (1) is provided with a first main connecting pad (101) and a second main connecting pad (102), the first sub-substrate (4) is provided with a first sub-connecting pad (401) and a second sub-connecting pad (402), the first main connecting pad (101), the second main connecting pad (102), the first sub-connecting pad (401) and the second sub-connecting pad (402) are connected by a first connecting wire (3), and the first connecting wire (3) is electrically conductive.

4. The stacked semiconductor package structure of claim 1, wherein the second sub-substrate (5) comprises a third sub-solder ball (501), a third chip (502), a third sub-pad (503), a fifth sub-connection pad (504), a sixth sub-connection pad (505), and a fourth sub-pad (506), the third sub-solder ball (501) is soldered on the fourth sub-pad (506), and the third chip (502) is soldered on the third sub-pad (503).

5. The stacked semiconductor package structure of claim 1, wherein a third sub-bonding pad (405) and a fourth sub-bonding pad (406) are disposed on the first sub-substrate (4), a fifth sub-bonding pad (504) and a sixth sub-bonding pad (505) are disposed on the second sub-substrate (5), the third sub-bonding pad (405), the fourth sub-bonding pad (406), the fifth sub-bonding pad (504), and the sixth sub-bonding pad (505) are all connected by a second connection line (6), and the second connection line (6) has electrical conductivity.

6. The stacked semiconductor package structure of claim 1, wherein a first main pad (103) provided on the main substrate (1) facilitates soldering of the first chip (104), and a second main pad (105) provided on the main substrate (1) facilitates soldering of the first main solder ball (106).

7. The stacked semiconductor package structure of claim 1, wherein the supporting base (2) comprises an upper supporting plate (201), a spring (202), a sphere (203), and a lower supporting plate (204), the spring (202) is welded to the bottom of the upper supporting plate (201), the lower supporting plate (204) is welded to the other end of the spring (202), the sphere (203) is welded to the bottom of the upper supporting plate (201), the other end of the sphere (203) is welded to the top of the lower supporting plate (204), the spring (202) is located inside the sphere (203), and the sphere (203) has extensibility.

8. The stacked semiconductor package structure of claim 1, wherein the supporting base (2) is capable of protecting the main substrate (1) and the first sub-substrate (4) and the second sub-substrate (5), and the supporting base (2) is made to expand and contract when the first sub-substrate (4) and the second sub-substrate (5) receive the compression, so as to protect the main substrate (1) and the first sub-substrate (4) and the second sub-substrate (5).

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a laminated semiconductor packaging structure.

Background

The semiconductor is a material with electric conductivity between a conductor and an insulator at normal temperature, and has applications in the fields of integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, high-power conversion and the like, and the importance of the semiconductor is very great from the viewpoint of science and technology or economic development, and most of electronic products, such as computers, mobile phones or digital recorders, have close relationship with the semiconductor in terms of core units.

In the conventional semiconductor package structure, since the semiconductor needs to continuously satisfy the requirements for miniaturization and assembly efficiency, the conventional semiconductor package has many units, the conventional semiconductor package cannot satisfy the requirements for miniaturization, and the conventional semiconductor package has low reliability in use after the semiconductor is assembled, low work efficiency in assembly, and the like.

Disclosure of Invention

Objects of the invention

In order to solve the technical problems existing in the background technology, the invention provides a laminated semiconductor packaging structure, the device is ingenious in design and simple in structure, the working efficiency is improved, the reliability and the safety of semiconductor implementation are ensured, the added connecting pads can conveniently electrically connect the semiconductor lamination, the added welding pads can conveniently assemble electronic units on a substrate, the added welding balls can meet the assembly of different electronic units on the substrate, the added supporting seat can protect the laminated substrate to prevent damage, and the device is convenient to use, strong in practicability and convenient to popularize.

(II) technical scheme

The invention provides a stacked semiconductor packaging structure which comprises a main substrate, wherein a plurality of supporting seats are welded at the top of the main substrate, a first auxiliary substrate is welded at one end, away from the main substrate, of each supporting seat, a plurality of supporting seats are welded at the top of the first auxiliary substrate, a second auxiliary substrate is welded at the top of each supporting seat, the main substrate comprises a first main connecting pad, a second main connecting pad, a first main welding pad, a first chip, a second main welding pad and a first main welding ball, the first chip is welded on the first main welding pad, and the first main welding ball is welded on the second main welding pad.

Preferably, the first secondary substrate comprises a first secondary connection pad, a second secondary connection pad, a first secondary welding pad, a second chip, a third secondary connection pad, a fourth secondary connection pad, a second secondary welding ball and a second secondary welding pad, the second secondary welding ball is welded on the second secondary connection pad, and the second chip is welded on the first secondary connection pad.

Preferably, a first main connecting pad and a second main connecting pad are arranged on the main substrate, a first auxiliary connecting pad and a second auxiliary connecting pad are arranged on the first auxiliary substrate, the first main connecting pad, the second main connecting pad, the first auxiliary connecting pad and the second auxiliary connecting pad are all connected through a first connecting wire, and the first connecting wire is conductive.

Preferably, the second sub-substrate includes a second sub-solder ball, a third chip, a second sub-pad, a fifth sub-pad, a sixth sub-pad, and a fourth sub-pad, the third sub-solder ball is welded on the fourth sub-pad, and the third chip is welded on the third sub-pad.

Preferably, the first secondary substrate is provided with a third secondary connecting pad and a fourth secondary connecting pad, the second secondary substrate is provided with a fifth secondary connecting pad and a sixth secondary connecting pad, the third secondary connecting pad, the fourth secondary connecting pad, the fifth secondary connecting pad and the sixth secondary connecting pad are all connected through a second connecting wire, and the second connecting wire has electrical conductivity.

Preferably, the first main pad arranged on the main substrate facilitates welding of the first chip, and the second main pad arranged on the main substrate facilitates welding of the first main solder ball.

Preferably, the supporting seat includes backup pad, spring, spheroid, bottom suspension fagging, the bottom welding of going up the backup pad has the spring, the other end welding of spring has the bottom suspension fagging, the bottom welding of going up the backup pad has the spheroid, the top welding of spheroidal other end and bottom suspension fagging, the spring is located spheroidal inside, the spheroid has the extensibility.

Preferably, the support seat can protect the main substrate, the first sub-substrate and the second sub-substrate, and the support seat can stretch and contract when the first sub-substrate and the second sub-substrate receive the extrusion, so as to protect the main substrate, the first sub-substrate and the second sub-substrate.

Compared with the prior art, the technical scheme of the invention has the following beneficial technical effects:

the device design benefit, simple structure improves work efficiency, guarantees reliability and the security that the semiconductor was implemented, and the connection pad of interpolation can conveniently be connected the electricity between the semiconductor range upon range of, and the pad of interpolation can make things convenient for the electronic unit to assemble on the base plate, and the welded ball of interpolation can satisfy the assembly of different electronic units on the base plate, and the base plate of interpolation can be protected, prevents to damage, and the device facilitates the use, and the practicality is strong, the facilitate promotion.

Drawings

Fig. 1 is a schematic three-dimensional structure diagram of a stacked semiconductor package structure according to the present invention.

Fig. 2 is a schematic three-dimensional structure of a main substrate of a stacked semiconductor package structure according to the present invention.

Fig. 3 is a schematic three-dimensional structure diagram of a first sub-substrate of a stacked semiconductor package structure according to the present invention.

Fig. 4 is an enlarged schematic view of a portion a of the stacked semiconductor package structure shown in fig. 1 according to the present invention.

Fig. 5 is a schematic view of an internal structure of a support base of a stacked semiconductor package structure according to the present invention.

Reference numerals: 1. a main substrate; 2. a supporting seat; 3. a first connecting line; 4. a first sub-substrate; 5. a second sub-substrate; 6. a second connecting line; 101. a first main connection pad; 102. a second main connection pad; 103. a first main pad; 104. a first chip; 105. a second main pad; 106. a first main solder ball; 201. an upper support plate; 202. a spring; 203. a sphere; 204. a lower support plate; 401. a first secondary connection pad; 402. a second secondary connection pad; 403. a first sub pad; 404. a second chip; 405. a third secondary connection pad; 406. a fourth secondary connection pad; 407. a second sub-solder ball; 408. a second sub-pad; 501. a third pair of solder balls; 502. a third chip; 503. a third sub pad; 504. a fifth secondary connection pad; 505. a sixth secondary connection pad; 506. a fourth sub-pad.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

As shown in fig. 1-5, a stacked semiconductor package structure according to the present invention comprises a main substrate 1, a plurality of supporting bases 2 welded to the top of the main substrate 1, a first sub-substrate 4 welded to one end of each supporting base 2 away from the main substrate 1, a plurality of supporting bases 2 welded to the top of each first sub-substrate 4, a second sub-substrate 5 welded to the top of each supporting base 2, the main substrate 1 comprising a first main connecting pad 101, a second main connecting pad 102, a first main bonding pad 103, and a first chip 104, the second main welding pad 105, the first main welding ball 106, the first chip 104 is welded on the first main welding pad 103, the first main welding ball 106 is welded on the second main welding pad 105, the added support base 2 can protect the main substrate 1, the first auxiliary substrate 4 and the second auxiliary substrate 5, and the packaged chip can be prevented from being damaged when the main substrate 1, the first auxiliary substrate 4 and the second auxiliary substrate 5 are extruded.

The first sub-substrate 4 comprises a first sub-connection pad 401, a second sub-connection pad 402, a first sub-pad 403, a second chip 404, a third sub-connection pad 405, a fourth sub-connection pad 406, a second sub-solder ball 407, and a second sub-pad 408, the second sub-solder ball 407 is soldered on the second sub-pad 408, the second chip 404 is soldered on the first sub-pad 403, the main substrate 1 is provided with a first main connection pad 101 and a second main connection pad 102, the first sub-substrate 4 is provided with a first sub-connection pad 401 and a second sub-connection pad 402, the first main connection pad 101, the second main connection pad 102, the first sub-connection pad 401, and the second sub-connection pad 402 are all connected through a first connection wire 3, the first connection wire 3 has conductivity, the second sub-substrate 5 comprises a second sub-solder ball 501, a third chip 502, a second sub-pad 503, a fifth sub-connection pad 504, a sixth sub-connection pad 505, and a fourth sub-pad 506, the third sub solder ball 501 is welded on the fourth sub solder pad 506, the third chip 502 is welded on the third sub solder pad 503, the first sub substrate 4 is provided with a third sub connecting pad 405 and a fourth sub connecting pad 406, the second sub substrate 5 is provided with a fifth sub connecting pad 504 and a sixth sub connecting pad 505, the third sub connecting pad 405, the fourth sub connecting pad 406, the fifth sub connecting pad 504 and the sixth sub connecting pad 505 are all connected through a second connecting wire 6, the second connecting wire 6 has conductivity, the added first connecting wire 3 and the added second connecting wire 6 can realize the electric connection among the semiconductor stacks, and meanwhile, the added solder pads on the main substrate 1, the first sub substrate 4 and the second sub substrate 5 can facilitate the packaging of the chip and the assembly of the solder balls.

The welding of the first chip 104 is made things convenient for to the first main pad 103 that sets up on the primary substrate 1, the welding of the first main solder ball 106 of second main pad 105 that sets up on the primary substrate 1 makes things convenient for, supporting seat 2 includes backup pad 201, spring 202, spheroid 203, bottom suspension fagging 204, the bottom welding of going up backup pad 201 has spring 202, bottom suspension fagging 204 has been welded to the other end of spring 202, the bottom welding of going up backup pad 201 has spheroid 203, the other end of spheroid 203 and the top welding of bottom suspension fagging 204, spring 202 is located the inside of spheroid 203, spheroid 203 has the extensibility, supporting seat 2 can play the guard action to primary substrate 1 and first sub-base plate 4 and the vice base plate 5 of second, make supporting seat 2 produce flexible when receiving the extrusion at first sub-base plate 4 and the vice base plate 5 of second, can protect primary substrate 1 and first sub-base plate 4 and the vice base plate 5 of second.

In the present invention, first, a first connecting wire 3 is soldered to a first main connecting pad 101 and a second main connecting pad 102 mounted on a main substrate 1, then, the other end of the first connecting wire 3 is soldered to a first sub-connecting pad 401 and a second sub-connecting pad 402 of a first sub-substrate 4, so that the main substrate 1 is electrically connected to the first sub-substrate 4, then, a third sub-connecting pad 405 and a fourth sub-connecting pad 406 on the first sub-substrate 4 are soldered to a second connecting wire 6, then, the other end of the second connecting wire 6 is soldered to a fifth sub-connecting pad 504 and a sixth sub-connecting pad 505 on a second sub-substrate 5, so that the first sub-substrate 4 is electrically connected to the second sub-substrate 5, so that the main substrate 1, the first sub-substrate 4 and the second sub-substrate 5 are electrically connected to each other through the first connecting wire 3 and the second connecting wire 6, and at the same time, the first main pad 103 is disposed on the main substrate 1, can make things convenient for first chip 104 to weld with it, because need weld on the primary substrate 1 to a first chip 104, the welding speed of first chip 104 can be improved to first main solder pad 103 that sets up on primary substrate 1, and simultaneously, the second main solder pad 105 that sets up on primary substrate 1, can make things convenient for the welding of first main solder ball 106, because need have a plurality of first main solder balls 106 on the second main solder pad 105, and in the same way, can improve the welding speed of first main solder ball 106, thereby the time has been saved, on first sub-base plate 4 and the second sub-base plate 5 based on same setting, thereby the welding speed of the chip that improves on the whole.

Since the semiconductor is packaged in a stacked manner, a pressing condition may be encountered during the stacked manner, so that the main substrate 1, the first sub-substrate 4 and the second sub-substrate 5 are pressed against each other, and the chip to be soldered is damaged, at this time, the support seat 2 is disposed between the first main substrate 1, the first sub-substrate 4 and the second sub-substrate 5, when the first main substrate 1, the first sub-substrate 4 and the second sub-substrate 5 are pressed, the upper support plate 201 is pressed, when the upper support plate 201 is pressed, the spring 202 and the ball 203 are pressed against the lower support plate 204, and since the spring 202 and the ball 203 have a telescopic function, the pressing pressure applied to the first main substrate 1, the first sub-substrate 4 and the second sub-substrate 5 can be relieved, thereby protecting the first main substrate 1, the second sub-substrate 5, and the first main substrate 1, A first sub-substrate 4 and a second sub-substrate 5.

It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such changes and modifications that fall within the scope and bounds of the appended claims, or equivalents of such scope and bounds.