阅读说明：本技术 集成电路装置 (Integrated circuit device ) 是由 王奎 周猛 于 2021-09-15 设计创作，主要内容包括：一种集成电路装置。所述集成电路装置包括载板、胶层以及集成电路芯片。所述胶层涂覆于所述载板之上,其中所述胶层包括铜浆,所述胶层的厚度在5-35微米的范围,所述铜浆的粘度系数在10000-30000cPs的范围,所述铜浆的触变指数在1.5-3的范围。所述集成电路芯片通过所述胶层粘接于所述载板之上。(An integrated circuit device. The integrated circuit device comprises a carrier plate, an adhesive layer and an integrated circuit chip. The adhesive layer is coated on the carrier plate, wherein the adhesive layer comprises copper paste, the thickness of the adhesive layer is in the range of 5-35 microns, the viscosity coefficient of the copper paste is in the range of 10000-30000cPs, and the thixotropic index of the copper paste is in the range of 1.5-3. The integrated circuit chip is bonded on the carrier plate through the adhesive layer.)

1. An integrated circuit device, comprising:

a carrier plate;

the adhesive layer is coated on the carrier plate, the adhesive layer comprises copper paste, the thickness of the adhesive layer is in the range of 5-35 microns, the viscosity coefficient of the copper paste is in the range of 10000-30000cPs, and the thixotropic index of the copper paste is in the range of 1.5-3; and

and the integrated circuit chip is bonded on the carrier plate through the adhesive layer.

2. The integrated circuit device of claim 1, wherein the copper paste is a polymeric oxidation resistant copper paste.

3. The integrated circuit device of claim 1, wherein the copper paste comprises nano oxidation-resistant copper powder.

4. The integrated circuit device of claim 1, wherein the viscosity coefficient of the copper paste is 15880 cPs.

5. The integrated circuit device of claim 1, wherein the thixotropic index of the copper paste is 2.12.

6. The integrated circuit device of claim 1, wherein the thermal conductivity of the glue layer is greater than 15W/m-K.

7. The integrated circuit device of claim 1, wherein the glue layer has a thickness in the range of 15-35 microns.

8. The integrated circuit device of claim 1, wherein the integrated circuit chip has a thickness greater than 200 microns, and wherein the glue layer has an overflow height in a range of 20% -80% of the thickness of the integrated circuit chip.

9. The integrated circuit device of claim 1, wherein the integrated circuit chip has a thickness greater than 200 microns, and wherein the glue layer has an overflow height in a range of 40% -60% of the thickness of the integrated circuit chip.

10. The integrated circuit device as claimed in claim 1, wherein the thickness of the integrated circuit chip is in the range of 100-200 μm, and the overflow height of the glue layer is in the range of 20-90% of the thickness of the integrated circuit chip.

11. The integrated circuit device as claimed in claim 1, wherein the thickness of the integrated circuit chip is in the range of 100-200 μm, and the overflow height of the glue layer is in the range of 30-80% of the thickness of the integrated circuit chip.

12. The integrated circuit device of claim 1, wherein the integrated circuit chip has a thickness of less than 100 microns, and wherein the glue layer has an overflow height that is less than the thickness of the integrated circuit chip.

13. The integrated circuit device of claim 1, wherein the integrated circuit chip has a thickness of less than 100 microns, and wherein the glue layer has an overflow height of less than 95% of the thickness of the integrated circuit chip.

14. The integrated circuit device of claim 1, wherein the size of the integrated circuit chip is less than or equal to 2 mm by 2 mm, and a chip tilt of the integrated circuit chip placed on the glue layer is less than 10 microns.

15. The integrated circuit device of claim 1, wherein the size of the integrated circuit chip is less than or equal to 2 mm by 2 mm, and a chip tilt of the integrated circuit chip placed on the glue layer is less than 7 microns.

16. The integrated circuit device of claim 1, wherein the size of the integrated circuit chip is greater than 2 mm by 2 mm, and the chip pitch of the integrated circuit chip placed on the glue layer is less than 20 microns.

17. The integrated circuit device of claim 1, wherein the size of the integrated circuit chip is greater than 2 mm by 2 mm, and the chip pitch of the integrated circuit chip placed on the glue layer is less than 15 microns.

Technical Field

The present application relates generally to devices, and more particularly, to integrated circuit devices.

Background

In the current semiconductor packaging process, a common silver paste is generally used for performing a die bonding process to complete soldering. However, the silver paste may have a risk of cracking after baking, and when some materials are used to make a carrier (e.g., a lead frame), the color of the silver paste is similar to the color of the carrier, so that the position of the silver paste on the carrier cannot be identified.

Disclosure of Invention

In view of the above, the present application provides an integrated circuit device to solve the above problems.

According to an embodiment of the present application, an integrated circuit device is provided. The integrated circuit device comprises a carrier plate, an adhesive layer and an integrated circuit chip. The adhesive layer is coated on the carrier plate, wherein the adhesive layer comprises copper paste, the thickness of the adhesive layer is in the range of 5-35 microns, the viscosity coefficient of the copper paste is in the range of 10000-30000cPs, and the thixotropic index of the copper paste is in the range of 1.5-3. The integrated circuit chip is bonded on the carrier plate through the adhesive layer.

According to an embodiment of the present application, the copper paste is a polymer antioxidant copper paste.

According to an embodiment of the present application, the copper paste includes nano oxidation-resistant copper powder.

According to an embodiment of the present application, the viscosity coefficient of the copper paste is 15880 cPs.

According to an embodiment of the present application, the thixotropic index of the copper paste is 2.12.

According to an embodiment of the present application, the thermal conductivity of the glue layer is greater than 15W/m.k.

According to an embodiment of the application, the thickness of the glue layer is in the range of 15-35 microns.

According to an embodiment of the present application, the thickness of the integrated circuit chip is greater than 200 micrometers, and the overflow height of the glue layer is in a range of 20% -80% of the thickness of the integrated circuit chip.

According to an embodiment of the present application, the thickness of the integrated circuit chip is greater than 200 micrometers, and the overflow height of the glue layer is in a range of 40% -60% of the thickness of the integrated circuit chip.

According to an embodiment of the present application, the thickness of the integrated circuit chip is in the range of 100-200 μm, and the overflow height of the glue layer is in the range of 20% -90% of the thickness of the integrated circuit chip.

According to an embodiment of the present application, the thickness of the integrated circuit chip is in the range of 100-200 μm, and the overflow height of the glue layer is in the range of 30% -80% of the thickness of the integrated circuit chip.

According to an embodiment of the present application, the thickness of the integrated circuit chip is less than 100 micrometers, and the overflow height of the glue layer is less than the thickness of the integrated circuit chip.

According to an embodiment of the present application, the thickness of the integrated circuit chip is less than 100 micrometers, and the overflow height of the glue layer is less than 95% of the thickness of the integrated circuit chip.

According to an embodiment of the present application, the size of the ic chip is less than or equal to 2 mm x 2 mm, and the chip tilt of the ic chip placed on the adhesive layer is less than 10 μm.

According to an embodiment of the present application, the size of the ic chip is less than or equal to 2 mm x 2 mm, and the chip tilt of the ic chip placed on the adhesive layer is less than 7 μm.

According to an embodiment of the present application, the size of the ic chip is greater than 2 mm by 2 mm, and the chip tilt of the ic chip placed on the adhesive layer is less than 20 μm.

According to an embodiment of the present application, the size of the ic chip is greater than 2 mm by 2 mm, and the chip tilt of the ic chip placed on the adhesive layer is less than 15 μm.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:

FIG. 1 illustrates a side view of an integrated circuit device according to one embodiment of the present application.

FIG. 2 illustrates a side view of an integrated circuit device according to another embodiment of the present application.

Detailed Description

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.

FIG. 1 illustrates a side view of an integrated circuit device 1 according to an embodiment of the present application. In some embodiments, the integrated circuit device 1 includes a carrier 11, a glue layer 12, and an integrated circuit chip 13. In some embodiments, the carrier 11 may be a lead frame, a substrate, a PCB, etc. In some embodiments, the carrier 11 (e.g., the lead frame) may be made of ni-pd-au, pure copper or ag-cu, which should not be construed as a limitation. In some embodiments, the integrated circuit chip 13 is adhered to the carrier 11 by the adhesive layer 12. In some embodiments, the integrated circuit chip 13 may be a chip with a substrate made of silicon carbide, nitrogen carbide or silicon material, which is not limited herein.

In some embodiments, the glue layer 12 is coated on the carrier 11. In certain embodiments, the bondline 12 comprises a copper paste composed of at least copper powder, a binder, and a monomer. In some embodiments, the copper paste may be a polymer antioxidant copper paste, the copper powder may be nano antioxidant copper powder, and the use of the polymer antioxidant copper paste can overcome the defect of easy oxidation of copper.

In certain embodiments, the viscosity index of the copper slurry is in the range of 10000-. In certain embodiments, the viscosity coefficient of the copper paste is 15880 cPs. In certain embodiments, the thixotropic index of the copper paste is in the range of 1.5 to 3. In certain embodiments, the thixotropic index of the copper paste is 2.12. It should be noted that the present application is not limited to the manner of manufacturing the copper paste.

In certain embodiments, the thermal conductivity of the bondline 12 is greater than 15W/m.K. In some embodiments, the thickness D12 of the adhesive layer 12 is in the range of 5-35 μm, so that the product has better thermal conductivity, electrical conductivity and shear strength, the thermal conductivity of the product reaches 15W/m.k, the specific resistance of the product is less than or equal to 1.0 × 10-4 Ω cm, and the shear strength (also called the push test thrust value) of the product is greater than 2.5kg, wherein the shear strength is a test data of separating the integrated circuit chip from the carrier plate by applying a thrust to the integrated circuit chip by a special push crystal device after the integrated circuit chip and the carrier plate 11 are bonded and cured by the adhesive layer in order to verify the bonding effect.

Through research and development experiments of the applicant, the integrated circuit chip is inclined when the thickness of the adhesive layer is more than 35 microns.

In some embodiments, the thickness D12 of the bondline 12 is in the range of 25 microns ± 10 microns, i.e. in the range of 15-35 microns.

It should be noted that the shape of the glue layer 12 shown in fig. 1 is merely an example. It will be understood by those skilled in the art that when the ic chip 13 is bonded to the carrier 11 through the adhesive layer 12, the adhesive layer 12 is deformed, and thus the protrusion height is generated. Fig. 2 illustrates a side view of an integrated circuit device 1' according to another embodiment of the present application. In some embodiments, the integrated circuit device 1 'is substantially the same as the integrated circuit device 1, except that the adhesive layer 12' included in the integrated circuit device 1 'is deformed due to the placement of the integrated circuit chip 13, and a portion of the adhesive layer 12' adheres to the side of the integrated circuit chip 13. The deformed glue line 12 'has an overflow height D12'. In some embodiments, the flash height D12 'of the glue layer 12' is related to the thickness D13 of the integrated circuit chip 13.

In some embodiments, when the thickness D13 of the ic chip 13 is greater than 200 μm, the height D12 'of the adhesive layer 12' is within 20% -80% of the thickness D13 of the ic chip 13, and less than 20% of the chip has voids, poor adhesion, and falling off, and more than 80% of the chip has copper adhesive spilling over the surface of the chip, which may cause poor wire bonding and short circuit. In some embodiments, when the thickness D13 of the ic chip 13 is greater than 200 μm, the height D12 'of the adhesive layer 12' is within a range of 40% to 60% of the thickness D13 of the ic chip 13, and the sticking within this range can better prevent the above-mentioned abnormality caused by poor control of the amount of adhesive, and simultaneously better ensure the thermal conductivity and electrical conductivity of the copper adhesive product, the thermal conductivity of the product reaches 15W/m.k, and the specific resistance of the product is less than or equal to 1.0 × 10-4 Ω cm.

In some embodiments, when the thickness D13 of the integrated circuit chip 13 is within the range of 100-200 μm, the overflow height D12 'of the adhesive layer 12' is within the range of 20% -90% of the thickness D13 of the integrated circuit chip 13, and less than 20% of the chip has voids, which are not firmly bonded and fall off, and more than 90% of the chip has the risk of copper adhesive overflowing to the chip surface, which may cause defects such as bad wire bonding and short circuit of the chip. In some embodiments, when the thickness D13 of the integrated circuit chip 13 is within the range of 100-200 μm, the protrusion height D12 'of the adhesive layer 12' is within the range of 30% -80% of the thickness D13 of the integrated circuit chip 13, and the control within this range can better prevent the above-mentioned abnormality caused by poor control of the adhesive amount, and simultaneously better ensure the heat conductivity and the electrical conductivity of the copper adhesive product, the heat conductivity of the product reaches 15W/m.k, and the specific resistance of the product is less than or equal to 1.0 × 10-4 Ω cm.

In some embodiments, when the thickness D13 of the ic chip 13 is less than 100 μm, the overflow height D12 'of the adhesive layer 12' is less than 100% of the thickness D13 of the ic chip 13 (i.e., less than the thickness D13 of the ic chip 13), and if the copper adhesive overflows to the surface of the ic chip more than 100%, the wire bonding is poor and the chip is short-circuited. In some embodiments, when the thickness D13 of the ic chip 13 is less than 100 μm, the height D12 'of the adhesive layer 12' is less than 95% of the thickness D13 of the ic chip 13, and the amount of the adhesive is controlled within this range, which can better prevent the above-mentioned abnormality caused by poor control of the amount of the adhesive, and can better ensure the thermal conductivity and the electrical conductivity of the copper adhesive product, the thermal conductivity of the product reaches 15W/m.k, and the specific resistance of the product is less than or equal to 1.0 × 10-4 Ω cm.

In some embodiments, when the size of the ic chip 13 is less than or equal to 2 mm x 2 mm, the tilt of the ic chip 13 placed on the adhesive layer 12 (or the adhesive layer 12') is less than 10 μm, so as to better control the abnormalities such as crystal floating and chip adhesion, and to better ensure the thermal conductivity of the copper paste product, so as to make the thermal conductivity more uniform. In some embodiments, when the size of the ic chip 13 is less than or equal to 2 mm x 2 mm, and the tilt of the ic chip 13 placed on the adhesive layer 12 (or the adhesive layer 12') is less than 7 μm, the chip is better prevented from floating, the chip is not firmly bonded, and the like, thereby ensuring the heat conductivity and the electrical conductivity of the copper adhesive product to a greater extent, the heat conductivity of the product reaches 15W/m.k, and the specific resistance of the product is less than or equal to 1.0 x 10-4 Ω cm.

In some embodiments, when the size of the ic chip 13 is greater than 2 mm by 2 mm, the tilt of the ic chip 13 placed on the adhesive layer 12 (or the adhesive layer 12') is less than 20 μm, so as to better control the abnormalities such as crystal floating and chip adhesion weakness, and to better ensure the thermal conductivity of the copper paste product, so that the thermal conductivity is more uniform. In some embodiments, when the size of the ic chip 13 is greater than 2 mm by 2 mm, the tilt of the ic chip 13 placed on the adhesive layer 12 (or the adhesive layer 12') is less than 15 μm, and the clamping control is within this range, thereby better preventing the abnormalities such as crystal floating and chip bonding, and ensuring the heat conduction and electrical conductivity of the copper adhesive product to a greater extent, the thermal conductivity of the product reaches 15W/m.k, and the specific resistance of the product is less than or equal to 1.0 × 10-4 Ω cm.

In some embodiments, the area of a single void on the bondline 12 (or bondline 12 ') is less than 2% of the area of the bondline 12 (or bondline 12 '), and the total void area is less than 15% of the area of the bondline 12 (or bondline 12 '). In some embodiments, the area of a single void on the bondline 12 (or bondline 12 ') is less than 1% of the area of the bondline 12 (or bondline 12 '), and the total void area is less than 5% of the area of the bondline 12 (or bondline 12 ').

After experiments, the applicant of the application finds that when the copper paste disclosed by the application is used for carrying out crystal bonding operation on an integrated circuit, no watermark phenomenon occurs after two hours after dispensing and after glue curing; moreover, even if the machine is stopped for 30 minutes, the glue dispensing needle can smoothly discharge glue, the shape and the position of the glue are not deviated or damaged, and the gelatin has good fluidity; in addition, the high-molecular anti-oxidation copper paste still has the glue performance after the glue is pasted within 2 hours after the glue is discharged.

As used herein, the terms "approximately," "substantially," "essentially," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ± 10%, ± 5%, ± 1%, or ± 0.5% of the given value or range. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints. The term "substantially coplanar" may refer to two surfaces located within a few micrometers (μm) along the same plane, e.g., within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm located along the same plane. When referring to "substantially" the same numerical value or property, the term can refer to values that are within ± 10%, ± 5%, ± 1%, or ± 0.5% of the mean of the stated values.

As used herein, the terms "approximately," "substantially," "essentially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the terms can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" or "about" the same if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ± 10 ° from 0 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ± 10 ° from 90 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.

For example, two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm. A surface may be considered planar or substantially planar if the displacement of the surface relative to the plane between any two points on the surface is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.

As used herein, the terms "conductive", "electrically conductive" and "conductivity" refer to the ability to transfer electrical current. Conductive materials generally indicate those materials that are minimally or zero antagonistic to current flow. One measure of conductivity is siemens per meter (S/m). Typically, the electrically conductive material is one having an electrical conductivity greater than approximately 104S/m (e.g., at least 105S/m or at least 106S/m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.

As used herein, spatially relative terms, such as "below," "lower," "above," "upper," "lower," "left," "right," and the like, may be used herein for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

The foregoing summarizes features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure and various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.