阅读说明：本技术 氮化硅电路基板及电子部件模块 (Silicon nitride circuit board and electronic component module ) 是由 矢野清治 寺野克典 于 2020-03-26 设计创作，主要内容包括：本发明提供氮化硅电路基板,其具备氮化硅基板、设置于上述氮化硅基板的一面的第一铜层、和设置于上述氮化硅基板的另一面的第二铜层,上述氮化硅基板的断裂韧性值Kc为5.0MPa·m～(0.5)以上、10.0MPa·m～(0.5)以下,将上述氮化硅基板的线膨胀率设为α-(B)(/℃)、将上述氮化硅基板的杨氏模量设为E-(B)(GPa)、将上述第一铜层的线膨胀率设为α-(A)(/℃)、将上述第二铜层的线膨胀率设为α-(C)(/℃)时,热冲击参数HS1及热冲击参数HS2各自为1.30GPa以上、2.30GPa以下。(The invention provides a silicon nitride circuit board, which comprises a silicon nitride substrate, and a first copper layer arranged on one surface of the silicon nitride substrateAnd a second copper layer provided on the other surface of the silicon nitride substrate, wherein the silicon nitride substrate has a fracture toughness value Kc of 5.0MPa m 0.5 Above, 10.0 MPa.m 0.5 Hereinafter, the linear expansion coefficient of the silicon nitride substrate is defined as α B (/ DEG C), the Young's modulus of the silicon nitride substrate is represented by E B (GPa) and the linear expansion coefficient of the first copper layer is alpha A (/ DEG C), the linear expansion coefficient of the second copper layer is defined as alpha C (v. degree. C.) the thermal shock parameter HS1 and the thermal shock parameter HS2 were 1.30GPa or more and 2.30GPa or less, respectively.)

1. A silicon nitride circuit board is provided with:

a silicon nitride substrate;

a first copper layer disposed on one surface of the silicon nitride substrate; and

a second copper layer disposed on the other surface of the silicon nitride substrate,

the silicon nitride substrate has a fracture toughness Kc of 5.0 MPa-m^0.5Above, 10.0 MPa.m^0.5In the following, the following description is given,

the linear expansion coefficient of the silicon nitride substrate is set as alpha_B(/ DEG C), Young's modulus of the silicon nitride substrateModulus is set to E_B(GPa) and the linear expansion coefficient of the first copper layer is alpha_A(/ DEG C), the linear expansion coefficient of the second copper layer is defined as alpha_C(v. degree. C.) when the temperature is measured,

the thermal shock parameter HS1 represented by the following formula (1) and the thermal shock parameter HS2 represented by the following formula (2) are each 1.30GPa or more and 2.30GPa or less,

formula (1) HS1 ═ α_A-α_B)×E_B×(350-(-78))

Formula (2) HS2 ═ α_C-α_B)×E_B×(350-(-78))。

2. The silicon nitride circuit substrate of claim 1, wherein the average crystal grain size of the copper crystals in the first copper layer is 50 μm or more and 500 μm or less.

3. The silicon nitride circuit substrate of claim 1 or 2, wherein the average crystal grain size of the copper crystals in the second copper layer is 50 μ ι η to 500 μ ι η.

4. The silicon nitride circuit substrate of any of claims 1-3, wherein the silicon nitride substrate has a Young's modulus E_BIs 250GPa or more and 320GPa or less.

5. The silicon nitride circuit substrate of any of claims 1-4, wherein the silicon nitride substrate has a linear expansion coefficient α_BIs 1.5X 10^-64.0X 10 at a temperature of 4.0 ℃ or higher^-6Below/° c.

6. The silicon nitride circuit substrate according to any one of claims 1 to 5, used in a form sealed by a sealing resin portion.

7. The silicon nitride circuit substrate according to claim 6, wherein the morphology is a morphology in which a surface of the second copper layer opposite to a surface on which the silicon nitride substrate is provided has an uncoated region not covered with the sealing resin portion.

8. The silicon nitride circuit substrate according to claim 6 or 7, wherein the form is a form in which a surface of the second copper layer opposite to a surface on which the silicon nitride substrate is provided is bonded to a heat sink directly or via a bonding material layer.

9. The silicon nitride circuit substrate of any of claims 1-8, wherein the first copper layer is a copper layer formed into a circuit pattern.

10. The silicon nitride circuit substrate of any of claims 1-9, wherein the second copper layer is a copper layer for heat spreader bonding.

11. An electronic component module, comprising: a silicon nitride circuit board, an electronic component mounted on the silicon nitride circuit board, and a sealing resin section for sealing the silicon nitride circuit board and the electronic component,

wherein the silicon nitride circuit substrate is the silicon nitride circuit substrate of any one of claims 1-10.

12. The electronic component module according to claim 11, wherein a surface of the second copper layer opposite to a surface on which the silicon nitride substrate is provided protrudes in a direction away from the silicon nitride substrate than the sealing resin portion.

Technical Field

The invention relates to a silicon nitride circuit board and an electronic component module.

Background

As a circuit board used for a power module or the like, a ceramic substrate of alumina, beryllia, silicon nitride, aluminum nitride or the like is used from the viewpoints of thermal conductivity, cost, safety and the like. These ceramic substrates are used as circuit substrates by bonding a metal circuit layer of copper, aluminum, or the like and a heat dissipation layer. The ceramic substrate is used as a substrate for mounting an electronic component having high heat dissipation properties because it has excellent insulation properties, heat dissipation properties, and the like, as compared with a metal substrate using a resin substrate or a resin layer as an insulating material.

In power module applications such as elevators, vehicles, hybrid cars, and the like, the following ceramic circuit boards are used: a metal circuit board is joined to the surface of a ceramic substrate with a brazing material, and a semiconductor element is mounted on a predetermined position of the metal circuit board. In recent years, as semiconductor elements have been highly integrated, have been increased in frequency, have been increased in output, and the like, the amount of heat generated from the semiconductor elements has increased, and for this purpose, ceramic substrates such as aluminum nitride sintered bodies and silicon nitride sintered bodies having high thermal conductivity have been used. Among these, a silicon nitride substrate having high mechanical reliability and excellent mechanical strength and toughness is particularly required as a ceramic substrate for mounting electronic components.

Further, in an electronic component module or the like, since thermal stress is repeatedly applied to a ceramic circuit board, if the ceramic circuit board cannot withstand the thermal stress, micro cracks are generated in the ceramic circuit board, or when a thermal load cycle is continued in a state where the micro cracks are generated, a metal circuit layer is peeled off from the ceramic circuit board, which causes a problem of poor bonding strength or poor thermal resistance, and a problem of lowering operation reliability as an electronic device.

For this reason, for example, patent document 1 describes that the fracture toughness value of a silicon nitride substrate is set to 6.5MPa · m^1/2The above technique. The invention described in patent document 1 discloses that the three-point bending strength is 500MPa or more and the fracture toughness value is as high as 6.5MPa · m^1/2The silicon nitride substrate described above can suppress the occurrence of cracks due to thermal stress.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 2002-

However, in an electronic component module or the like, high output and high integration have been advanced, and thermal stress repeatedly applied to a ceramic circuit board tends to be further increased, and in the conventional technology, a ceramic substrate cannot withstand thermal stress, for example, a micro crack is generated, or a metal circuit layer is peeled off from the ceramic substrate, and thus a bonding strength failure or a thermal resistance failure may occur, and the reliability of an electronic component module in which an electronic component such as a semiconductor element is mounted on such a ceramic circuit board is insufficient.

Disclosure of Invention

Problems to be solved by the invention

In view of the above problems, an object of the present invention is to obtain a silicon nitride circuit board capable of improving reliability and yield as an electronic component module.

Means for solving the problems

According to the present invention, a silicon nitride circuit board and an electronic component module described below are provided.

That is, according to the present invention, there is provided a silicon nitride circuit board comprising:

a silicon nitride substrate;

a first copper layer provided on one surface of the silicon nitride substrate; and

a second copper layer provided on the other surface of the silicon nitride substrate,

fracture toughness of the silicon nitride substrateThe value Kc is 5.0MPa · m^0.5Above, 10.0 MPa.m^0.5In the following, the following description is given,

the linear expansion coefficient of the silicon nitride substrate is set to alpha_B(/ DEG C), the Young's modulus of the silicon nitride substrate is represented by E_B(GPa) and the linear expansion coefficient of the first copper layer is alpha_A(/ DEG C), the linear expansion coefficient of the second copper layer is defined as alpha_C(v. degree. C.) when the temperature is measured,

the thermal shock parameter HS1 represented by the following formula (1) and the thermal shock parameter HS2 represented by the following formula (2) are each 1.30GPa to 2.30 GPa.

Formula (1) HS1 ═ α_A-α_B)×E_B×(350-(-78))

Formula (2) HS2 ═ α_C-α_B)×E_B×(350-(-78))

Further, according to the present invention, there is provided an electronic component module comprising a silicon nitride circuit board, an electronic component mounted on the silicon nitride circuit board, and a sealing resin portion sealing the silicon nitride circuit board and the electronic component,

the silicon nitride circuit substrate is the silicon nitride circuit substrate.

ADVANTAGEOUS EFFECTS OF INVENTION

Since the silicon nitride circuit board of the present invention is configured as described above, an electronic component module having a low incidence of poor bonding strength or poor thermal resistance when thermal stress is applied and high reliability and yield as an electronic device can be obtained.

Drawings

Fig. 1 is a plan view of a silicon nitride circuit board according to the present embodiment.

Fig. 2 is a cross-sectional view of a silicon nitride circuit board according to the present embodiment.

Fig. 3 is a sectional view of the electronic component module according to the present embodiment.

Fig. 4 is an enlarged cross-sectional view of a part of the electronic component module according to the present embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and the description thereof is omitted as appropriate. The drawings are schematic and do not match the actual size ratios.

First, the structure of the silicon nitride substrate of the present embodiment will be described.

< Structure of silicon nitride Circuit Board in accordance with this embodiment >

The silicon nitride circuit board of the present embodiment will be described with reference to fig. 1 and 2. Fig. 1 is a plan view of a silicon nitride circuit board according to the present embodiment, and fig. 2 is a sectional view of the silicon nitride circuit board according to the present embodiment.

As shown in fig. 2, the silicon nitride circuit board 100 according to the present embodiment includes a silicon nitride substrate 10, a first copper layer 30, and a second copper layer 20. The silicon nitride substrate 10 and the second copper layer 20 are stacked with the solder layer 12 interposed therebetween, and the silicon nitride substrate 10 and the first copper layer 30 are stacked with the solder layer 13 interposed therebetween.

In the present embodiment, the "silicon nitride-copper composite" refers to a state before forming a circuit pattern, and is a state in which the first copper layer 30, the solder layer 13, the silicon nitride substrate 10, the solder layer 12, and the second copper layer 20 are laminated. The term "silicon nitride circuit board" refers to a state in which a circuit pattern is formed on a "silicon nitride-copper composite", and may be a state in which an electronic component such as the electronic component 40 is mounted on a part of a copper layer on which the circuit pattern is formed.

As described above, the silicon nitride circuit substrate according to the present embodiment is a silicon nitride circuit substrate including the silicon nitride substrate 10, the first copper layer 30 provided on one surface of the silicon nitride substrate 10, and the second copper layer 20 provided on the other surface of the silicon nitride substrate, and the silicon nitride substrate 10 has a fracture toughness value Kc of 5.0MPa · m^0.5Above, 10.0 MPa.m^0.5Hereinafter, the linear expansion coefficient of the silicon nitride substrate 10 is defined as α_B(/ DEG C), the Young's modulus of the silicon nitride substrate 10 is represented by E_B(GPa) and the linear expansion coefficient of the first copper layer 30 is set as alpha_A(/ DEG C), the linear expansion coefficient of the second copper layer 20 is defined as alpha_C(v. degree. C.) the thermal shock parameter HS1 represented by the following formula (1) and the thermal shock parameter HS2 represented by the following formula (2) are set to be 1.30GPa or more and 2.30GPa or less, respectively.

Formula (1) HS1 ═ α_A-α_B)×E_B×(350-(-78))

Formula (2) HS2 ═ α_C-α_B)×E_B×(350-(-78))

In the above formulae, HS1 and HS2 are parameters relating to the difference in linear expansion coefficient between the silicon nitride substrate 10 and the second copper layer 20, and between the silicon nitride substrate 10 and the first copper layer 30, and the product of the young's modulus of the silicon nitride substrate 10 and the temperature, and the thermal stress that can be accumulated between the silicon nitride substrate 10 and the second copper layer 20 and between the silicon nitride substrate 10 and the first copper layer 30.

For example, the silicon nitride substrate 10 has a linear expansion coefficient α_B＝4.0×10^-6(/ deg.C), Young's modulus E_BLinear expansion coefficient α of the first copper layer 30, 250(GPa) silicon nitride substrate_A＝17.3×10^-6(/ deg.C), the linear expansion coefficient alpha of the second copper layer 20_C＝17.3×10^-6(/ ° c), HS1 ═ α_A-α_B)×E_B×(350-(-78))＝1.42(GPa)，HS2＝(α_C-α_B)×E_B×(350-(-78))＝1.42(GPa)。

The fracture toughness Kc of the silicon nitride substrate 10 is more preferably 5.5MPa · m^0.5Above, 9.0 MPa.m^0.5The following. The thermal shock parameter HS1 represented by the formula (1) and the thermal shock parameter HS2 represented by the formula (2) are more preferably 1.30GPa to 1.80 GPa.

The thermal shock parameter HS1 represented by the formula (1), the thermal shock parameter HS2 represented by the formula (2), and the fracture toughness value Kc of the silicon nitride substrate 10 can be adjusted by controlling the types of the respective constituent materials used for manufacturing the silicon nitride circuit substrate, the manufacturing conditions, and the like.

According to the present embodiment, by setting the thermal shock parameters HS1 and HS2 and the fracture toughness value Kc of the silicon nitride substrate 10 within the above numerical ranges and setting the residual stress accumulated in the silicon nitride circuit substrate and the degree of crack development in the silicon nitride substrate within specific ranges, it is possible to prevent the occurrence of fracture and peeling due to the development of cracks and the like, and to reduce the occurrence of poor bonding strength and poor thermal resistance when the silicon nitride circuit substrate is manufactured into an electronic component module.

As will be understood from the results of the examples described later, when the thermal shock parameter HS1 represented by the formula (1) and the thermal shock parameter HS2 represented by the formula (2) were set to 1.80GPa or less, a silicon nitride circuit board with improved reliability and yield was obtained.

The fracture toughness value Kc of the silicon nitride substrate 10 can be measured by IF method in accordance with JIS R1607. That is, a vickers indenter was pressed into the surface of the silicon nitride substrate at 2kgf, and the fracture toughness value of the silicon nitride substrate was evaluated from the length of the diagonal line of the vickers indentation and the length of the crack extending from each end.

Linear expansion coefficient (alpha) of silicon nitride substrate 10, second copper layer 20 and first copper layer 30_B、α_C、α_AAnd) a thermomechanical analysis device (TMA: thermal analyzer). In the present invention, the linear expansion coefficient (α)_B、α_C、α_AAnd) the linear expansion coefficients (linear expansion coefficients) of the copper plates and the silicon nitride substrates at 25 to 400 ℃.

Young's modulus (E) of silicon nitride substrate 10_B) The measurement can be performed by a static deflection method according to JIS R1602.

The respective configurations of the silicon nitride circuit board according to the present embodiment will be described in more detail below.

< silicon nitride substrate >

The silicon nitride substrate 10 according to the present embodiment has a function of supporting the first copper layer 30 and the second copper layer 20. Here, the silicon nitride substrate 10 is rectangular when viewed from the thickness direction thereof. The thickness of the silicon nitride substrate 10 is set to a range of 0.2mm to 1.5mm, and in the present embodiment, 0.32 mm. The shape and the like of the silicon nitride substrate 10 are examples in the present embodiment, and may be different from those in the present embodiment as long as the functions according to the present invention can be exhibited.

As described above, the silicon nitride substrate 10 according to the present embodiment has a fracture toughness Kc of 5.0MPa · m^0.5Above, 10.0 MPa.m^0.5The lower limit is more preferably 5.5MPa · m^0.5Above, 9.0 MPa.m^0.5The following.

Further, the young's modulus E of the silicon nitride substrate 10 according to the present embodiment_BPreferably 250GPa or more and 320GPa or less, more preferably 250GPa or more and less than 300 GPa.

In addition, the silicon nitride substrate 10 according to the present embodiment has a linear expansion coefficient α_BPreferably 1.5X 10^-64.0X 10 at a temperature of 4.0 ℃ or higher^-6Lower than/° C, more preferably 1.5X 10^-6over/DEG C and less than 2.5 x 10^-6/℃。

By adjusting the physical properties of the silicon nitride substrate 10 in the above manner, the thermal shock parameters HS1 and HS2 can be easily adjusted to fall within the above numerical value range, and the bonding strength defect or the thermal resistance defect can be further reduced.

The silicon nitride substrate 10 can be produced by a known method, and the fracture toughness Kc and the young's modulus E of the silicon nitride substrate 10_BLinear expansion coefficient alpha_BThe method of manufacturing the silicon nitride substrate 10, specifically, the mixing of raw materials, firing conditions (temperature rise rate, holding temperature, holding time, cooling rate, etc.), and the like can be controlled. The method for manufacturing the silicon nitride substrate 10 is described below.

< first copper layer and second copper layer >

The first copper layer 30 and the second copper layer 20 are polygonal when viewed from the thickness direction thereof. The thicknesses of the first copper layer 30 and the second copper layer 20 are set to be in the range of 0.5mm to 2.0mm, and more preferably 0.8mm to 1.2 mm. In the present embodiment, 0.8mm is used as an example. The shapes and the like of the first copper layer 30 and the second copper layer 20 are examples in the present embodiment, and may be different from those in the present embodiment as long as the functions according to the present invention can be exhibited.

The linear expansion coefficients of the first copper layer 30 and the second copper layer 20 according to the present embodiment vary depending on the kind of copperHowever, since the coefficient of linear expansion of the copper layer in this embodiment is 17.3 × 10, it does not change greatly^-6(/℃)。

By adjusting the physical properties of the first copper layer 30 and the second copper layer 20 in the above manner, the thermal shock parameters HS1 and HS2 can be easily adjusted to fall within the above numerical range, and the bonding strength failure and the thermal resistance failure can be further reduced.

The average crystal grain size of the copper crystals in the first copper layer 30 is preferably 50 μm or more and 500 μm or less, and more preferably 100 μm or more and 300 μm or less.

When the silicon nitride circuit substrate according to the present embodiment is used as an electronic component module as described later, the electronic component 40 is mounted on the first copper layer 30 via a bonding layer such as a solder layer 31, and the first copper layer 30 is sandwiched between the solder layer and the electronic component and the silicon nitride substrate 10, and is subjected to thermal stress caused by a difference in thermal expansion from these materials, but by setting the average crystal grain size of the copper crystal in the first copper layer 30 within the above numerical range, it is possible to further reduce bonding strength failure and thermal resistance failure. The reason for this is presumed, although not clear, that the average crystal grain size of the copper crystals in the first copper layer 30 is within the above numerical range, so that grain boundary sliding and the like of the copper crystals occur moderately in the first copper layer 30, and the stress is moderately relieved.

The average crystal grain size of the copper crystals in the second copper layer 20 is preferably 50 μm or more and 500 μm or less, and more preferably 100 μm or more and 300 μm or less.

When the silicon nitride circuit substrate according to the present embodiment is used as an electronic component module as described later, a heat sink is bonded to the second copper layer 20 via a bonding layer such as a solder layer, and the second copper layer 20 is sandwiched between the solder layer, the heat sink, and the silicon nitride substrate 10, and is subjected to thermal stress caused by a difference in thermal expansion from these materials, but by setting the average crystal grain size of the copper crystals in the second copper layer 20 within the above numerical range, it is possible to further reduce bonding strength defects and thermal resistance defects. The above mechanism is not clear, but it is presumed that the reason is that when the average crystal grain size of the copper crystals in the second copper layer 20 is within the above numerical range, grain boundary sliding or the like occurs moderately in the copper crystals in the second copper layer 20, and the stress is moderately relieved.

The average crystal grain size in the first copper layer 30 and the second copper layer 20 can be adjusted by controlling the kind of copper plate constituting the copper layers, the manufacturing conditions of the silicon nitride circuit board, and the like.

The average crystal grain size of the copper crystals in the first copper layer 30 and the second copper layer 20 can be determined by the method described in examples.

< solder layer >

The solder layer 12 and the solder layer 13 according to the present embodiment are respectively disposed between the silicon nitride substrate 10 and the first copper layer 30 and between the silicon nitride substrate 10 and the second copper layer 20, and the first copper layer 30 or the second copper layer 20 is bonded to the silicon nitride substrate 10. The thicknesses of the solder layer 12 and the solder layer 13 are typically set in the range of 3 μm to 40 μm, and more preferably 4 μm to 25 μm.

The silicon nitride circuit board according to the present embodiment may have a plating layer on the first copper layer 30 and the second copper layer 20. The plating layer may be formed of a known material, for example, Ag, Ni — P.

The composition of the solder layers 12 and 13 may be a silver-copper solder containing at least one active metal selected from titanium, zirconium, hafnium, niobium, tantalum, vanadium, aluminum, and tin in the solder. The ratio of Ag, Cu, and Sn or In is preferably a ratio including: 85.0 to 95.0 parts by mass of Ag; 5.0 to 13.0 parts by mass of Cu; 0.4 to 3.5 parts by mass of Sn or In. By setting the above numerical value range, excessive increase in the melting temperature of the brazing material is prevented, bonding can be performed at an appropriate temperature, thermal stress due to a difference in thermal expansion coefficient at the time of bonding can be reduced, and heat cycle resistance can be improved.

The amount of the active metal such as titanium added may be, for example, 1.5 parts by mass or more and 5.0 parts by mass or less with respect to 100 parts by mass of the total of Ag, Cu, Sn and In. By appropriately adjusting the amount of the active metal added, the wettability with the ceramic plate can be further improved, and the occurrence of poor bonding can be further suppressed.

Next, an embodiment of the silicon nitride circuit board according to the present embodiment will be further described with reference to fig. 3 and 4. Fig. 3 is a sectional view of the electronic component module according to the present embodiment. Fig. 4 is an enlarged cross-sectional view of a part of the electronic component module according to the present embodiment.

As described above, the silicon nitride circuit board 100 according to the present embodiment is a silicon nitride circuit board including the silicon nitride substrate 10, the first copper layer 30 provided on one surface of the silicon nitride substrate 10, and the second copper layer 20 provided on the other surface of the silicon nitride substrate 10, and is used in a form sealed by the sealing resin portion 50 as shown in fig. 3.

In the present embodiment, the surface of the second copper layer 20 opposite to the surface on which the silicon nitride substrate 10 is provided has an uncoated region not covered with the sealing resin portion 50.

In the present embodiment, the silicon nitride circuit board may be formed such that the surface of the second copper layer 20 opposite to the surface on which the silicon nitride substrate 10 is provided is bonded to the heat sink directly or via a bonding material layer, and in the example of the present embodiment shown in fig. 3, the second copper layer 20 is bonded to the heat sink 60 via the bonding material layer 21.

That is, in the present embodiment, second copper layer 20 is bonded to heat sink 60 via bonding material layer 21, and the surface of second copper layer 20 facing heat sink 60 has an uncoated region not covered with sealing resin portion 50.

According to the present embodiment, even when the silicon nitride circuit board is used in a form further having a portion covered with the sealing resin portion 50 having a different linear expansion coefficient and an uncovered region not covered, and even when the second copper layer 20 in the silicon nitride circuit board is used in a form further bonded to the heat sink 60 having a different linear expansion coefficient, by adjusting the thermal shock parameters HS1 and HS2 and the fracture toughness value of the silicon nitride circuit board 10, it is possible to reduce the bonding strength failure and the thermal resistance failure.

In the present embodiment, the first copper layer 30 is a copper layer formed as a circuit pattern. The electronic component 40 is bonded to the first copper layer 30 via the solder layer 31, and the first copper layer 30 and the electronic component 40 are connected to the external connection terminals 70 via a lead frame for external connection and a wire bonding (wire bonding) 71. In the present embodiment, an example in which the external connection terminals 70 are connected by bonding wires 71 is shown as an example. The external connection terminals 70 may be directly connected to the substrate without the bonding wires 71. In this case, the external connection terminals 70 may be bonded by soldering or ultrasonic bonding, for example.

The electronic component 40 is an electronic component such as a Semiconductor element, and various Semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a FWD (Free Wheeling Diode) can be selected according to a desired function.

The solder layer 31 for bonding the electronic component 40 may be, for example, a Sn — Sb, Sn — Ag, Sn — Cu, Sn — In, or Sn — Ag — Cu solder material (so-called lead-free solder material).

The external connection terminals 70 are made of, for example, copper or a copper alloy, and the bonding wires 71 are made of, for example, copper, a copper alloy, aluminum, gold, or the like.

The sealing resin portion 50 can be formed by curing a sealing resin portion-forming resin composition.

The type of the resin composition for forming the sealing resin portion is not particularly limited, and a resin composition generally used in the technical field, such as a resin composition for transfer molding, a resin composition for compression molding, a liquid sealing material, and the like, can be used.

The resin composition for forming the sealing resin portion preferably contains a thermosetting resin, preferably contains one or more selected from the group consisting of an epoxy resin, a phenol resin, a cyanate resin, a bismaleimide-triazine resin, an acrylic resin, and a silicone resin, and more preferably contains at least an epoxy resin.

The resin composition for forming the sealing resin portion may further contain a curing agent, a filler, and the like.

Examples of the filler include powders such as fused silica (spherical silica), crystalline silica, alumina, silicon carbide, silicon nitride, aluminum nitride, boron nitride, beryllium oxide, and zirconia, or beads obtained by forming these powders into a spherical shape, glass fibers, aramid fibers, and carbon fibers. The filler may be used alone or in combination of two or more. As the resin composition for forming the sealing resin portion, for example, SiO-containing resin can be used₂And epoxy-based resins as fillers.

In the present embodiment, the second copper layer 20 is a copper layer for bonding a heat sink.

In the present embodiment, the second copper layer 20 is bonded to the heat sink 60 via the bonding material layer 21.

The heat sink 60 is made of a material having high thermal conductivity, such as aluminum, copper, or an alloy thereof, and is preferably made of aluminum or an aluminum alloy.

The electronic component module according to the present embodiment includes the silicon nitride circuit board. That is, the electronic component module according to the present embodiment includes: a silicon nitride circuit substrate; an electronic component 40 mounted on the silicon nitride circuit board; and a sealing resin portion 50 for sealing the silicon nitride circuit board 100 and the electronic component 40.

In the electronic component module according to the present embodiment, the surface of the second copper layer 20 opposite to the surface on which the silicon nitride substrate 10 is provided protrudes further away from the silicon nitride substrate 10 than the sealing resin portion 50. That is, as shown in fig. 4, when the surface of the sealing resin portion 50 facing the heat sink 60 is defined as the sealing resin portion lower surface 51 and the surface of the second copper layer 20 facing the heat sink 60 is defined as the second copper layer lower surface 22, a level difference is present between the sealing resin portion lower surface 51 and the bonding material layer 21, and the second copper layer lower surface 22 is designed to protrude from the sealing resin portion lower surface 51. By such a design, in the step of bonding the silicon nitride circuit board 100 to the heat sink 60, that is, in the step of bonding the second copper layer lower surface 22 (the uncoated region not covered with the sealing resin portion 50) to the heat sink 60, when the silicon nitride circuit board 100 is brought into pressure contact with the heat sink 60, the second copper layer lower surface 22 is first brought into contact with the heat sink 60, and therefore, the sealing resin portion 50 does not interfere with the bonding, the second copper layer lower surface 22 can be smoothly bonded to the heat sink 60, and the reliability of bonding the second copper layer 20 to the heat sink 60 can be improved.

< method for producing silicon nitride Circuit Board >

The silicon nitride circuit board according to the present embodiment can be manufactured by the following method.

First, a silicon nitride substrate 10 having desired physical properties is prepared. The silicon nitride substrate 10 can be obtained by the following production method. That is, the silicon nitride powder and Y were mixed by a ball mill₂O₃And a raw material powder of a sintering aid such as MgO, an organic solvent, and an organic binder, a plasticizer, and the like added as needed are uniformly mixed to prepare a raw material slurry. The obtained raw material slurry was defoamed and thickened, and then sheet molding was performed by a doctor blade method to obtain a molded article. The obtained sheet molded body is cut, degreased at 400 to 800 ℃, and fired in a firing furnace at 1700 to 1900 ℃ for 1 to 10 hours in a nitrogen atmosphere, whereby a silicon nitride substrate 10 can be obtained.

Here, the fracture toughness Kc and young's modulus E of the silicon nitride substrate 10_BLinear expansion coefficient alpha_BThe method of manufacturing the silicon nitride substrate 10, specifically, the production conditions such as the mixing of raw materials and the firing conditions can be adjusted by controlling the conditions. The fracture toughness value Kc can be controlled by adjusting firing conditions (temperature rise rate, holding temperature, holding time, cooling rate, etc.), for example, depending on the blending of raw materials and the balance with other production conditions. In addition, Young's modulus E_BFor example, the Young's modulus E can be controlled by adjusting the firing conditions (temperature rise rate, holding temperature, holding time, cooling rate, etc.), and by increasing the firing temperature, for example_BDecrease in Young's modulus E when the firing temperature is lowered_BAnd (4) improving. In addition, although it also depends onEquilibrium with other manufacturing conditions, linear expansion coefficient alpha_BFor example, the amount of the sintering aid added becomes smaller as the amount of the sintering aid added increases, and becomes larger as the amount of the sintering aid added decreases.

Next, an Ag — Cu alloy paste containing Ti as an active metal, for example, is formed by printing on both surfaces of the silicon nitride substrate 10 as a brazing material containing an active metal, and a rectangular copper plate substantially identical to the silicon nitride substrate 10 is heated and bonded to both surfaces at a temperature of 600 to 900 ℃. Here, as the copper plate, an oxygen-free copper plate is preferably used, and a rolled copper plate is more preferably used. A silicon nitride-copper composite can be obtained by joining copper plates to both surfaces of the silicon nitride substrate 10 through a brazing material.

Next, the first copper layer 30 is etched to form a circuit pattern. A photoresist (not shown) is laminated on the upper surface of the film 30. In this case, a photoresist in a liquid state may be applied.

Next, pattern exposure is performed with reference to the circuit pattern in order to form a circuit pattern on the photoresist. In this case, the film on which the negative image of the circuit pattern is formed may be brought into close contact with the photoresist to expose the photoresist by so-called batch exposure, or the photoresist may be exposed by using a so-called direct-writing type exposure apparatus (without using the film).

Then, the photoresist exposed to light is etched according to the circuit pattern.

Next, the remaining photoresist is removed.

In this case, the second copper layer 20 may be patterned in the same manner without performing etching treatment. The second copper layer 20 and the first copper layer 30 after the circuit pattern is formed may be further plated.

In this manner, the silicon nitride circuit substrate 100 in a state where the circuit pattern is formed is manufactured.

Next, the electronic component 40 is mounted on the first copper layer 30 through the solder layer 31. In the present embodiment, the first copper layer 30 and the electronic component 40 are solder-bonded using, for example, a Sn — Sb, Sn — Ag, Sn — In, or Sn — Ag — Cu solder material.

Next, the electronic component module is resin-sealed with a sealing resin, thereby forming a sealing resin portion 50. The resin sealing may be performed by a known method, for example, by transfer molding. In the resin sealing step, for example, by performing resin sealing while pressing the second copper layer lower surface 22 of the electronic component module against a plastic material in advance, an uncoated region not covered with the sealing resin portion 50 can be left on the surface of the second copper layer 20 opposite to the surface on which the silicon nitride substrate 10 is provided (i.e., the second copper layer lower surface 22), and the second copper layer lower surface 22 can be protruded from the sealing resin portion lower surface 51.

In this manner, an electronic component module is manufactured.

The present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within a range in which the object of the present invention can be achieved are included in the present invention.

Examples

The present invention will be described in detail with reference to examples below, but the present invention is not limited to the description of these examples.

HS1, HS2 and fracture toughness value K were prepared by the following method_CDifferent silicon nitride circuit boards were subjected to a thermal cycle test described later.

< silicon nitride substrate >

Various linear expansion coefficients alpha were prepared by adjusting the blending of raw materials and the firing conditions_BYoung's modulus E_BFracture toughness value K_CSilicon nitride substrates B-1 to B-10(148 mm. times.200 mm. times.0.32 mm) were obtained.

< copper plate for first copper layer and second copper layer >

The prepared linear expansion coefficient was 17.3X 10^-6A rolled copper plate having a thickness of 0.8mm at/° C.

< method for producing silicon nitride Circuit Board >

Silicon nitride circuit boards 1 to 10 were produced using a silicon nitride substrate and a copper plate in the combinations shown in table 1.

First, a brazing filler metal (containing an active metal) containing 3.5 parts by mass of titanium hydride powder (TCH-100, manufactured by TOHO TECHNICAL Co., Ltd.) was prepared per 100 parts by mass in total of 89.5 parts by mass of Ag powder (Ag-HWQ 2.5 μm, manufactured by Fuda Metal foil powder industries Co., Ltd.), 9.5 parts by mass of Cu powder (Cu-HWQ 3 μm, manufactured by Fuda Metal foil powder industries Co., Ltd.) and 1.0 part by mass of Sn powder (Sn-HPN 3 μm, manufactured by Fuda Metal foil powder industries Co., Ltd.).

And mixing the brazing filler metal, the binder resin and the solvent to obtain the brazing filler metal paste. The solder paste was applied to both surfaces of a silicon nitride substrate by a screen printing method so that the dry thickness at each surface became about 10 μm.

Then, copper plates were stacked on both sides of the silicon nitride substrate at 1.0X 10^-3Heating was performed in a vacuum of 780 ℃ for 30 minutes or less under Pa, and the silicon nitride substrate and the copper plate were joined by the brazing material. Thus, a silicon nitride-copper composite was obtained in which the silicon nitride substrate and the copper plate were joined by a brazing material. Then, a resist was printed on the copper layer of the obtained silicon nitride-copper composite, and a circuit pattern was formed by etching with an iron chloride solution, thereby obtaining a silicon nitride circuit board.

As a result of evaluating the average crystal grain size of copper with respect to the silicon nitride circuit board 1 by the following method, the average crystal grain size of copper crystals in the first copper layer was 250 μm, and the average crystal grain size of copper crystals in the second copper layer was 255 μm.

< evaluation methods for copper plate and silicon nitride substrate >

(1) Linear expansion coefficient (alpha) of copper plate and silicon nitride substrate_B)

The linear expansion coefficients (linear expansion coefficients) of the copper plates and the silicon nitride substrates at 25 ℃ to 400 ℃ were measured by a thermomechanical analyzer (TMA) according to JIS R618.

(2) Young's modulus (E) of silicon nitride substrate_B)

The measurement was performed by a static deflection method in accordance with JIS R1602. The test piece had a shape of 3 mm. times.4 mm. times.40 mm.

(3) Fracture toughness value (K) of silicon nitride substrate_C)

Measured by the IF method in accordance with JIS R1607. That is, a vickers indenter was pressed into the surface of the silicon nitride substrate at 2kgf, and the fracture toughness value of the silicon nitride substrate was evaluated based on the length of the diagonal line of the vickers indentation and the length of the crack extending from each end.

< method for evaluating average grain size of copper >

The average crystal grain size of copper in the first copper layer and the second copper layer in the silicon nitride circuit substrate was determined by the following method.

First, a "cross section" for measurement is obtained by the following procedure.

(1) The ceramic circuit substrates obtained in the examples and comparative examples were cut along a cross section perpendicular to the main surface and passing through the center of gravity of the substrate. A band saw is used for cutting.

(2) The cut silicon nitride circuit substrate was embedded with resin to prepare a resin-embedded body.

(3) The cross section of the composite body in the produced resin-embedded body was polished using diamond abrasive grains.

The cross section of the polished silicon nitride circuit substrate was measured by an electron back scattering diffraction method.

Specifically, first, analysis by an Electron Back Scattering Diffraction (EBSD) method was performed in an observation field of 50 times at an acceleration voltage of 15kV in the vicinity of the approximate center of the polished first copper layer or second copper layer, and data was acquired. In the EBSD method, an SU6600 field emission type scanning microscope manufactured by Hitachi Kagaku K.K. and an analytical instrument manufactured by TSL Solutions, K.K. were used.

Software manufactured by TSL Solutions, ltd: OIM Data Analysis 7.3.0 visualizes the measurement Data, and makes a crystal orientation map. The crystal orientation map was analyzed by image processing software to determine the average crystal grain size of copper crystals in the copper layer.

In the above, as the Image processing software, Image-Pro Plus Shape Stack version 6.3 manufactured by Media Cybernetics was used. In the calculation of the average crystal grain size, 10 or more straight lines having a predetermined length are drawn in parallel on one observation image by an intercept method, and the average of the lengths of the straight lines at the portions where the straight lines cross the copper crystal grains is obtained as the average crystal grain size of the copper crystal (these are values calculated by software automatically processing).

< Heat cycle test and reliability evaluation >

First, a bonding substrate to be tested at a normal temperature (for example, 20 ℃) is moved into an environment of 150 ℃ and is held in the environment of 150 ℃ for 15 minutes (step 1).

Subsequently, the bonded substrate was moved from the environment of 150 ℃ to the environment of-55 ℃ and kept in the environment of-55 ℃ for 15 minutes (step 2).

Then, the 1 st step and the 2 nd step were alternately repeated 2000 times.

Then, the copper layer was examined for the presence or absence of peeling by ultrasonic flaw detection measurement.

The evaluation criteria are shown below.

O: peeling did not occur.

And (delta): peeling occurred in small amounts.

Specifically, the case where the occurrence of peeling was observed but was comparable to the silicon nitride circuit substrate 2 or the case where the occurrence of peeling was observed but was lighter than the silicon nitride circuit substrate 2 was evaluated as Δ with respect to the silicon nitride circuit substrate 2 where peeling occurred.

X: peeling occurred in large amounts.

Specifically, the case where peeling was observed and more peeling than the silicon nitride circuit substrate 2 occurred was evaluated as x, based on the silicon nitride circuit substrate 2 where peeling was observed.

The evaluation results and the like are summarized in Table 1.

[ Table 1]

As shown in table 1, the silicon nitride circuit substrates according to examples in which the fracture toughness values and HS1 and HS2 were controlled to fall within the ranges specified in the present invention exhibited little peeling, and particularly, the silicon nitride circuit substrates according to examples in which HS1 and HS2 were 1.80GPa or less exhibited no peeling.

As can be understood from the above, in order to stably obtain a highly reliable silicon nitride circuit board, it is important to select a material for the copper layer and a material for the silicon nitride substrate.

The present application claims priority based on japanese application No. 2019-066151 filed on 29/3/2019, the entire disclosure of which is incorporated herein.

Description of the reference numerals

10 silicon nitride substrate

12 solder layer

13 solder layer

20 second copper layer

21 bonding material layer

22 lower surface of the second copper layer

30 first copper layer

31 solder layer

40 electronic component

50 sealing resin part

51 sealing resin part lower surface

60 radiator

70 external connection terminal

71 bonding wire

100 silicon nitride circuit substrate