阅读说明：本技术 电力用半导体模块 (Power semiconductor module ) 是由 坂本达朗 于 2021-05-10 设计创作，主要内容包括：提供一种电力用半导体模块,抑制半导体开关元件之间的电流不平衡。电力用半导体模块包括：汇流条,所述汇流条接合有半导体开关元件各自的第一主电极；散热性金属基板,所述散热性金属基板接合有半导体开关元件各自的第二主电极；以及控制栅极端子,所述控制栅极端子通过接合线与半导体开关元件各自的栅极垫连接,多个半导体开关元件中的至少两个在散热性金属基板上相邻配置,形成并联电连接的一个桥臂。(Provided is a power semiconductor module in which current imbalance between semiconductor switching elements is suppressed. The power semiconductor module includes: a bus bar to which respective first main electrodes of the semiconductor switching elements are joined; a heat dissipating metal substrate to which second main electrodes of the semiconductor switching elements are bonded; and a control gate terminal connected to the gate pad of each of the semiconductor switching elements by a bonding wire, wherein at least two of the plurality of semiconductor switching elements are arranged adjacent to each other on the heat dissipating metal substrate to form one arm electrically connected in parallel.)

1. A power semiconductor module, comprising:

a plurality of semiconductor switching elements having a first main electrode and a gate pad on a front surface and a second main electrode on a rear surface;

a bus bar to which the first main electrodes of the respective semiconductor switching elements are joined;

a heat dissipating metal substrate to which the second main electrodes of the semiconductor switching elements are bonded; and

a control gate terminal connected to the gate pad of each of the semiconductor switching elements by a bonding wire,

at least two of the plurality of semiconductor switching elements are disposed adjacent to each other on the heat dissipating metal substrate, and form one arm electrically connected in parallel.

2. The power semiconductor module according to claim 1,

the distance between the closest points of at least two adjacent semiconductor switching elements is within 5 mm.

3. The power semiconductor module according to claim 1 or 2,

the bus bar, the heat dissipating metal substrate, and the bonding wires are arranged such that a direction of a current flowing in the bus bar is different from a direction of a current flowing in the bonding wires, and a direction of a current flowing in the heat dissipating metal substrate is different from the direction of a current flowing in the bonding wires.

4. The power semiconductor module according to any one of claims 1 to 3,

the gate pads of at least two of the semiconductor switching elements arranged adjacently are connected to one of the bonding wires,

all of the bond wires are connected to one of the control gate terminals.

5. The power semiconductor module according to any one of claims 1 to 3,

the gate pads of at least two of the semiconductor switching elements arranged adjacently are connected to one of the bonding wires,

each of the bonding wires is connected to a different one of the control gate terminals.

6. The power semiconductor module according to any one of claims 1 to 5,

the first semiconductor switching element unit including at least two semiconductor switching elements arranged adjacent to each other and the second semiconductor switching element unit including at least two semiconductor switching elements arranged adjacent to each other are arranged in mirror symmetry with respect to a reference line as a symmetry axis.

7. The power semiconductor module according to claim 6,

the structure of the bus bar is mirror-symmetrical with the reference line as a symmetry axis.

8. The power semiconductor module according to claim 6 or 7,

a first one of the bond wires and a second one of the bond wires are arranged mirror-symmetrically with respect to the axis of symmetry.

9. The power semiconductor module according to any one of claims 1 to 8,

the power semiconductor module includes a reflux diode connected in anti-parallel with the semiconductor switching element.

10. The power semiconductor module according to claim 9,

the reflux diode is formed of a wide band gap semiconductor having a wider band gap than silicon.

11. The power semiconductor module according to any one of claims 1 to 8,

the semiconductor switching element is formed of a wide band gap semiconductor having a wider band gap than silicon.

12. The power semiconductor module according to claim 10 or 11,

the wide band gap semiconductor is any one of silicon carbide, gallium nitride, and diamond.

13. The power semiconductor module according to any one of claims 1 to 12,

the power semiconductor module includes two of the bridge arms,

one of said legs being a positive leg and the other of said legs being a negative leg are connected in series with each other,

the power semiconductor module comprises an alternating current electrode, and the alternating current electrode is connected to a connection point of the positive bridge arm and the negative bridge arm.

Technical Field

The present application relates to a power semiconductor module.

Background

In an electric vehicle such as an electric vehicle or a plug-in hybrid vehicle, a power conversion device such as an inverter is used to drive a motor by a high-voltage battery, and the power conversion device includes a power semiconductor module for converting power by a switching operation. The power semiconductor module includes a semiconductor switching element that performs a switching operation on a heat-dissipating metal substrate, and the semiconductor switching element is connected to an external terminal and sealed with a sealing material such as resin or gel.

The semiconductor switching element generates a loss corresponding to a current and a voltage during conduction and switching. The semiconductor switching element is set to a rated power to prevent a temperature rise due to loss from exceeding a breakdown temperature of the semiconductor switching element and peripheral members. In general, in a power semiconductor module of a power conversion device for large current and high voltage, a large-sized semiconductor switching element is used to secure rated power as the power semiconductor module. However, there is a limit to the increase in the size of the semiconductor switching elements in terms of manufacturing technology, yield, and the like of the semiconductor switching elements, and in a power semiconductor module in which a large power capacity is sought, a plurality of semiconductor switching elements are connected in parallel in order to suppress heat generation of each semiconductor switching element.

When a plurality of semiconductor switching elements are connected in parallel, current imbalance occurs between the semiconductor switching elements at the time of switching due to variations in control signals and the like. If a current imbalance occurs between the semiconductor switching elements, a large loss occurs in a part of the semiconductor switching elements. Therefore, it is necessary to use a large semiconductor switching element or a large number of semiconductor switching elements, thereby increasing the size and cost of the power semiconductor module. On the other hand, a technique has been proposed in which the inductance variation between control signal wirings is reduced by the structure of a control signal board in a module to suppress the variation of a control signal (see, for example, patent document 1).

Documents of the prior art

Patent document

Patent document 1: international publication No. 2019/064874

In the conventional power semiconductor module, when there is a current imbalance due to a deviation of the ground potential between the semiconductor switching elements or a deviation of the parasitic inductance between the semiconductor switching elements, there is a technical problem that the current imbalance cannot be suppressed.

Disclosure of Invention

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power semiconductor module in which a variation in control signals between semiconductor switching elements, a variation in ground potential, and a variation in parasitic inductance are reduced with a simple configuration, thereby suppressing a current imbalance between the semiconductor switching elements.

The power semiconductor module disclosed in the present application includes: a plurality of semiconductor switching elements having a first main electrode and a gate pad on a front surface and a second main electrode on a rear surface; a bus bar to which respective first main electrodes of the semiconductor switching elements are joined; a heat dissipating metal substrate to which second main electrodes of the semiconductor switching elements are bonded; and a control gate terminal connected to the gate pad of each of the semiconductor switching elements by a bonding wire, wherein at least two of the plurality of semiconductor switching elements are arranged adjacent to each other on the heat dissipating metal substrate to form one arm electrically connected in parallel.

The power semiconductor module disclosed in the present application includes: a plurality of semiconductor switching elements having a first main electrode and a gate pad on a front surface and a second main electrode on a rear surface; a bus bar to which respective first main electrodes of the semiconductor switching elements are joined; a heat dissipating metal substrate to which second main electrodes of the semiconductor switching elements are bonded; and a control gate terminal connected to the gate pad of each of the semiconductor switching elements by a bonding wire, wherein at least two of the plurality of semiconductor switching elements are disposed adjacent to each other on the heat-dissipating metal substrate to form one arm electrically connected in parallel, and therefore, a variation in control signal, a variation in ground potential, and a variation in parasitic inductance among the semiconductor switching elements can be reduced with a simple configuration, and current imbalance among the semiconductor switching elements can be suppressed.

Drawings

Fig. 1 is a diagram showing an external appearance of a power semiconductor module according to embodiment 1.

Fig. 2 is a diagram showing an internal structure of the power semiconductor module according to embodiment 1 from which a resin mold is removed.

Fig. 3 is an equivalent circuit diagram of the power semiconductor module according to embodiment 1.

Fig. 4 is a diagram showing an external appearance of a power semiconductor module according to embodiment 2.

Fig. 5 is a diagram showing an internal structure of a power semiconductor module according to embodiment 2 from which a resin mold is removed.

Fig. 6 is an equivalent circuit diagram of the power semiconductor module according to embodiment 2.

Fig. 7 is a diagram showing an external appearance of a power semiconductor module according to embodiment 3.

Fig. 8 is a diagram showing an internal structure of a power semiconductor module according to embodiment 3 from which a resin mold is removed.

Fig. 9 is a diagram showing an external appearance of a power semiconductor module according to embodiment 4.

Fig. 10 is a diagram showing an internal configuration of a power semiconductor module according to embodiment 4, with a resin module removed.

Fig. 11 is a diagram showing an internal configuration of the power semiconductor module according to embodiment 4, from which the resin mold, the negative arm N bus bar, and the control ground terminal are removed.

Fig. 12 is a diagram showing an internal configuration of the power semiconductor module according to embodiment 4, from which the resin mold, the negative arm N bus bar, the control ground terminal, and the intermediate bus bar are removed.

(symbol description)

1. 1a, 1b, 1c resin molded article;

2. 2a, 2b P bus bars;

3. 3a, 3b N bus bars;

4. 4a, 4b, 4c, 4d control the ground terminal;

5. 5a, 5b, 5c, 5d, 5e control gate terminals;

6. 6a, 6b, 6c, 6d heat dissipating metal substrates;

7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, 7i, 7j, 7k, 7l, 7m, 7n semiconductor switching elements;

8. 8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h bond wires;

9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, 9l, 9m, 9n source electrodes;

10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10l, 10m, 10n gate pads;

11a, 11b positive arm P bus bar;

12 negative bridge arm N busbars;

13a, 13b ac bus bars;

14 an intermediate bus bar;

parasitic inductance on 21a, 21b, 21c, 21d, 21e, 21f P side;

22. 22a P side shared inductor;

parasitic inductances on the 23a, 23b, 23c, 23d, 23e, 23f N sides;

24. the 24aN side shares aN inductor;

25a, 25b, 25c, 25d, 25e, 25f gate control signal parasitic inductance;

26. 26a the grid control signals share an inductor;

27. 27a common inductor for ground control signals;

28a, 28b P side primary common inductance;

primary common inductance on sides 29a and 29b N;

30a, 30b gate control signal primary common inductance;

100. 200, 300, 400 power semiconductor modules;

1000 reference line.

Detailed Description

Hereinafter, a power semiconductor module according to an embodiment for carrying out the present application will be described in detail with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding parts.

Embodiment mode 1

Fig. 1 is a diagram showing an external appearance of a power semiconductor module 100 according to embodiment 1. Fig. 2 is a diagram showing the internal structure of the power semiconductor module 100 according to embodiment 1, with the resin module 1 removed. The power semiconductor module 100 according to embodiment 1 includes a resin mold 1, a P bus bar 2, an N bus bar 3, a control ground terminal 4, a control gate terminal 5, a heat-dissipating metal substrate 6, a semiconductor switching element 7a, a semiconductor switching element 7b, and a bonding wire 8. The semiconductor switching element 7a includes a source electrode 9a and a gate pad 10a on the front surface, and includes a drain electrode not shown on the rear surface. The semiconductor switching element 7b includes a source electrode 9b and a gate pad 10b on the front surface, and includes a drain electrode not shown on the rear surface. The semiconductor switching element 7a and the semiconductor switching element 7b are disposed adjacent to each other on the heat dissipating metal substrate 6, and drain electrodes of the semiconductor switching element 7a and the semiconductor switching element 7b are bonded to and electrically connected to the heat dissipating metal substrate 6. The N bus bar 3 is disposed on the semiconductor switching element 7a and the semiconductor switching element 7b, and the source electrode 9a of the semiconductor switching element 7a and the source electrode 9b of the semiconductor switching element 7b are joined to and electrically connected to the N bus bar 3. Thus, the drain electrodes and the source electrodes of the semiconductor switching elements 7a and 7b are electrically connected in parallel to each other, thereby forming a pair of arms. The N bus bar 3 is connected to the control ground terminal 4, and one end portion is output to the outside of the resin mold 1. A bonding wire 8 is electrically connected to the gate pad 10a of the semiconductor switching element 7a and the gate pad 10b of the semiconductor switching element 7b, an end of the bonding wire 8 is electrically connected to the control gate terminal 5, and the control gate terminal 5 is output to the outside of the resin mold 1. The power semiconductor module 100 is sealed by the resin mold 1.

The semiconductor switching elements 7a and 7b are bonded to the heat dissipating metal substrate 6 by soldering, but the bonding method is not limited thereto, and other bonding methods such as silver sintering (japanese: Ag シンター) may be used. The heat dissipating metal substrate 6 is a heat dissipating fin made of Copper, but is not limited thereto, and may be a member made of another substrate material such as a DBC (Direct Bonded Copper) substrate in which a ceramic insulating substrate, which is an insulating material in which metal foils are Bonded by soldering or the like, and a base plate made of Copper are Bonded.

The power semiconductor module 100 is sealed by a resin mold 1 formed by transfer molding, for example. However, the present invention is not limited to this, and a resin case impregnated with gel may be used instead of the resin mold 1.

Fig. 3 is an equivalent circuit diagram of the power semiconductor module 100 according to embodiment 1. In fig. 3, MOSFETs (metal oxide semiconductor field effect transistors) are shown as the semiconductor switching element 7a and the semiconductor switching element 7b, but the present invention is not limited to this, and IGBTs (insulated gate bipolar transistors), bipolar transistors, or the like may be used. In the description, when an IGBT or a bipolar transistor is used, a portion serving as a "drain" is a "collector", and a portion serving as a "source" is an "emitter". In addition, although fig. 3 shows a structure in which the parasitic diode of the MOSFET is used as the free wheeling diode, when a semiconductor switching element having no parasitic diode such as an IGBT is used, the free wheeling diode may be connected in reverse parallel to the semiconductor switching element.

In fig. 3, the P-side parasitic inductance 21a, the N-side parasitic inductance 23a, and the gate control signal parasitic inductance 25a are parasitic inductances possessed by a wiring connected to the semiconductor switching element 7a, and the P-side parasitic inductance 21b, the N-side parasitic inductance 23b, and the gate control signal parasitic inductance 25b are parasitic inductances possessed by a wiring connected to the semiconductor switching element 7 b. The P-side common inductor 22, the N-side common inductor 24, the gate control signal common inductor 26, and the ground control signal common inductor 27 of the power semiconductor module 100, which are common to the semiconductor switching element 7a and the semiconductor switching element 7b, are shown as other inductance components.

Next, the structure and effects of the power semiconductor module 100 according to embodiment 1 will be described. There are mainly two causes of current imbalance that occurs between the semiconductor switching element 7a and the semiconductor switching element 7 b. The first cause is caused by a deviation of parasitic inductance between PN electrodes. When the sum of the inductance components of the P-side parasitic inductance 21a and the N-side parasitic inductance 23a of the semiconductor switching element 7a in fig. 3 is La, the sum of the inductance components of the P-side parasitic inductance 21b and the N-side parasitic inductance 23b of the semiconductor switching element 7b is Lb, the current time variation at the time of switching of the semiconductor switching element 7a is dla/dt, and the current time variation at the time of switching of the semiconductor switching element 7b is dIb/dt, a voltage difference represented by Δ Vds of expression (1) is generated in the drain-source voltage between the semiconductor switching element 7a and the semiconductor switching element 7 b.

ΔVds＝La(dIa/dt)－Lb(dIb/dt) (1)

In the semiconductor switching element, since the conduction current changes when the drain-source voltage changes, a current imbalance occurs due to the generation of the drain-source voltage difference Δ Vds. The current imbalance can be suppressed by adding an inductance for suppressing the variation in parasitic inductance between the PN electrodes of the semiconductor switching element 7a and the semiconductor switching element 7b, but the addition of the inductance causes a problem of an increase in surge voltage and a complicated configuration.

In the power semiconductor module 100 according to embodiment 1, as shown in fig. 2, the semiconductor switching element 7a and the semiconductor switching element 7b are disposed adjacent to each other on the heat-dissipating metal substrate 6 and bonded thereto, and the N bus bar 3 is disposed on the semiconductor switching element 7a and the semiconductor switching element 7b and bonded thereto, whereby the drain electrodes and the source electrodes of the semiconductor switching element 7a and the semiconductor switching element 7b are electrically connected in parallel. The parasitic inductance of the semiconductor switching element increases in proportion to the length of the current path and decreases in inverse proportion to the area of the current path. In the power semiconductor module 100, the P-side parasitic inductances 21a and 21b and the N-side parasitic inductances 23a and 23b are made smaller by shortening the distance between the semiconductor switching element 7a and the semiconductor switching element 7b as the current path and providing a connection by a bus bar having a large area of the current path instead of a connection by a general bonding wire. As a result, La, which is the sum of the inductance components of the P-side parasitic inductance 21a and the N-side parasitic inductance 23a, and Lb, which is the sum of the inductance components of the P-side parasitic inductance 21b and the N-side parasitic inductance 23b, are reduced, and the drain-source voltage difference Δ Vds is reduced, thereby suppressing the current imbalance. The shorter the distance between the semiconductor switching element 7a and the semiconductor switching element 7b, the more the current imbalance can be suppressed. Therefore, the distance between the closest points of the semiconductor switching elements 7a and 7b is set to be, for example, within 5 mm.

The second cause of the current imbalance between the semiconductor switching element 7a and the semiconductor switching element 7b is caused by the deviation of the gate voltage due to the deviation of the ground potential and the deviation of the control signal. The variation in the ground potential between the semiconductor switching elements is caused by the variation in the product of N-side parasitic inductances 23a and dIa/dt and the variation in the product of N-side parasitic inductances 23b and dIb/dt. The deviation of the control signal is caused by the magnetic coupling of the gate control signal parasitic inductance 25a and the gate control signal parasitic inductance 25b with the respective parasitic inductances in the circuit, and the magnitude of the influence of the magnetic coupling is proportional to the magnitude of the inductance value and the magnitude of the temporal change in the current flowing through the respective parasitic inductances in the circuit.

In the power semiconductor module 100 according to embodiment 1, as shown in fig. 2, the semiconductor switching element 7a and the semiconductor switching element 7b are disposed adjacent to each other on the heat-dissipating metal substrate 6 and bonded to each other, and the N bus bar 3 is disposed on the semiconductor switching element 7a and the semiconductor switching element 7b and bonded to each other, whereby the N-side parasitic inductances 23a and 23b are made small, and the variation in the ground potential can be suppressed.

In the semiconductor switching element 7a and the semiconductor switching element 7b arranged adjacent to each other, the bonding wire 8 is connected to the gate pad 10a and the gate pad 10b, and the end of the bonding wire 8 is connected to the control gate terminal 5. Here, the gate control signal parasitic inductance 25a is parasitic inductance generated from the bonding wire 8 between the gate pad 10a of the semiconductor switching element 7a and the gate pad 10b of the semiconductor switching element 7 b. In the power semiconductor module 100 according to embodiment 1, the semiconductor switching element 7a and the semiconductor switching element 7b are disposed adjacent to each other, and the distance from the gate pad 10a of the semiconductor switching element 7a to the gate pad 10b of the semiconductor switching element 7b is short, so that the gate control signal parasitic inductance 25a can be suppressed. The gate control signal parasitic inductance 25b is a parasitic inductance generated from the bonding wire 8 to the gate pad 10b of the semiconductor switching element 7b, and is almost negligible. Since the magnitude of the influence of the magnetic coupling is proportional to the inductance value, the control signal variation can be suppressed. In the power semiconductor module 100 according to embodiment 1, since variations in the ground potential and variations in the control signal can be suppressed, variations in the gate voltage and current imbalance can be suppressed.

Among the magnetic fluxes generated by the power semiconductor module 100, the magnetic flux generated by the PN-to-PN current is the largest, and the PN-to-PN current is the dominant factor in the magnetic coupling between the gate control signal parasitic inductance 25a and the gate control signal parasitic inductance 25b and the parasitic inductances in the circuit. Thus, when the N bus bar 3, the heat dissipating metal substrate 6, and the bonding wires 8 are arranged such that the on direction of the current between PN flowing through the N bus bar 3 and the heat dissipating metal substrate 6 is orthogonal to the direction of the current flowing through the bonding wires 8, the variation in the control signal can be further suppressed, and the current imbalance can be further suppressed. When it is difficult to arrange the N bus bar 3, the heat dissipating metal substrate 6, and the bonding wire 8 so that the on direction of the PN-to-PN current and the direction of the current flowing through the bonding wire 8 are orthogonal to each other due to layout constraints, current imbalance can be suppressed by making the on direction of the PN-to-PN current and the direction of the current flowing through the bonding wire 8 at least different directions non-parallel. That is, it may be: the N bus bar 3 and the bonding wire 8 may be arranged such that the direction of the current flowing through the N bus bar 3 and the direction of the current flowing through the bonding wire 8 are different directions, and the heat dissipating metal substrate 6 and the bonding wire 8 may be arranged such that the direction of the current flowing through the heat dissipating metal substrate 6 and the direction of the current flowing through the bonding wire 8 are different directions.

The semiconductor switching element 7a and the semiconductor switching element 7b include source electrodes 9a and 9b and gate pads 10a and 10b on the front surface and a drain electrode on the back surface, but may include a first main electrode of any one of the source electrodes 9a and 9b and the drain electrode as main electrodes on the front surface and another second main electrode on the back surface. When the drain and gate pads 10a and 10b are provided on the front surface and the source electrodes 9a and 9b are provided on the rear surface, the positive and negative of the bus bars are reversed, and the control ground terminal 4 is connected to the heat dissipating metal substrate 6.

In the power semiconductor module 100 according to embodiment 1, the same effect can be obtained if the number of semiconductor switching elements is two or more. Further, since the current imbalance is affected by the amount of temporal change in the current, the effect of the current imbalance becomes large when the switching speed is high. Therefore, when not only silicon si (silicon), but also silicon carbide sic (silicon carbide), gallium nitride gan (gallium nitride), or a semiconductor switching element and a free wheeling diode that are formed of diamond and that can operate at high speed are used as a wide band gap semiconductor having a wider band gap than silicon, the power semiconductor module 100 according to embodiment 1 can obtain a more significant effect.

As described above, the power semiconductor module 100 according to embodiment 1 includes: a plurality of semiconductor switching elements 7a and 7b, the semiconductor switching elements 7a and 7b having first main electrodes 9a and 9b and gate pads 10a and 10b on front surfaces thereof and second main electrodes on rear surfaces thereof; a bus bar 3 to which first main electrodes 9a, 9b of the semiconductor switching elements 7a, 7b are respectively bonded; a heat dissipating metal substrate 6 to which second main electrodes of the semiconductor switching elements 7a and 7b are bonded, respectively; and a control gate terminal 5, wherein the control gate terminal 5 is connected to gate pads 10a, 10b of the semiconductor switching elements 7a, 7b by a bonding wire 8, and at least two of the plurality of semiconductor switching elements 7a, 7b are disposed adjacent to each other on the heat-dissipating metal substrate 6 to form one arm electrically connected in parallel, so that variations in control signals, variations in ground potential, and variations in parasitic inductance between the semiconductor switching elements 7a, 7b can be reduced without adding unnecessary members, and current imbalance between the semiconductor switching elements 7a, 7b can be suppressed.

Embodiment mode 2

Fig. 4 is a diagram showing an external appearance of a power semiconductor module 200 according to embodiment 2. Fig. 5 is a diagram showing an internal configuration of the power semiconductor module 200 according to embodiment 2, with the resin module 1a removed. The power semiconductor module 200 according to embodiment 2 is configured such that the power semiconductor module 100 according to embodiment 1 is arranged in mirror symmetry with the reference line 1000 as a symmetry axis.

The power semiconductor module 200 according to embodiment 2 includes a resin mold 1a, P bus bars 2a, 2b, N bus bar 3a, a control ground terminal 4a, a control gate terminal 5a, a heat radiation metal substrate 6a, semiconductor switching elements 7c, 7d, 7e, 7f, and bonding wires 8a, 8 b. The semiconductor switching elements 7c, 7d, 7e, and 7f are connected to one heat-dissipating metal substrate 6a and one N bus bar 3 a. The semiconductor switching element 7c and the semiconductor switching element 7d are disposed adjacent to each other on the heat dissipating metal substrate 6a, and drain electrodes of the semiconductor switching element 7c and the semiconductor switching element 7d are bonded to and electrically connected to the heat dissipating metal substrate 6 a. An N bus bar 3a is disposed on the semiconductor switching element 7c and the semiconductor switching element 7d, and a source electrode 9c of the semiconductor switching element 7c and a source electrode 9d of the semiconductor switching element 7d are joined to and electrically connected to the N bus bar 3 a. Further, the semiconductor switching element 7e and the semiconductor switching element 7f are disposed adjacent to each other on the heat dissipating metal substrate 6a, and drain electrodes of the semiconductor switching element 7e and the semiconductor switching element 7f are joined to and electrically connected to the heat dissipating metal substrate 6 a. An N bus bar 3a is disposed on the semiconductor switching element 7e and the semiconductor switching element 7f, and a source electrode 9e of the semiconductor switching element 7e and a source electrode 9f of the semiconductor switching element 7f are joined to and electrically connected to the N bus bar 3 a. A bonding wire 8a is connected to the gate pad 10c of the semiconductor switching element 7c and the gate pad 10d of the semiconductor switching element 7d, and an end of the bonding wire 8a is connected to the control gate terminal 5 a. Further, a bonding wire 8b is connected to the gate pad 10e of the semiconductor switching element 7e and the gate pad 10f of the semiconductor switching element 7f, and the end of the bonding wire 8b is also connected to the control gate terminal 5 a.

In the power semiconductor module 200 according to embodiment 2, the structures of the semiconductor switching elements 7c and 7d, the N bus bar 3a, and the heat dissipation metal substrate 6a are the same as those of the semiconductor switching elements 7a and 7b, the N bus bar 3, and the heat dissipation metal substrate 6 in the power semiconductor module 100 according to embodiment 1. Accordingly, similarly to the current imbalance between the semiconductor switching element 7a and the semiconductor switching element 7b of the power semiconductor module 100 according to embodiment 1, the current imbalance between the semiconductor switching element 7c and the semiconductor switching element 7d can be suppressed. The semiconductor switching elements 7e and 7f and the heat dissipating metal substrate 6a have mirror symmetry with respect to the semiconductor switching elements 7c and 7d and the heat dissipating metal substrate 6a, and have the same configurations as the semiconductor switching elements 7a and 7b, the N bus bar 3 and the heat dissipating metal substrate 6 in the power semiconductor module 100 according to embodiment 1, so that the current imbalance between the semiconductor switching element 7e and the semiconductor switching element 7f can be suppressed, similarly to the current imbalance between the semiconductor switching element 7a and the semiconductor switching element 7b in the power semiconductor module 100 according to embodiment 1.

Next, the effect of the power semiconductor module 200 of embodiment 2 alone, that is, the effect of suppressing the current imbalance between the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7f will be described. Fig. 6 is an equivalent circuit diagram of the power semiconductor module 200 according to embodiment 2. In fig. 6, the P-side parasitic inductance 21c, the N-side parasitic inductance 23c, and the gate control signal parasitic inductance 25c are parasitic inductances possessed by a wiring connected to the semiconductor switching element 7c, the P-side parasitic inductance 21d, the N-side parasitic inductance 23d, and the gate control signal parasitic inductance 25d are parasitic inductances possessed by a wiring connected to the semiconductor switching element 7d, the P-side parasitic inductance 21e, the N-side parasitic inductance 23e, and the gate control signal parasitic inductance 25e are parasitic inductances possessed by a wiring connected to the semiconductor switching element 7e, and the P-side parasitic inductance 21f, the N-side parasitic inductance 23f, and the gate control signal parasitic inductance 25f are parasitic inductances possessed by a wiring connected to the semiconductor switching element 7 f. The P-side primary common inductor 28a, the N-side primary common inductor 29a, and the gate control signal primary common inductor 30a of the power semiconductor module 200, which are common to the semiconductor switching element 7c and the semiconductor switching element 7d, are shown as other inductance components, and the P-side primary common inductor 28b, the N-side primary common inductor 29b, and the gate control signal primary common inductor 30b of the power semiconductor module 200, which are common to the semiconductor switching element 7e and the semiconductor switching element 7f, are shown. Note that the P-side common inductor 22a, the N-side common inductor 24a, the gate control signal common inductor 26a, and the ground control signal common inductor 27a of the power semiconductor module 200, which are common to the semiconductor switching elements 7c, 7d, 7e, and 7f, are shown.

With respect to the variation in the parasitic inductances between PN, the P-side parasitic inductances 21c, 21d, 21e, 21f and the N-side parasitic inductances 23c, 23d, 23e, 23f are suppressed to be extremely small, and the current imbalance due to these parasitic inductances can be suppressed. In the power semiconductor module 200 according to embodiment 2, the P-side primary common inductors 28a and 28b and the N-side primary common inductors 29a and 29b are made small and the current imbalance can be suppressed by connecting and connecting the electrodes of the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7f in parallel to one heat-dissipating metal substrate 6a and one N-bus bar 3 a.

In the power semiconductor module 200, the arrangement of the first semiconductor switching element unit including the semiconductor switching elements 7c and 7d and the second semiconductor switching element unit including the semiconductor switching elements 7e and 7f, the arrangement of the P bus bar 2a and the P bus bar 2b, the arrangement of the N bus bar 3a, and the arrangement of the heat dissipation metal substrate 6a are mirror-symmetrical with respect to the reference line 1000 as a symmetry axis, and therefore, the conduction paths of the currents are mirror-symmetrical in the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7 f. This can suppress the deviation between the P-side primary common inductor 28a and the P-side primary common inductor 28b and the deviation between the N-side primary common inductor 29a and the N-side primary common inductor 29b, and further suppress the current imbalance between the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7 f.

Here, although the heat dissipating metal substrate 6a is configured to be mirror-symmetrical about the reference line 1000 as a symmetry axis, a portion of the path through which the switching current flows may be mirror-symmetrical. Further, the control gate terminal 5a and the control ground terminal 4a, which are not paths through which the switching current flows, need not be mirror-symmetrical. In addition, in the case where a fixed point or the like is required for manufacturing, mirror symmetry is not required as long as it is not a position that affects a path through which a switching current flows.

Further, since the arrangement of the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7f, the arrangement of the P bus bar 2a and the P bus bar 2b, the structure of the N bus bar 3a, and the structure of the heat dissipating metal substrate 6a are mirror-symmetric about the reference line 1000 as a symmetry axis, the variation between the N-side primary common inductor 29a and the N-side primary common inductor 29b can be suppressed, and the variation in the ground potential between the semiconductor switching elements 7c, 7d, 7e, and 7f can be suppressed.

Further, a portion of the bonding wire 8a as the first bonding wire connecting the gate pad 10c of the semiconductor switching element 7c and the gate pad 10d of the semiconductor switching element 7d and a portion of the bonding wire 8b as the second bonding wire connecting the gate pad 10e of the semiconductor switching element 7e and the gate pad 10f of the semiconductor switching element 7f are arranged at positions mirror-symmetrical with respect to the reference line 1000 as a symmetry axis. This makes it possible to suppress variations in the control signals, because the gate control signal primary common inductance 30a, which is the parasitic inductance of the bonding wire 8a, and the gate control signal primary common inductance 30b, which is the parasitic inductance of the bonding wire 8b, are offset from each other, and the influence of the magnetic coupling between the bonding wire 8a and each parasitic inductance can be made to coincide with the influence of the magnetic coupling between the bonding wire 8b and each parasitic inductance. As a result, variations in gate voltage between the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7f can be suppressed, and current imbalance can be suppressed.

Embodiment 3

Fig. 7 is a diagram showing an external appearance of a power semiconductor module 300 according to embodiment 3. Fig. 8 is a diagram showing an internal configuration of a power semiconductor module 300 according to embodiment 3, with a resin module 1b removed. The power semiconductor module 300 according to embodiment 3 is different from the power semiconductor module 200 according to embodiment 2 in that a bonding wire 8c connected to a gate pad 10c of a semiconductor switching element 7c and a gate pad 10d of the semiconductor switching element 7d is connected to a control gate terminal 5b, a bonding wire 8d connected to a gate pad 10e of a semiconductor switching element 7e and a gate pad 10f of a semiconductor switching element 7f is connected to a control gate terminal 5c, a control gate terminal 5b as a first control gate terminal and a control gate terminal 5c as a second control gate terminal are mirror-symmetrical with respect to a reference line 1000 as a symmetry axis, and a bonding wire 8c as a first bonding wire and a bonding wire 8d as a second bonding wire are mirror-symmetrical with respect to the reference line 1000 as a symmetry axis. Further, although the shapes of the N bus bar 3b, the control ground terminal 4b, and the heat dissipating metal substrate 6b are different from those in the power semiconductor module 200 according to embodiment 2, the shapes of the N bus bar 3b and the heat dissipating metal substrate 6b are mirror-symmetrical with the reference line 1000 as the symmetry axis, which is the same as that in the power semiconductor module 200 according to embodiment 2.

In the power semiconductor module 200 according to embodiment 2, since the currents flowing through the bonding wires 8a and 8b flow to the single control gate terminal 5a, a large current flows through the gate control signal common inductor 26a shown in fig. 6. At this time, a voltage difference is generated in the gate control signal common inductor 26a controlling the gate terminal 5a, and this causes an erroneous on operation due to, for example, an increase in the gate voltage of each of the semiconductor switching elements 7c, 7d, 7e, and 7f, thereby restricting the switching speed. In the power semiconductor module 300 according to embodiment 3, the current flowing through one control gate terminal is reduced by connecting the bonding wire 8c as the first bonding wire and the bonding wire 8d as the second bonding wire to the respective different control gate terminals, and therefore, the voltage difference generated at the control gate terminal can be suppressed. This enables faster switching.

Embodiment 4

Fig. 9 is a diagram showing an external appearance of a power semiconductor module 400 according to embodiment 4. Fig. 10 is a diagram showing an internal configuration of a power semiconductor module 400 according to embodiment 4, with a resin module 1c removed. Fig. 11 is a diagram showing an internal configuration of a power semiconductor module 400 according to embodiment 4, from which a resin mold 1c, a negative arm N bus bar 12, and a control ground terminal 4c have been removed. Fig. 12 is a diagram showing an internal configuration of a power semiconductor module 400 according to embodiment 4, from which a resin mold 1c, a negative arm N bus bar 12, a control ground terminal 4c, and an intermediate bus bar 14 have been removed.

The power semiconductor module 400 according to embodiment 4 has two arms, i.e., a positive arm and a negative arm, each of which is composed of semiconductor switching elements, and has a shape called a "2-in-1 module" in which the positive arm and the negative arm are connected in series. The power semiconductor module 400 according to embodiment 4 is configured such that the power semiconductor module 200 according to embodiment 2 and the power semiconductor module 200 according to embodiment 2 are arranged in a manner such that two power semiconductor modules are arranged side by side with each other with the power semiconductor modules turned upside down.

When the upper half of the power semiconductor module 400 according to embodiment 4 is compared with the power semiconductor module 200 according to embodiment 2, the arrangement of the resin mold 1c, the ac bus bars 13a, 13b, the negative arm N bus bar 12, the control ground terminal 4c, the control gate terminal 5d, the heat dissipation metal substrate 6c, the semiconductor switching elements 7g, 7h, 7i, 7j, and the bonding wires 8e, 8f is the same as that of the power semiconductor module 200 according to embodiment 2, although the P bus bars 2a, 2b are replaced with the ac bus bars 13a, 13b, and the N bus bar 3a is replaced with the negative arm N bus bar 12. Drain electrodes of the semiconductor switching elements 7g, 7h, 7i, and 7j are connected to one heat dissipation metal substrate 6c, and the heat dissipation metal substrate 6c is connected to the ac bus bars 13a and 13 b. The source electrodes 9g, 9h, 9i, and 9j of the semiconductor switching elements 7g, 7h, 7i, and 7j are connected to one negative arm N bus bar 12, and the negative arm N bus bar 12 is connected to the control ground terminal 4 c. A bonding wire 8e is connected to the gate pad 10g of the semiconductor switching element 7g and the gate pad 10h of the semiconductor switching element 7h, and an end of the bonding wire 8e is connected to the control gate terminal 5 d. Further, a bonding wire 8f is connected to the gate pad 10i of the semiconductor switching element 7i and the gate pad 10j of the semiconductor switching element 7j, and the end of the bonding wire 8f is also connected to the control gate terminal 5 d.

When the lower half of the power semiconductor module 400 according to embodiment 4 is compared with the power semiconductor module 200 according to embodiment 2, the arrangement of the resin mold 1c, the positive arm P bus bars 11a, 11b, the intermediate bus bar 14, the control ground terminal 4d, the control gate terminal 5e, the heat dissipation metal substrate 6d, the semiconductor switching elements 7k, 7l, 7m, 7N, and the bonding wires 8g, 8h is the same as that of the power semiconductor module 200 according to embodiment 2, although the P bus bars 2a, 2b are replaced with the positive arm P bus bars 11a, 11b, and the N bus bar 3a is replaced with the intermediate bus bar 14. Drain electrodes of the semiconductor switching elements 7k, 7l, 7m, and 7n are connected to one heat dissipating metal substrate 6d, and the heat dissipating metal substrate 6d is connected to the positive arm P bus bars 11a and 11 b. The source electrodes 9k, 9l, 9m, and 9n of the semiconductor switching elements 7k, 7l, 7m, and 7n are connected to one intermediate bus bar 14, and the intermediate bus bar 14 is connected to the control ground terminal 4d and the heat dissipation metal substrate 6 c. A bonding wire 8g is connected to the gate pad 10k of the semiconductor switching element 7k and the gate pad 10l of the semiconductor switching element 7l, and an end of the bonding wire 8g is connected to the control gate terminal 5 e. Further, a bonding wire 8h is connected to the gate pad 10m of the semiconductor switching element 7m and the gate pad 10n of the semiconductor switching element 7n, and the end of the bonding wire 8h is also connected to the control gate terminal 5 e.

The semiconductor switching elements 7k, 7l, 7m, and 7N are connected in parallel via the heat dissipating metal substrate 6d and the intermediate bus bar 14 to form a positive arm, and the semiconductor switching elements 7g, 7h, 7i, and 7j are connected in parallel via the heat dissipating metal substrate 6c and the negative arm N bus bar 12 to form a negative arm. The heat dissipating metal substrate 6c serving as the drain potential of the negative arm is connected to the intermediate bus bar 14 serving as the source potential of the positive arm, and thereby the positive arm and the negative arm are connected with the heat dissipating metal substrate 6c as a connection point. Ac busbars 13a and 13b as ac electrodes are connected to a heat dissipating metal substrate 6c as a connection point between the positive arm and the negative arm. The intermediate bus bar 14 is disposed to overlap the negative arm N bus bar 12, and the intermediate bus bar 14 and the negative arm N bus bar 12 have a double-layer structure.

Next, the structure and effects of the power semiconductor module 400 according to embodiment 4 will be described. Since the directions of the currents flowing through the intermediate bus bar 14 and the negative arm N bus bar 12 are opposite to each other, and the intermediate bus bar 14 and the negative arm N bus bar 12 are arranged to overlap each other, the currents flowing through the intermediate bus bar 14 and the negative arm N bus bar 12 act to cancel out the parasitic inductance. Here, the intermediate bus bar 14 is a ground potential which is the source potential of the semiconductor switching elements 7k, 7l, 7m, and 7n, and the parasitic inductance of the intermediate bus bar 14 can be reduced, thereby suppressing the current imbalance in the semiconductor switching elements 7k, 7l, 7m, and 7 n. Similarly, the negative arm N bus bar 12 is a ground potential which is the source potential of the semiconductor switching elements 7g, 7h, 7i, and 7j, and the parasitic inductance of the negative arm N bus bar 12 can be reduced, thereby suppressing the current imbalance in the semiconductor switching elements 7g, 7h, 7i, and 7 j. In addition, by reducing the sum of the parasitic inductances between PN, the surge voltage associated with switching can be suppressed, and high-speed switching can be realized.

While various exemplary embodiments have been described in the present application, the various features, modes, and functions described in one or more embodiments are not limited to the application to specific embodiments, and can be applied to the embodiments alone or in various combinations.

Therefore, countless modifications not illustrated are assumed to be within the technical scope disclosed in the present application. For example, the case where at least one component is modified, added, or omitted is included, and the case where at least one component is extracted and combined with the components of the other embodiments is also included.