阅读说明：本技术 具有低电感栅极交叉的功率半导体模块 (Power semiconductor module with low inductance gate crossing ) 是由 A·施罗德 S·基辛 F·莫恩 J·舒德勒 于 2020-04-02 设计创作，主要内容包括：一种功率半导体模块(10)包括：主衬底(12),该主衬底具有被分隔成导电区域(24)的主导电层(18)；功率半导体芯片(22),其中每个功率半导体芯片(22)具有第一功率电极(38)、第二功率电极(40)和栅极电极(42),其中每个功率半导体芯片(22)利用第一功率电极(38)结合到主导电层(18),并且其中第一组(36a)的功率半导体芯片(22)经由第二功率电极(40)并联连接,并且第二组(36b)的功率半导体芯片(22)经由第二功率电极(40)并联连接；电连接到第一组(36a)中的功率半导体芯片(22)的第一电极(38)、第二电极(40)或栅极电极(42)中的一个的第一控制导体(62a、64a),以及电连接到第二组(36b)中的功率半导体芯片(22)的第一电极(38)、第二电极(40)或栅极电极(42)中的一个的第二控制导体(62b、64b)；第一绝缘层(54)和第一绝缘层(54)上的第一导电层(46),其中第一控制导体的至少一部分由第一导电层的至少一部分(58a,58b)提供；以及第二绝缘层(56)和第二绝缘层(56)上的第二导电层(48),其中第二控制导体(56)的至少一部分由第二导电层(48)的至少一部分(60a,60b)提供。主导电层(18)、第一绝缘层(54)、第一导电层(46)、第二绝缘层(56)和第二导电层(48)彼此叠置。(A power semiconductor module (10) includes: a host substrate (12) having a main conductive layer (18) separated into conductive regions (24); power semiconductor chips (22), wherein each power semiconductor chip (22) has a first power electrode (38), a second power electrode (40) and a gate electrode (42), wherein each power semiconductor chip (22) is bonded to the main conductive layer (18) with the first power electrode (38), and wherein the power semiconductor chips (22) of the first group (36a) are connected in parallel via the second power electrode (40), and the power semiconductor chips (22) of the second group (36b) are connected in parallel via the second power electrode (40); a first control conductor (62a, 64a) electrically connected to one of the first electrode (38), the second electrode (40) or the gate electrode (42) of the power semiconductor chips (22) in the first group (36a), and a second control conductor (62b, 64b) electrically connected to one of the first electrode (38), the second electrode (40) or the gate electrode (42) of the power semiconductor chips (22) in the second group (36 b); a first insulating layer (54) and a first conductive layer (46) on the first insulating layer (54), wherein at least a portion of the first control conductor is provided by at least a portion (58a, 58b) of the first conductive layer; and a second insulating layer (56) and a second conductive layer (48) on the second insulating layer (56), wherein at least a portion of the second control conductor (56) is provided by at least a portion (60a, 60b) of the second conductive layer (48). The main conductive layer (18), the first insulating layer (54), the first conductive layer (46), the second insulating layer (56), and the second conductive layer (48) are stacked on each other.)

1. A power semiconductor module (10) comprising:

a host substrate (12), the host substrate (12) having a main conductive layer (18) separated into conductive regions (24);

power semiconductor chips (22), wherein each power semiconductor chip (22) has a first power electrode (38), a second power electrode (40) and a gate electrode (42), wherein each power semiconductor chip (22) is bonded to the main conductive layer (18) with the first power electrode (38), and wherein power semiconductor chips (22) of a first group (36a) are connected in parallel via the second power electrode (40), and power semiconductor chips (22) of a second group (36b) are connected in parallel via the second power electrode (40);

a first insulating layer (54) and a first conductive layer (46) on the first insulating layer (54);

wherein the first conductive layer (46) provides a first gate conductor region (58a) electrically connected to the gate electrodes (42) of the first group (36a) and a first auxiliary emitter conductor region (58b) electrically connected to the power electrodes (38, 40) of the first group (36 a);

a second insulating layer (56) and a second conductive layer (48) on the second insulating layer (56);

wherein the second conductive layer (48) provides a second gate conductor region (60a) electrically connected to the gate electrodes (42) of the second group (36b) and a second auxiliary emitter conductor region (60b) electrically connected to the power electrodes (38, 40) of the second group (36 b);

wherein the main conductive layer (18), the first insulating layer (54), the first conductive layer (46), the second insulating layer (56), and the second conductive layer (48) are stacked with respect to each other.

2. The power semiconductor module (10) according to claim 1,

wherein the first gate conductor region (58a) and the second gate conductor region (60a) overlap each other;

wherein the first auxiliary emitter conductor region (58b) and the second auxiliary emitter conductor region (60b) overlap each other.

3. The power semiconductor module (10) according to claim 1 or 2,

wherein the first auxiliary emitter conductor region (58b) is disposed on both sides of the first gate conductor region (58 a);

wherein the second auxiliary emitter conductor region (60b) is disposed at both sides of the second gate conductor region (60 a).

4. A power semiconductor module (10) comprising:

a host substrate (12), the host substrate (12) having a main conductive layer (18) separated into conductive regions (24);

power semiconductor chips (22), wherein each power semiconductor chip (22) has a first power electrode (38), a second power electrode (40) and a gate electrode (42), wherein each power semiconductor chip (22) is bonded to the main conductive layer (18) with the first power electrode (38), and wherein power semiconductor chips (22) of a first group (36a) are connected in parallel via the second power electrode (40), and power semiconductor chips (22) of a second group (36b) are connected in parallel via the second power electrode (40);

a first insulating layer (54) and a first conductive layer (46) on the first insulating layer (54);

wherein the first conductive layer (46) provides a first auxiliary emitter conductor region (58b) electrically connected to the power electrodes (38, 40) of the first group (36a) and a second auxiliary emitter conductor region (60b) electrically connected to the power electrodes (38, 40) of the second group (36 b);

a second insulating layer (56) and a second conductive layer (48) on the second insulating layer (56);

wherein the second conductive layer (48) provides a first gate conductor region (58a) electrically connected to the gate electrodes (42) of the first group (36a) and a second gate conductor region (60a) electrically connected to the gate electrodes (42) of the second group (36 b);

wherein the main conductive layer (18), the first insulating layer (54), the first conductive layer (46), the second insulating layer (56), and the second conductive layer (48) are stacked with respect to each other.

5. The power semiconductor module (10) of claim 4,

wherein the first gate conductor region (58a) and the first auxiliary emitter conductor region (60a) overlap each other;

wherein the second gate conductor region (60a) and the second auxiliary emitter conductor region (60b) overlap each other.

6. Power semiconductor module (10) according to claim 4 or 5,

wherein a third conductive layer (68) provides a third auxiliary emitter conductor region (58c) electrically connected to the first auxiliary emitter conductor region (58a) and a fourth auxiliary emitter conductor region (60c) electrically connected to the second auxiliary emitter conductor region (60 a).

7. The power semiconductor module (10) according to any one of claims 4 to 6,

wherein the first auxiliary emitter conductor region (58b), the first gate conductor region (58a) and the third auxiliary emitter conductor region (58c) overlap each other;

wherein the second auxiliary emitter conductor region (60b), the second gate conductor region (60a) and the fourth auxiliary emitter conductor region (60c) overlap each other.

8. Power semiconductor module (10) according to one of the preceding claims,

wherein the first conductive layer (46) comprises first elongate strips (58a, 58b) and the second conductive layer (48) comprises second elongate strips (60a, 60 b);

wherein the first and second elongate strips (58a, 58b, 60a, 60b) run parallel to each other.

9. The power semiconductor module (10) according to any one of the preceding claims, further comprising:

a third conductive layer (68) overlying the first conductive layer (46) and the second conductive layer (48), the third conductive layer (68) providing one or more third conductive regions.

10. Power semiconductor module (10) according to one of the preceding claims,

wherein an intermediate conductive layer (66) is arranged between the first conductive layer (46) and the second conductive layer (48);

wherein the intermediate conductive layer (66) is electrically floating.

11. Power semiconductor module (10) according to one of the preceding claims,

wherein the main conductive layer (18) of the main substrate (12) comprises a first control conductor region (24d, 24d ', 24e, 24 e') providing a portion of a first control conductor (62a, 64 a);

wherein the first control conductor region (24d, 24d ', 24e, 24 e') is connected with the first conductive layer (46) via at least one wire bond (44);

wherein the main conductive layer (18) of the host substrate (12) comprises a second control conductor region (24f, 24g) providing a portion of a second control conductor (62b, 64 b);

wherein the second control conductor region (24f, 24g) is connected with the second conductive layer (48) via at least one wire bond (44).

12. The power semiconductor module (10) according to any one of claims 1 to 3,

wherein the main conductive layer (18) comprises a main layer gate conductor region (24d, 24d ') and two main layer auxiliary emitter conductor regions (24e, 24 e'), the two main layer auxiliary emitter conductor regions (24e, 24e ') being arranged on both sides of the main layer gate conductor region (24d, 24 d');

wherein the main layer gate conductor region (24d, 24 d') is electrically interconnected with one of the first and second gate conductor regions (58a, 60 a);

wherein the main layer auxiliary emitter conductor region (24e, 24 e') is electrically interconnected with one of the first and second auxiliary emitter conductor regions (58a, 58 b);

wherein the main layer gate conductor region (24d, 24d ') and the third auxiliary emitter conductor region (24e, 24 e') are arranged such that they face one of the first and second gate conductor regions (58a, 60a) and one of the first and second auxiliary emitter conductor regions (58a, 58 b).

13. Power semiconductor module (10) according to one of the preceding claims,

wherein the power semiconductor chips (22) are arranged in parallel rows (34a, 34b) and the first and second conductive layers (46, 48) are arranged on the sides of the rows (34a, 34b) and run orthogonally to the rows (34a, 34 b).

14. The power semiconductor module (10) according to any one of claims 1 to 3 and 12,

wherein the power semiconductor chips (22) of the first group (36a) are arranged in two parallel first rows (34a) and the power semiconductor chips (22) of the second group (36b) are arranged in two parallel second rows (34b) arranged between the first rows (34 a);

wherein a first main layer gate conductor region (24 d') of the main conductive layer (18) is arranged outside a row (34a, 34b) of semiconductor chips (22) and is electrically connected to the first conductive layer (46);

wherein a second main layer gate conductor region (52a) is arranged between the second row (34b) of semiconductor chips (22) and is electrically connected to the second electrically conductive layer (48).

Technical Field

The present invention relates to the field of packaging of power semiconductors. In particular, the invention relates to a power semiconductor module.

Background

Half-bridge power modules form a key building block for various power electronics devices, such as motor drives or power inverters. The new module may include a silicon carbide (SiC) semiconductor that may exhibit enhanced performance compared to conventional silicon (Si) semiconductors: SiC devices provide high power density. In addition, since the switching speed of SiC devices is typically much higher than that of Si devices, there is an increasing need for low inductance module layouts to avoid voltage overshoot and potential damage of SiC devices.

The switching performance of the module is mainly determined by the commutation loop inductance of the module. Furthermore, the inductance of the gate connection and the mutual inductance between the commutation loop and the gate loop may affect the switching performance. To take full advantage of the fast switching capability of SiC devices, these inductances are as low as possible. In the case of parallel semiconductor chips, the individual inductances must also be well balanced.

WO 2018109069 a1 shows a power semiconductor module with two gate paths running partly parallel to each other in a conductive layer of an additional substrate.

US 5705848A relates to a power semiconductor module and mentions that stacked layers of insulating material and layers of conductive tracks result in a lower stray inductance.

Disclosure of Invention

It is an object of the invention to provide a compact power semiconductor module with a low gate path inductance.

This object is achieved by the subject matter of the independent claims. Further exemplary embodiments are apparent from the dependent claims and the following description.

The present invention relates to a power semiconductor module. A power semiconductor module may be a device that mechanically and electrically interconnects one or more power semiconductor chips with electrical conductors and terminals, such that the power semiconductor module may be used as a building block for larger machines, such as rectifiers, inverters, electrical drives, and the like. In particular, the power semiconductor module may be used in an electrical inverter of an electric or hybrid vehicle, i.e. for generating an AC voltage for an electric motor from a DC voltage from a battery.

The term "power" in a power semiconductor module and/or a power semiconductor chip may relate to the ability to handle currents of more than 10A and/or more than 100V.

According to an embodiment of the present invention, a power semiconductor module includes a main substrate having a main conductive layer separated into conductive regions. For example, the main substrate may be a DBC (direct bonded copper) substrate. The primary substrate may include an insulating layer, which may be made of ceramic, on which a conductive layer is deposited, which may be made of copper.

According to an embodiment of the invention, the power semiconductor module comprises power semiconductor chips, wherein each power semiconductor chip has a first power electrode, a second power electrode and a gate electrode, wherein each power semiconductor chip is bonded to the main conductive layer with the first power electrode, and wherein the power semiconductor chips of the first group are connected in parallel via the second power electrode and the power semiconductor chips of the second group are connected in parallel via the second power electrode. The power semiconductor chip may be a SiC chip. The power electrodes may be emitter electrodes and collector electrodes. The power electrodes may substantially cover the sides of the chip. At one side, the chip may be covered by a power electrode and a gate electrode.

The chips may be interconnected to form a half bridge. The chips of the first set may form either the high-side switch or the low-side switch of the half-bridge. The chips of the second group may form the other of the high-side switch or the low-side switch.

According to an embodiment of the invention, the power semiconductor module comprises a first control conductor electrically connected to one of the first electrode, the second electrode or the gate electrode of the power semiconductor chips in the first group, and a second control conductor electrically connected to one of the first electrode, the second electrode or the gate electrode of the power semiconductor chips in the second group. For example, the first and second control conductors may be gate conductors. However, it is also possible that one or both of the control conductors are auxiliary emitter conductors or conductors for conducting other signals.

Each control conductor may comprise a control conductor region of the main conductive layer. The chips and/or terminals of the module may be connected to these conductor areas.

According to an embodiment of the invention, a power semiconductor module comprises a first insulating layer and a first conductive layer on the first insulating layer, wherein at least a part of the first control conductor is provided by at least a part of the first conductive layer; and a second conductive layer comprising a second insulating layer and on the second insulating layer, wherein at least a portion of the second control conductor is provided by at least a portion of the second conductive layer.

A first control conductor may connect an electrode (such as one of a power electrode or a gate electrode) with the first control terminal. Similarly, a second control conductor may connect an electrode (such as one of the power electrodes or a gate electrode) with the second control terminal. The first control conductor may be considered a first control trace of the module. The second control conductor may be considered a second control trace of the module.

The control conductor region of the primary substrate may be connected to the first and second conductive regions. The first insulating layer may be attached to the main conductive layer of the main substrate, and the second insulating layer may be attached to the first conductive layer on the first insulating layer.

According to an embodiment of the present invention, the main conductive layer, the first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer are stacked with respect to each other. From the view onto the substrate, the first and second conductive layers (and the main conductive region) may overlap each other, which may reduce the area of the module for controlling the conductors.

The stacked conductive layers electrically insulated from each other may be considered a multi-level control conductor arrangement.

Furthermore, with the stacked conductive layers, crossing of the paths of the control conductors can be achieved. This crossover can be achieved without long wire bonds, which must span other portions of the module.

With this arrangement, the power density of the power semiconductor module (e.g. SiC half-bridge) can be increased. High power density can be achieved by reducing the space required for control conductors, such as gate traces, connecting the semiconductor gates together with the module terminals, for example.

Additionally, with the arrangement of the control conductors, the thermal properties of the module can be increased without changing the size of the substrate. Alternatively, the substrate size may be reduced while maintaining thermal performance. When the control conductor is a gate conductor, a low inductance gate connection can be achieved, as may be required for a fast switching device.

By using a multi-level control conductor arrangement, the module area occupied by the control conductors can be significantly reduced. Thus, the total substrate size can be reduced, while the area of the chip can be kept constant. With this aspect, power density can be enhanced, which is an important step towards highly compact module layouts for space demanding applications.

Instead of reducing the substrate size, the module area for chip placement may be increased. With this aspect, heat transfer resistance can be reduced, resulting in improved cooling efficiency. Higher cooling efficiency may enhance the current rating of the module. Alternatively, a larger module area may also facilitate placing more chips, which will correspondingly increase current capability.

Finally, using a multi-stage arrangement of control conductors may provide a low inductance and space-saving alternative as a design basis and may thus reduce the design effort.

The multi-layer arrangement may be provided with one, two or more additional substrates attached to the main substrate.

For example, the first insulating layer and the first conductive layer may be provided by the first substrate. The second insulating layer and the second conductive layer may be provided by a second substrate. The first substrate and/or the second substrate may be a DBC (direct copper clad) substrate, a DBA (direct aluminum clad) substrate, an AMB (Active metal bridging) ceramic substrate, a PCB (printed circuit board), an LTCC (Low Temperature co-fired ceramic) substrate, a laminated bus bar, a flexible foil, or the like.

Alternatively, the first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer may be provided by one substrate, such as a multilayer circuit board. The use of a separate multilayer substrate (e.g., fabricated as a printed circuit board) in combination with a DBC host substrate may combine inexpensive and mature multilayer PCB technology for temperature insensitive components such as gate traces with a DBC host substrate having excellent thermal properties.

According to an embodiment of the invention, the first conductive layer comprises a first elongated strip and the second conductive layer comprises a second elongated strip. The strip may be a portion of the conductive layer that is at least 5 times the width. The strip may be part of a control conductor trace running through the module.

The first elongated strip (i.e., a portion of the first control conductor) and the second elongated strip (i.e., a portion of the second control conductor) may run parallel to each other. This may reduce the inductance of the control loops, as their effective area coupled to the magnetic field may be reduced.

In general, a multi-layer control conductor arrangement may be used for different trace topologies. For example, each of the first and second conductive layers may comprise a single signal trace without a kelvin emitter (i.e. an auxiliary emitter conductor connecting the emitter of the power semiconductor and the auxiliary emitter terminal of one group). It is also possible that each of the first and second conductive layers comprises a gate conductor trace and an auxiliary emitter trace. It is also possible that the control conductor is arranged such that the two emitter traces are arranged beside (or above and below) the gate trace, which may result in a coaxial arrangement of the emitter trace and the gate trace.

According to an embodiment of the invention, the first control conductor is a first gate conductor and is electrically connected to the gate electrodes of the power semiconductor chips of the first group. Also, the second control conductor may be a second gate conductor and may be electrically connected to the gate electrodes of the power semiconductor chips of the second group. For example, in both cases, the electrical connection may also be made in a gate conductor region of the main conductive layer of the host substrate, which may be connected to the respective first and second conductive layers via wire bonding.

It is possible that the chips of the first group form the high side switches of the half-bridge and the chips of the second group form the low side switches of the half-bridge (or vice versa). The first gate conductor and/or the first conductive layer may be electrically connected to the gates of the chips of the first group, i.e. to the high-side switch or the low-side switch. The second gate conductor and/or the second conductive layer may be electrically connected to the gates of the chips of the second group, i.e. to the low-side switch or the high-side switch.

According to an embodiment of the invention, the first control conductor is a gate conductor electrically connected to the gate electrodes of the power semiconductor chips of the first or second group, and the second control conductor is an auxiliary emitter conductor electrically connected to one of the first and second power electrodes of the power semiconductor chips of the first or second group. The emitter conductors may be connected to emitter electrodes of the respective chips. It is possible that both the gate conductor and the emitter conductor connected to the chips of the same group are led to overlap each other. It is also possible that the emitter conductor is guided over the gate conductor, i.e. at a higher level with respect to the main substrate than the gate conductor.

According to an embodiment of the invention, the first control conductor is an auxiliary emitter conductor electrically connected to one of the first and second power electrodes of the power semiconductor chips of the first or second group, and the second control conductor is a gate conductor electrically connected to the gate electrodes of the power semiconductor chips of the first or second group. It is possible that the emitter conductor may be led below the gate conductor, i.e. at a lower level than the gate conductor with respect to the main substrate.

According to an embodiment of the invention, the first conductive layer provides a first gate conductor region and a first auxiliary emitter conductor region. The second conductive layer may provide a second gate conductor region and a second auxiliary emitter conductor region. In such an arrangement, the gate conductor region and the emitter conductor region may be arranged next to each other. The gate conductor region and the emitter conductor region may be arranged on the same level with respect to the main substrate.

According to an embodiment of the invention, the first gate conductor region and the second gate conductor region overlap each other. The gate conductors may overlap each other when viewed from above the module. Also, the first auxiliary emitter conductor region and the second auxiliary emitter conductor region may overlap each other. The auxiliary emitter conductors may overlap each other when viewed from above the module.

According to an embodiment of the present invention, the first auxiliary emitter conductor region is disposed on both sides of the first gate conductor region. Also, second auxiliary emitter conductor regions may be disposed on both sides of the second gate conductor region. In other words, the auxiliary emitter conductor region and the corresponding gate conductor region may be coaxially arranged parallel to the main substrate.

According to an embodiment of the invention, the first conductive layer provides a first auxiliary emitter conductor region electrically connected to the power electrodes in the first group and a second auxiliary emitter conductor region connected to the power electrodes in the second group. In this arrangement, the auxiliary emitter conductor regions for different chip sets may be arranged at one level with respect to the main substrate.

According to an embodiment of the invention, the second conductive layer provides a first gate conductor region electrically connected to the gate electrodes in the first group and a second gate conductor region connected to the gate electrodes in the second group. In such an arrangement, the gate conductor regions for different chip sets may be arranged at one level with respect to the host substrate.

According to an embodiment of the invention, the first gate conductor region and the first auxiliary emitter conductor region overlap each other, and/or the second gate conductor region and the second auxiliary emitter conductor region overlap each other. In other words, the gate conductor regions for different chip sets may be arranged at a first level with respect to the main substrate, while the auxiliary emitter conductor regions for different chip sets may be arranged at a second level with respect to the main substrate.

According to an embodiment of the invention, the power semiconductor module further comprises a third conductive layer overlapping the first conductive layer and the second conductive layer, the third conductive layer providing one or more third conductive regions. In general, it is possible to use more than two stacked conductive layers for transmitting the control signal.

According to an embodiment of the invention, the first conductive layer provides a first auxiliary emitter conductor region and a second auxiliary emitter conductor region. The second conductive layer may provide a first gate conductor and a second gate conductor region. The third conductive layer may provide a third auxiliary emitter conductor region electrically connected to the first auxiliary emitter conductor region and a fourth auxiliary emitter conductor region electrically connected to the second auxiliary emitter conductor region.

The first auxiliary emitter conductor region, the first gate conductor region and the third auxiliary emitter conductor region may overlap each other. In this way, the first and third auxiliary emitter conductor regions and the corresponding first gate conductor region may be coaxially arranged in a direction orthogonal to the main substrate.

Also, the second auxiliary emitter conductor region, the second gate conductor region, and the fourth auxiliary emitter conductor region may overlap each other. In this way, the second and fourth auxiliary emitter conductor regions and the corresponding second gate conductor region may be coaxially arranged in a direction orthogonal to the main substrate.

According to an embodiment of the invention, the intermediate conductive layer is arranged between the first conductive layer and the second conductive layer. This intermediate conductive layer may electrically shield the first conductive layer and the second conductive layer from each other.

The intermediate conductive layer may be electrically floating. This may mean that the intermediate conductive layer is electrically disconnected from the rest of the module. The intermediate layer may also be at a defined potential, for example for an auxiliary power supply. The intermediate layer may also be connected to control traces and/or may be adapted and/or used to conduct control signals.

According to an embodiment of the invention, the main conductive layer of the main substrate comprises a first control conductor region providing a part of the first control conductor. The first control conductor region may be a first gate conductor region or a first auxiliary emitter conductor region. The first control conductor region may be connected to the first conductive layer by at least one wire bond.

According to an embodiment of the invention, the main conductive layer of the main substrate comprises a second control conductor region providing a part of the second control conductor. The second control conductor region may be a second gate conductor region or a second auxiliary emitter conductor region. The second control conductor may be connected to the second conductive layer by at least one wire bond.

These wire bonds need not span over other conductors. Wire bonds may interconnect conductive layers disposed directly next to each other, which may result in shorter wire bonds and low inductance.

According to an embodiment of the present invention, the main conductive layer comprises a main layer gate conductor region and two main layer auxiliary emitter conductor regions arranged on both sides of the main layer gate conductor region. These conductor regions of the main substrate may be arranged coaxially on the main substrate.

According to an embodiment of the invention, the main layer gate conductor region is electrically interconnected with one of the first and second gate conductor regions, wherein the main layer auxiliary emitter conductor region is electrically interconnected with one of the first and second auxiliary emitter conductor regions. Such connections may be made via wire bonds, which may also be short because they directly connect adjacent conductive areas.

According to an embodiment of the present invention, the main layer gate conductor region and the main layer auxiliary emitter conductor region are arranged such that they face towards one of the first and second gate conductor regions and one of the first and second auxiliary emitter conductor regions. In other words, corresponding conductors of the coaxial conductor arrangement may be placed side by side and such interconnection of each wire bond may be shortened.

According to an embodiment of the invention, the power semiconductor chips are arranged in parallel rows, and the first and second conductive layers are arranged on the sides of the rows and run orthogonally to the rows. One or more rows may provide a first set of chips and/or one or more rows may provide a second set of chips. A stacked arrangement of control conductors may be placed beside the rows and may be used for collecting control signals of different rows. In particular, when the control terminals are arranged opposite a row of chips, the superimposed arrangement of control conductors may be used to distribute control signals from the terminals to different rows. The stacked first and second conductive layers provide an intersection of control signal paths.

According to an embodiment of the invention, the power semiconductor chips of the first group are arranged in two parallel first rows and the power semiconductor chips of the second group are arranged in two parallel second rows, which are arranged between the first rows. The second set may be a low side of the half bridge and the first set may be a high side of the half bridge. In this way, the chips may be arranged coaxially and/or the current path through the module may be made up of two loops with opposite current orientations.

The first main layer gate conductor region of the main conductive layer may be arranged outside the row of semiconductor chips and electrically connected to the first conductive layer. The first conductive layer may be electrically connected to all gates of the chips in the first group. The first conductive layer may also be electrically connected to a first gate terminal of the module.

The second main layer gate conductor region may be disposed between the second rows of semiconductor chips and electrically connected to the second conductive layer. The second main layer gate conductor region may be provided by a substrate attached to the main substrate. The second main layer conductive region may be electrically connected to all gates of the chips of the second group. The second main layer conductive layer may also be electrically connected to a second gate terminal of the module.

In this way, the gate signal distribution can be very compact and can have a low inductance.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

The subject matter of the invention will be explained in more detail below with reference to exemplary embodiments shown in the drawings.

Fig. 1 schematically shows a top view of a power semiconductor module according to an embodiment of the invention.

Fig. 2 schematically shows a top view of a power semiconductor module according to a further embodiment of the invention.

Fig. 3 shows a side view of a part of the power semiconductor module of fig. 1.

Fig. 4A, 4B, 4C and 4D schematically show arrangements of control conductor regions that can be used in the modules shown in fig. 1 and 2.

The reference symbols used in the drawings and their meanings are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference numerals in the figures.

Detailed Description

Fig. 1 shows a power semiconductor module 10 with a main substrate 12 which is composed of an insulating layer 14 (for example made of ceramic) which is sandwiched between two conductive layers 16, 18 (for example made of copper). The lower conductive layer 16 may be used to attach the cooling body to the module 10.

Several terminals 20 and power semiconductor chips 22 are bonded to the upper conductive layer 18, which may be considered as the main conductive layer 18. The conductive layer 18 is structured into several conductive regions 24 that are separated from one another relative to the substrate (although they may be electrically interconnected with one another via additional components of the module 10). In addition, several additional substrates 26, 28, temperature sensors 30 and resistors 32 are bonded to the conductive layer 18.

The temperature sensor 30 may be bonded to the first temperature sensor region 24h of the conductive layer 18 and electrically connected with the second temperature sensor region 24h via wire bonds 44. The respective terminals 20h are coupled to the two temperature sensor areas 24 h.

The power semiconductor chips 22 are arranged in four rows 34a, 34b, of which two outer rows 34a are connected in parallel in a first group 36a and form the high side switches of a half bridge, and two inner rows 34b are connected in parallel in a second group 36b and form the low side switches of the half bridge.

Each power semiconductor chip 22 has a first power electrode 38 (collector electrode) on the side bonded to the main conductive layer 18 and a second power electrode 40 (emitter electrode) on the opposite side, on which a gate electrode 42 is also arranged. For reasons of clarity in fig. 1, only one chip 22 is provided with reference numerals for the electrodes 38, 40, 42.

The chips 22 of the outer row 34a (i.e. the chips in the first group 36a forming the high-side switch) are bonded to two DC + regions 24a of the main conductive layer 18, to which two DC + regions 24a are also bonded a DC + terminal 20a, which DC + terminals 20a electrically interconnect the DC + regions 24a with each other.

With their second power electrodes 40m, the chips 22 of the outer row 34a are electrically connected to the AC regions 24c of the main conductive layer 18 via wire bonds 44 (only some of which are referenced in fig. 1). The AC region 24c is U-shaped and is arranged within the DC + region 24 a. The AC terminal 20c is coupled to the AC region 24c at a side opposite the DC + terminal 20 a.

The chips 22 of the inner row 34b (i.e. the chips in the second group 36b forming the low-side switch) are connected with their first power electrodes 38 to the AC area 24c and in particular to the arms of the U-shaped piece. These chips 22 are electrically connected via wire bonds 44 with their second power electrodes 40 to the DC-region 24b, which is arranged within the arms of the U-shaped piece of the AC-region 24 c. On the side of the module 10 where the DC + terminals 20 are arranged, the DC-terminals 20b are also bonded to the DC-regions 24 b.

Due to the arrangement of the terminals 20a, 20b, 20c and the areas 24a, 24b, 24c, current paths are generated through the module 10 in two oppositely directed current loops, which significantly reduces the overall inductance of the module 10.

At the side of the module 10, where the AC terminals 20c are arranged, further control terminals 20d, 20e, 20f, 20g, 20i are provided.

One of the DC + regions 24a travels to the side of the module 10 where the terminals 20c, 20d, 20e, 20g, 20f, 20h are arranged. There, the auxiliary collector terminal 20i is bonded to the DC + region 24 a.

The high-side gate terminal 20d is bonded to the high-side gate region 24d and the high-side auxiliary emitter terminal 20e is bonded to two high-side auxiliary emitter regions 24e, which two high-side auxiliary emitter regions 24e are arranged on both sides of the high-side gate region 24d to form a coaxial arrangement with low inductance.

Similarly, on the opposite side of the alternating current terminal 20c, a low side gate terminal 20f is joined to a low side gate region 24f, and a low side auxiliary emitter terminal 20g is joined to two low side auxiliary emitter regions 24g, the two low side auxiliary emitter regions 20g being arranged on either side of the low side gate region 24f to form a further coaxial arrangement with low inductance.

The two coaxial terminals and conductor arrangements are electrically connected to emitter electrodes 40 and gate electrodes 42 of the chip 22 with further coaxial arrangements, these emitter electrodes 40 and gate electrodes 42 being provided in part by the further substrates 26, 28.

Additional high side gate regions 24 d' of layer 18 are disposed outside of rows 34a of chips 22. The gate electrodes 42 of the chips 22 of row 34a (i.e., first group 36a) are electrically connected to this gate region 24d via wire bonds 44 and resistors 32. The emitter electrodes 40 of these chips are connected by bond wires to the high-side auxiliary emitter regions 24e or to further high-side auxiliary emitter regions 24e 'arranged on one or both sides of the further high-side gate regions 24 d'.

The further high-side gate region 24d 'and the further high-side auxiliary emitter region 24 e' are electrically connected via wire bonds 44 with regions of a first conductive layer 46 of the control substrate 28, which first conductive layer 46 of the control substrate 28 is attached to the module 10 over the AC region 24c beside the rows 34a, 34 b.

The gate electrodes 42 of the chips 22 of row 34b are connected to the gate regions 52a of the conductive layer 50 of the low side gate substrate 26. The emitter electrodes 40 of the dies 22 of row 34b are connected to two auxiliary emitter regions 52b of the conductive layer 50. The auxiliary emitter regions 52b are arranged on both sides of the gate region 52a to form a coaxial arrangement with low inductance.

The low side gate substrate 26 is attached to the DC-region 24b and runs parallel to the rows 34b and/or between these rows 34 b. Also, the longitudinal and/or elongated regions 52a, 52b travel in this direction.

The conductive layer 50 of the low side gate substrate 26 is disposed on an insulating layer of the low side gate substrate 26 that is attached to the DC-region 24 b.

The gate region 52a and the auxiliary emitter region 52b are electrically connected via wire bonds 44 with regions of the second conductive layer 48 of the control substrate 28, which second conductive layer 48 is arranged above the first conductive layer of the control substrate 28. Also, low side gate region 24f and low side auxiliary emitter region 24g are electrically connected to second conductive layer 48 via wire bonds 44.

The control substrate 28 has a first insulating layer 54 attached to the main substrate 12 and/or the main conductive layer 18. In particular, the first insulating layer is attached to the AC region 24 c. The first conductive layer 46 is attached to and/or disposed on the first insulating layer 54. The second insulating layer 56 of the control substrate 28 is attached to the first conductive layer 46. The second conductive layer 48 is attached to and/or disposed on the second insulating layer 56.

Generally, the main conductive layer 18 and the layers 54, 46, 56, 48 are stacked relative to one another in this order.

For example, the control substrate 28 may be a multi-layer PCB providing all layers 54, 46, 56, 48. Furthermore, the control substrate 28 may be made of a first substrate and a second substrate, wherein the first substrate provides the first insulating layer 54 and the first conductive layer 46, and the second substrate provides the second insulating layer 56 and the second conductive layer 48.

The first conductive layer 46 is separated into a first gate region 58a and two first auxiliary emitter regions 58b, which two first auxiliary emitter regions 58b run on both sides of the first gate region 58a to form a coaxial arrangement. Similarly, the second conductive layer 48 is separated into a second gate region 60a and two second auxiliary emitter regions 60b, which two second auxiliary emitter regions 60b run on both sides of the second gate region 60a to form a coaxial arrangement.

Note that in the above and below, the term "first" may relate to a high-side portion of the half bridge formed by the module 10, and the term "second" may relate to a low-side portion of the half bridge. For example, the first gate region 58a may be a high side gate region and the second gate region 60a may be a low side gate region.

The regions 58a, 58b, 60a, 60b are elongate strips or tracks running substantially parallel to each other. The direction of these strips or tracks may be orthogonal to the direction of the chip rows 34a, 34 b.

The first gate region 58a is electrically connected (e.g., via wire bonds 44) to the conductive regions 24d and 24 d'. All of these regions form the first gate conductor 62 a.

The first auxiliary emitter region 58b is electrically connected (e.g., via wire bonds 44) with the conductive regions 24e and 24 d'.

All these regions form the first auxiliary emitter conductor 64 a.

Both the first gate conductor 62a and the first auxiliary emitter conductor 64a can be considered as a first control conductor of the module 10.

The second gate region 60a is electrically connected (e.g., via wire bonds 44) to the conductive regions 24f and 52 a. All of these regions form the second gate conductor 62 b.

The second auxiliary emitter region 60b is electrically connected (e.g., via wire bonds 44) with the conductive regions 24g and 52 b. All these regions form the second auxiliary emitter conductor 64 b.

Both the second gate conductor 62b and the second auxiliary emitter conductor 64b may be considered as a second control conductor of the module 10.

Fig. 2 shows in a more schematic way a stacked arrangement of first control conductors 62a, 64a and second control conductors 62b, 64 b.

In fig. 2, groups 36a, 36b and rows 34a, 34b of chips are depicted. The emitter (second power) electrodes 40 and/or the gate electrodes 42 of the chips 22 in the first group 36a may be connected with the respective terminals 20d, 20e via first control conductors 62a, 64 a. Due to the arrangement of the chips 22 in the rows 34a, 34b, the first control conductors 62a, 64a branch off from the terminals 20d, 20e into two arms, which run along the two outer rows 34 a.

On the other hand, the emitter (second power) electrodes 40 and/or gate electrodes 42 of the chips 22 in the second group 36b may be connected with the respective terminals 20f, 20g via second control conductors 62b, 64 b. Due to the arrangement of the chips 22 in the rows 34a, 34b, the second control conductors 62a, 64a from the terminals 20f, 20g cross the first control conductors 62a, 64a to run along the two inner rows 34 b.

Interleaving is performed with a first conductive layer 46 and a second conductive layer 48 stacked on top of each other. In addition, the conductive layers 46, 48 run along and/or overlap each other, which may reduce gate loop inductance.

Due to the overlying conductive layers 46, 48, the wire bonds 44 required to interconnect portions of the control conductors 62a, 64a, 62b, 64b may be relatively short, as they need not span a longer distance, but may interconnect adjacent conductive areas.

Fig. 3 shows a side view of a portion of the module 10 of fig. 1 with a control substrate 28. It is shown that the intermediate conductive layer 66 may be disposed between the first conductive layer 46 and the second conductive layer 48.

The intermediate layer 66, which may be made of Cu, may be sandwiched between two insulating layers 56, 56' made of ceramic, and may be electrically floating. This may electrically shield the first and second conductive layers 46, 48 from each other.

Fig. 4A to 4D show possible arrangements of gate conductor regions 58a, 60a and auxiliary emitter conductor regions 58b, 60b, 58c, 60c, which may alternatively be used in the embodiments shown in fig. 1 to 3. It has to be noted that additionally the areas corresponding to the electrical connections of the first set 36a and/or the high side switches may also be exchanged with the areas electrically connected to the second set 36b and/or the low side switches.

Fig. 4A shows an embodiment in which the gate conductor regions 58a, 60a are arranged in the same layer 46, 48 as the corresponding auxiliary emitter conductor regions 58b, 60 b. In addition, only one auxiliary emitter conductor region 58b, 60b is provided per layer 46, 48. The first and second gate conductor regions 58a and 60a may overlap each other, and/or the first and second auxiliary emitter conductor regions 58b and 60b may overlap each other.

Fig. 4B shows the embodiment of fig. 1 and 3, wherein the gate conductor regions 58a, 60a are arranged in the same layer 46, 48 as two corresponding auxiliary emitter conductor regions 58B, 60B, which are arranged on both sides of the gate conductor regions 58a, 60 a. The first auxiliary emitter conductor region 58b may be disposed on both sides of the first gate conductor region 58a, and/or the second auxiliary emitter conductor region 60b may be disposed on both sides of the second gate conductor region 60 a.

Fig. 4C shows an embodiment in which the gate conductor regions 58a, 60a are arranged in a different layer 46, 48 than the corresponding auxiliary emitter conductor regions 58b, 60 b.

For example, the first conductive layer 46 may provide a first gate conductor region 58a that is electrically connected to the gate electrodes 42 in the first group 36a and a second gate conductor region 60a that is connected to the gate electrodes 42 in the second group 36 b. The second conductive layer 48 may provide a first auxiliary emitter conductor region 58b electrically connected to the power electrodes 38, 40 in the first group 36a and a second auxiliary emitter conductor region 60b connected to the power electrodes 38, 40 in the second group 36 b. However, the first and second conductive layers 46, 48 may be interchanged here.

The first gate conductor region 58a and the first auxiliary emitter conductor region 60a may overlap each other, and/or the second gate conductor region 60a and the second auxiliary emitter conductor region 60b may overlap each other.

Fig. 4D shows an embodiment having a third conductive layer 68, the third conductive layer 68 overlying the first and second conductive layers 46, 48. An additional insulating layer may be provided between third conductive layer 68 and second conductive layer 48.

Like the first and second conductive layers 46, 48, the third conductive layer may provide one or more conductive regions 58c, 60c that may be used as part of the control conductors 62a, 64a, 62b, 64 b.

In fig. 4D, the conductive regions are arranged to form a coaxial arrangement in a direction orthogonal to the direction of extension of the layers 46, 48, 68.

The first conductive layer 46 provides a first auxiliary emitter conductor region 58b and a second auxiliary emitter conductor region 60 b. The second conductive layer 48 provides a first gate conductor region 58a and a second gate conductor region 60 a. The third conductive layer provides a third auxiliary emitter conductor region 58c electrically connected to the first auxiliary emitter conductor region 58a and a fourth auxiliary emitter conductor region 60c electrically connected to the second auxiliary emitter conductor region 60 a.

The first auxiliary emitter conductor region 58b, the first gate conductor region 58a and the third auxiliary emitter conductor region 58c may overlap each other, and/or the second auxiliary emitter conductor region 60b, the second gate conductor region 60a and the fourth auxiliary emitter conductor region 60c may overlap each other.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or controller or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope.

List of reference numerals

10 power semiconductor module

12 substrate

14 insulating layer

16 lower conductive layer

18 main conductive layer

20a DC + terminal

20b DC terminal

20c AC terminal

20d high side gate terminal

20e high side auxiliary emitter terminal

20f low side gate terminal

20g low side auxiliary emitter terminal

20h temperature sensor terminal

20i auxiliary collector terminal

22 power semiconductor chip

24a DC + region

24b DC-region

24c AC region

24 d' high side gate region

24 d' additional high side gate region

24e high side auxiliary emitter region

24 e' additional high side auxiliary emitter region

24 f' low side gate region

24g low side auxiliary emitter region

24h temperature sensor area

26 low side gate substrate

28 control substrate

30 temperature sensor

32 resistor

34a outer row

34b inner row

36a first group

36b second group

38 first power electrode

40 second power electrode

42 gate electrode

44 wire bonding

46 first conductive layer

48 second conductive layer

50 conductive layer

52a gate region

52b auxiliary emitter region

54 first insulating layer

56 second insulating layer

56' additional insulating layer

58a first gate region

58b first auxiliary emitter region

60a second gate region

60b second auxiliary emitter region

62a first gate conductor

62b second gate conductor

64a first auxiliary emitter conductor

64b second auxiliary emitter conductor

66 intermediate conductive layer

68 third conductive layer