阅读说明：本技术 一种多碳化硅芯片并联的模块 (Module with multiple silicon carbide chips connected in parallel ) 是由 庄伟东 成浩 赵冲 于 2021-10-26 设计创作，主要内容包括：本发明涉及碳化硅模块领域,公开了一种多碳化硅芯片并联的模块,其技术方案要点是包括铜底板,所述铜底板上方连接有覆铜基板,所述覆铜基板上设置有芯片、键合线、正极功率端子、负极功率端子和交流输出端子,其特征是：所述芯片包括若干碳化硅芯片和附带的续流二极管,对应连接的所述碳化硅芯片和续流二极管形成碳化硅芯片组,所有的碳化硅芯片组形成半桥型模块,所述半桥型模块包括上桥臂和下桥臂,上桥臂中碳化硅芯片组间的键合线与下桥臂中碳化硅芯片组间的键合线的角度为90度,使得模块的电感值有了明显的降低,增加了模块的输出能力。(The invention relates to the field of silicon carbide modules, and discloses a module with multiple silicon carbide chips connected in parallel, which adopts the technical scheme that the module comprises a copper base plate, wherein a copper-clad substrate is connected above the copper base plate, and the copper-clad substrate is provided with a chip, a bonding wire, a positive power terminal, a negative power terminal and an alternating current output terminal, and is characterized in that: the chip comprises a plurality of silicon carbide chips and attached freewheeling diodes, the silicon carbide chips and the freewheeling diodes which are correspondingly connected form a silicon carbide chip set, all the silicon carbide chip sets form a half-bridge type module, the half-bridge type module comprises an upper bridge arm and a lower bridge arm, and the angle between a bonding wire between the silicon carbide chip sets in the upper bridge arm and a bonding wire between the silicon carbide chip sets in the lower bridge arm is 90 degrees, so that the inductance value of the module is obviously reduced, and the output capacity of the module is improved.)

1. The utility model provides a parallelly connected module of many carborundum chips, includes the copper bottom plate, copper bottom plate top is connected with the copper-clad base plate, be provided with chip, bonding wire, anodal power terminal, negative pole power terminal and interchange output terminal, characterized by on the copper-clad base plate: the chip comprises a plurality of silicon carbide chips and attached freewheeling diodes, the silicon carbide chips and the freewheeling diodes which are correspondingly connected form a silicon carbide chip set, all the silicon carbide chip sets form a half-bridge type module, the half-bridge type module comprises an upper bridge arm and a lower bridge arm, and the angle between a bonding wire between the silicon carbide chip sets in the upper bridge arm and a bonding wire between the silicon carbide chip sets in the lower bridge arm is 90 degrees.

2. The module of claim 1, wherein the silicon carbide chips are connected in parallel: the silicon carbide chip groups included on the same bridge arm are arranged up and down separately.

3. The module of claim 2, wherein the module comprises: the quantity of the terminal pins of the positive power terminal and the negative power terminal corresponds to the quantity of the silicon carbide chips.

4. The module of claim 3, wherein the silicon carbide chips are connected in parallel: the terminal pin of the positive power terminal is respectively connected with the collector of the silicon carbide chip and the cathode of the fly-wheel diode, and the terminal pin of the negative power terminal is respectively connected with the emitter of the silicon carbide chip and the anode of the fly-wheel diode.

5. The module of claim 4, wherein the silicon carbide chips are connected in parallel: the silicon carbide chip and the positive power terminal and the negative power terminal are connected by connecting the copper layers of the copper-clad substrates.

Technical Field

The invention relates to the field of silicon carbide modules, in particular to a module with multiple silicon carbide chips connected in parallel.

Background

With the development of power electronic technology, the continuous demand for high efficiency and high power density design makes the performance of power semiconductors reach the limit of silicon materials. Wide bandgap semiconductor materials, including silicon carbide and GaN (gallium nitride), can reduce both conduction and switching losses compared to Si (silicon) materials. However, as switching speeds and operating frequencies increase, the impact of parasitic parameters in the module package also increases. For example, copper-clad substrates (DBC substrates) and wire-bond package structures are widely used in multi-chip power module packages due to their mature manufacture, low cost, and good thermal performance, however, this packaging method results in a large parasitic inductance in the current loop. The large parasitic inductance causes overvoltage of the power semiconductor device, causes high switching loss, and also causes electromagnetic interference problems such as high-frequency oscillation.

When silicon carbide chips are used, often in multi-chip parallel connections to increase the current handling capability of the module, parasitic inductances within the multi-chip power module become more complex due to their parallel structure. In order to fully utilize the advantages of wide bandgap semiconductor materials, it is important to solve the problem of multi-chip power module oscillation caused by parasitic inductance.

Disclosure of Invention

The invention aims to provide a module with a plurality of silicon carbide chips connected in parallel, so that the inductance value of the module is obviously reduced, and the output capacity of the module is improved.

The technical purpose of the invention is realized by the following technical scheme: the utility model provides a module that many carborundum chips were parallelly connected, includes the copper bottom plate, copper bottom plate top is connected with the copper-clad base plate, be provided with chip, bonding wire, positive power terminal, negative power terminal and interchange output terminal on the copper-clad base plate, the chip includes a plurality of carborundum chips and subsidiary freewheel diode, and what correspond the connection carborundum chip and freewheel diode form the carborundum chipset, and all carborundum chipsets form half-bridge type module, half-bridge type module includes upper bridge arm and lower bridge arm, and the angle of the bonding wire between the carborundum chip group in the upper bridge arm and the bonding wire between the carborundum chip group in the lower bridge arm is 90 degrees.

In a preferred embodiment of the present invention, the silicon carbide chip groups included in the same arm are vertically separated from each other.

In a preferred embodiment of the present invention, the number of the pins of the positive power terminal and the negative power terminal corresponds to the number of the silicon carbide chips.

In a preferred embodiment of the present invention, the terminal pin of the positive power terminal is connected to the collector of the silicon carbide chip and the cathode of the freewheeling diode, and the terminal pin of the negative power terminal is connected to the emitter of the silicon carbide chip and the anode of the freewheeling diode.

In a preferred embodiment of the present invention, the silicon carbide chip and the positive power terminal and the negative power terminal are connected to each other by connecting copper layers of copper-clad substrates.

In conclusion, the invention has the following beneficial effects: the total parasitic inductance can be effectively reduced, and lower switching loss, lower turn-off overvoltage and lower electromagnetic interference can be realized under the condition of not increasing any manufacturing difficulty.

Drawings

FIG. 1 is a schematic diagram of a half-bridge module of a silicon carbide chip according to the present invention;

FIG. 2 is a schematic diagram of the inductance of a half-bridge module;

FIG. 3 is a schematic structural view of a conventional half-bridge type silicon carbide module;

fig. 4 is a schematic diagram of a half-bridge module inductor according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

The invention provides a module with multiple silicon carbide chips connected in parallel, which comprises a copper base plate, wherein a copper-clad substrate is connected above the copper base plate, a chip, a bonding wire, a positive power terminal, a negative power terminal and an alternating current output terminal are arranged on the copper-clad substrate, the chip comprises a plurality of silicon carbide chips and an attached freewheeling diode, the silicon carbide chips and the freewheeling diode which are correspondingly connected form a silicon carbide chip set, all the silicon carbide chip sets form a half-bridge module, the half-bridge module comprises an upper bridge arm and a lower bridge arm, and the angle between the bonding wire between the silicon carbide chip sets in the upper bridge arm and the bonding wire between the silicon carbide chip sets in the lower bridge arm is 90 degrees. The silicon carbide chip groups included on the same bridge arm are arranged up and down separately.

Specifically, the number of the terminal pins of the positive power terminal and the negative power terminal corresponds to the number of the silicon carbide chips.

Specifically, the terminal pin of the positive power terminal is respectively connected with the collector of the silicon carbide chip and the cathode of the fly-wheel diode, and the terminal pin of the negative power terminal is respectively connected with the emitter of the silicon carbide chip and the anode of the fly-wheel diode.

Specifically, the silicon carbide chip and the positive power terminal and the negative power terminal are connected to each other by connecting copper layers of the copper-clad substrate.

In a general half-bridge module, as shown in fig. 2, when calculating the inductance and mutual inductance of the circuit, two silicon carbide chips T1 and T2 of the upper arm are connected in parallel, two silicon carbide chips T3 and T4 of the lower arm are connected in parallel, the circuit inductance of the silicon carbide chip due to the bonding wire connected to the chip exists in the emitter circuit of each silicon carbide chip, and the positive power terminal P reaches Ld1 of the copper layer of the copper-clad substrate for the first circuit in fig. 2; lo1 connecting bonding wires of the upper and lower bridge arm silicon carbide chips and a copper layer of the ceramic copper-clad substrate; ls1 from the lower arm silicon carbide chip bonding wire and the copper layer of the copper-clad substrate to the negative power terminal N is directed to the second loop, as well as the first loop, with Ld2, Lo2 and Ls2, and mutual inductance exists between Ld1 and Ld2, between Lo1 and Lo2 and between Ls1 and Ls 2.

As shown in fig. 3, which is a conventional half-bridge module, reference numeral 10 is a first terminal pin of a positive power terminal, and reference numeral 20 is a first terminal pin of a negative power terminal. Taking two sets of parallel chips as an example, the upper bridge arm has two silicon carbide chips (marked as 9a and 9 b), and each silicon carbide chip is attached with an anti-parallel fly-wheel diode (marked as 8a and 8 b). Correspondingly, the lower arm of the module has silicon carbide chips (marked as 9c and 9 d), and each silicon carbide chip is attached with an anti-parallel freewheeling diode (marked as 8c and 8 d). All silicon carbide chips are soldered to copper clad substrates (referenced 6, 7) and to the floor of the module (referenced 12) by means of a solder layer. The first terminal pin 10 of the positive power terminal of the module is connected to the lower arm chip through the copper layer of the copper-clad substrate, then through the bonding wires (labeled 11a, 11 b), the copper layer on the DBC and the bonding aluminum wire (labeled 12 a), and the lower arm chip is finally connected to the first terminal pin of the negative power terminal through the bonding aluminum wire (labeled 13a, 13 b) and the copper layer of the DBC. The calculation result shows that the mutual inductances among three groups of Ld1 and Ld2, Lo1 and Lo2, Ls1 and Ls2 are respectively as follows: 11.91nH, 7.66nH, 17.61 nH. Since the angle between the two current paths is almost zero, this results in a large mutual inductance between the two current paths, as does the other current paths.

In the module with multiple silicon carbide chips connected in parallel according to the present invention, as shown in fig. 1, two groups of chips connected in parallel are also taken as an example, positive power terminals of the two groups of chips connected in parallel on the left side are added to two terminal pins as inputs, that is, a first terminal pin 10 and a second terminal pin 11; the negative power terminal is added with two terminal pins as output, namely a first terminal pin 20 and a second terminal pin 21; meanwhile, a single silicon carbide chip and an attached anti-parallel fly-wheel diode are used as a chip set, and the two chip sets of the upper bridge arm and the lower bridge arm are relatively and vertically arranged (such as the fly-wheel diode 8a and the silicon carbide chip 9a of the upper bridge arm, the fly-wheel diode 8c and the silicon carbide chip 9c of the lower bridge arm), so that the angle between a bonding wire on the single chip set of the upper bridge arm and the bonding wire between the silicon carbide chip sets of the lower bridge arm are 90 degrees, and the angle between the bonding wire between the silicon carbide chip sets of the upper bridge arm and the bonding wire between the silicon carbide chip sets of the lower bridge arm is 90 degrees; and two chip sets of the same bridge arm are separately arranged up and down (such as the freewheeling diode 8a, the silicon carbide chip 9a, the freewheeling diode 8b and the silicon carbide chip 9b of the upper bridge arm), and the other parallel chip arrangements are also as described above.

As shown in fig. 4, the angles between the current loops are large, and the calculation result shows that the mutual inductances between three groups of Ld1 and Ld2, Lo1 and Lo2, Ls1 and Ls2 are respectively: 6.7nH, 0.008nH and 5.49nH, the mutual inductance value of the current loop is respectively reduced by 43.7%, 99.9% and 68.8%, so that the inductance value of the module is obviously reduced, and the output capability of the module is increased.

In summary, the module with multiple silicon carbide chips connected in parallel can effectively reduce the total parasitic inductance, and can realize lower switching loss, lower turn-off overvoltage and lower electromagnetic interference without increasing any manufacturing difficulty.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.