阅读说明：本技术 集成扇出型封装件 (Integrated fan-out package ) 是由 王之妤 郭宏瑞 胡毓祥 廖思豪 于 2020-05-18 设计创作，主要内容包括：一种集成扇出型(InFO)封装件,包含包封体、管芯、多个导电结构以及重布线结构。管芯和导电结构由包封体包封。导电结构包围管芯。重布线结构安置在包封体上。重布线结构包含多个布线图案、多个导通孔以及多个对准标记。多个导通孔内连布线图案。多个对准标记中的至少一个与包封体实体接触。(An integrated fan out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structure are encapsulated by an encapsulant. The conductive structure surrounds the die. The rewiring structure is disposed on the enclosure. The rewiring structure comprises a plurality of wiring patterns, a plurality of via holes and a plurality of alignment marks. A plurality of via holes interconnecting the wiring patterns. At least one of the plurality of alignment marks is in physical contact with the encapsulant.)

1. An integrated fan-out package, comprising:

an enclosure;

a semiconductor die encapsulated by the encapsulant;

a rewiring structure disposed over the semiconductor die and the encapsulant, the rewiring structure including a plurality of wiring patterns, a plurality of vias interconnecting the plurality of wiring patterns, and a plurality of alignment marks, at least one of the plurality of alignment marks including a plurality of groups,

wherein a first group among the plurality of groups includes a plurality of first grid patterns arranged parallel to and spaced apart from each other, a second group among the plurality of groups includes a plurality of second grid patterns arranged parallel to and spaced apart from each other, and a first extending direction of the plurality of first grid patterns is different from a second extending direction of the plurality of second grid patterns.

Technical Field

The disclosed embodiments relate to an integrated fan-out package.

Background

The semiconductor industry has experienced rapid growth due to the continuing improvement in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). To a large extent, this improvement in integration density comes from the repeated reduction in minimum feature size, which allows more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize smaller areas than previous packages. Currently, integrated fan-out packages are becoming increasingly popular due to their compactness. However, there are many challenges associated with integrating fan-out packages.

Disclosure of Invention

According to an embodiment of the present disclosure, an integrated fan-out package includes an encapsulant, a semiconductor die, and a redistribution structure. The semiconductor die is encapsulated by an encapsulant. The rewiring structure is arranged above the semiconductor die and the encapsulating body and comprises a plurality of wiring patterns, a plurality of through holes and a plurality of alignment marks, the wiring patterns are connected in the through holes, and at least one of the alignment marks comprises a plurality of groups. The first group among the plurality of groups includes a plurality of first grid patterns arranged parallel to and spaced apart from each other, the second group among the plurality of groups includes a plurality of second grid patterns arranged parallel to and spaced apart from each other, and a first extending direction of the plurality of first grid patterns is different from a second extending direction of the plurality of second grid patterns.

According to an embodiment of the present disclosure, an integrated fan-out package includes an encapsulant, a semiconductor die, and a redistribution structure. The semiconductor die is encapsulated by an encapsulant. The rewiring structure is disposed above the enclosure. The rewiring structure includes a first dielectric layer, a second dielectric layer, a first alignment mark, and a second alignment mark. The second dielectric layer is stacked on the first dielectric layer. The first alignment mark is disposed on the first dielectric layer. The second alignment mark is disposed on the second dielectric layer, and each of the first alignment mark and the second alignment mark respectively includes a plurality of groups. The first group among the plurality of groups includes a plurality of first grid patterns arranged parallel to and spaced apart from each other, the second group among the plurality of groups includes a plurality of second grid patterns arranged parallel to and spaced apart from each other, and the first alignment mark is different from the second alignment mark in size, pattern, and/or orientation.

According to an embodiment of the present disclosure, a method of manufacturing an integrated fan-out package includes: forming a die and a plurality of conductive structures over a carrier, wherein the plurality of conductive structures surround the semiconductor die; encapsulating the die and the plurality of conductive structures by an encapsulant; and forming a rewiring structure over the encapsulation, wherein the rewiring structure includes a plurality of alignment marks, and at least one of the plurality of alignment marks includes a plurality of groups, wherein a first group among the plurality of groups includes a plurality of first grid patterns arranged in parallel to each other and spaced apart from each other, a second group among the plurality of groups includes a plurality of second grid patterns arranged in parallel to each other and spaced apart from each other, and a first extending direction of the plurality of first grid patterns is different from a second extending direction of the plurality of second grid patterns.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1Y are schematic cross-sectional views illustrating a fabrication process of an integrated fan out (InFO) package, according to some embodiments of the present disclosure.

Fig. 2A to 2D are schematic top views illustrating various configurations of the first alignment mark AM1 in fig. 1H.

Fig. 3A-3B are schematic cross-sectional views illustrating intermediate stages of a fabrication process of an InFO package according to some alternative embodiments of the present disclosure.

Fig. 4 is a schematic cross-sectional view showing a package-on-package (PoP) structure.

Fig. 5 is a cross-sectional view showing an InFO package according to some alternative embodiments of the present disclosure.

Fig. 6A-6I are schematic cross-sectional views illustrating intermediate stages of a fabrication process of an InFO package according to some alternative embodiments of the present disclosure.

Fig. 7A-7D are schematic cross-sectional views illustrating intermediate stages of a fabrication process of an InFO package according to other embodiments of the present disclosure.

Description of the reference numerals

10. 20, 30: an integrated fan-out package;

20': a second package;

100. 500: a rewiring structure;

102: rewiring the conductive layer;

104: a dielectric layer;

106: rerouting the via hole;

200: a conductive structure;

300: a die;

300 a: a rear surface;

300 b: a front surface;

300 c: an active surface;

310: a semiconductor substrate;

320: a conductive pad;

330: a passivation layer;

340: a post-passivation layer;

350: a through hole;

360: a protective layer;

400: an enclosure;

400 a: an encapsulating material;

510. 512: a seed material layer;

510a, 510b, 510c, 512b, 514a, 514b, 514c, 516 a: a seed layer;

520a, 520b, 520c, 522a, 522b, 540a, 540b, 542a, 542b, 542c, 544 a: a conductive pattern;

530: a first dielectric layer;

532: a second dielectric layer;

534: a third dielectric layer;

530a, 532 a: a layer of dielectric material;

600. 700: a conductive terminal;

1000: a package on package (PoP) structure;

AD: an adhesive layer;

AM 1: a first alignment mark;

AM 2: a second alignment mark;

AM 3: a third alignment mark;

AR: an active region;

BR: a boundary region;

c: a carrier;

CV 1: a first via hole;

CV 2: a second via hole;

DB: a peeling layer;

g1, G2, G3, G4: a group;

OP1, OP1', OP2, OP2', OP3, OP4, OP 5: an opening;

PR1, PR1', PR2, PR 3: a photoresist layer;

RP1, RP 1': a first wiring pattern;

RP2, RP 2': a second wiring pattern;

RP 3: a third wiring pattern;

T_AM1、T_AM2、T_CV1、T_CV2、T₅₃₀、T₅₃₂: a top surface;

TP: and (7) carrying the tape.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below … …," "below … …," "lower," "above … …," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows for testing of 3D packages or 3DIC, use of probes and/or probe cards, and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods incorporating intermediate verification of known good dies to increase yield and reduce cost.

Fig. 1A-1Y are schematic cross-sectional views illustrating a fabrication process of an integrated fan-out (InFO) package 10 according to some embodiments of the present disclosure. Referring to fig. 1A, a carrier C having a release layer (de-bonding layer) DB formed thereon is provided. In some embodiments, carrier C is a glass substrate. However, other materials may be adapted as the material of the carrier C as long as they can withstand the subsequent manufacturing process while supporting the elements formed thereon. In some embodiments, the release layer DB is a light-to-heat conversion (LTHC) release layer formed on a glass substrate. The release layer DB allows the structure formed on the carrier C in the subsequent process to be released from the carrier C.

The rewiring structure 100 is formed over the carrier C. In some embodiments, the rewiring structure 100 is attached to the peeling layer DB. In some embodiments, the redistribution structure 100 includes a dielectric layer 104, a redistribution conductive layer 102, and a plurality of redistribution vias 106. The rewired conductive layer 102 may be constituted by a plurality of rewired conductive patterns. For simplicity, the dielectric layer 104 is shown as one monolayer of dielectric layer and the rerouting conductive layer 102 is shown embedded in the dielectric layer 104 in fig. 1A. Nevertheless, from a manufacturing process perspective, the dielectric layer 104 is comprised of two dielectric layers, and the rerouting conductive layer 102 is sandwiched between two adjacent dielectric layers. As shown in fig. 1A, the rerouted vias 106 are also embedded in the dielectric layer 104. In some embodiments, the material of the rerouting conductive layer 102 and the rerouting vias 106 includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. The rerouting conductive layer 102 may be formed by, for example, electroplating, deposition and/or photolithography, and etching. In some embodiments, the material of the dielectric layer 104 includes polyimide (polyimide), epoxy resin (epoxy resin), acrylic resin (acrylic resin), phenol resin (phenol resin), benzocyclobutene (BCB), Polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. The dielectric layer 104 may be formed, for example, by a suitable fabrication technique, such as spin-on coating, Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like.

It should be noted that the number of rerouting conductive layers 102 and the number of dielectric layers 104 shown in fig. 1A are for illustration purposes only and the disclosure is not limited thereto. In some alternative embodiments, more layers of re-routed conductive layers and more layers of dielectric layers may be formed depending on the circuit design. When more rewiring conductive layers and more dielectric layers are adapted, these rewiring conductive layers and these dielectric layers are alternately stacked, and the rewiring conductive layers are interconnected with each other by the rewiring via holes. In some embodiments, the rewiring structure 100 is referred to as a backside rewiring structure.

A plurality of conductive structures 200 are formed on the re-wiring structure 100. In some embodiments, InFO package 10 (shown in fig. 1Y) has an active area AR and a border area BR surrounding active area AR. The conductive structure 200 may be formed, for example, in the active region AR. In some embodiments, the conductive structure 200 is a conductive post formed by a photolithography process, a plating process, a photoresist strip process, and/or any other suitable process. In some embodiments, the conductive structure 200 is formed over the rerouting via 106 and in contact with the rerouting via 106 to form an electrical connection with the rerouting structure 100. In some embodiments, the conductive structure 200 can be formed at the same stage and at the same time as the rerouting via 106. For example, a plurality of contact openings corresponding to designated locations of the rerouting vias 106 may be formed in the dielectric layer 104. Subsequently, a seed material layer (not shown) extending into the contact opening may be formed over the dielectric layer. A mask pattern (not shown) may then be formed on the seed material layer. The mask pattern has openings to expose the seed material layer positioned inside the contact openings. In some embodiments, the openings of the mask pattern also expose portions of the seed material layer near the contact openings. Thereafter, a conductive material is filled into the openings and the contact openings by electroplating or deposition. Next, the mask pattern and the seed layer under the mask pattern are removed to obtain the conductive structure 200 and the rerouting via 106. However, the present disclosure is not limited thereto. Other suitable methods may be used to form the conductive structure 102 and the rerouting vias 106. For example, the conductive structure 200 and the rerouting via 106 may be formed separately. In some alternative embodiments, a plurality of conductive pads (not shown) may be formed over the rerouting vias 106. The conductive structure 200 is formed over the conductive pad such that the conductive structure 200 is electrically connected to the rewiring structure 100 through the conductive pad. In some embodiments, the formation of the conductive structure 200 may be omitted.

In some embodiments, the material of the conductive structure 200 includes copper, a copper alloy, or the like. It should be noted that the number of conductive structures 200 depicted in fig. 1A is merely used as an exemplary illustration, and the number of conductive structures 200 may be varied based on requirements.

Referring to fig. 1B, a plurality of dies 300 are formed on the rerouting structure 100. In some embodiments, the die 300 is placed between the plurality of conductive structures 200 in the active area AR. For example, a plurality of conductive structures 200 may be arranged to surround the die 300. In some embodiments, the die 300 is picked and placed onto the rerouting structure 100. For example, each of the plurality of dies 300 includes a semiconductor substrate 310, a plurality of conductive pads 320, a passivation layer 330, a post-passivation layer 340, a plurality of vias 350, and a protective layer 360. In some embodiments, the conductive pad 320 is disposed above the semiconductor substrate 310. A passivation layer 330 is formed over the semiconductor substrate 310 and has a contact opening that partially exposes the conductive pad 320. The semiconductor substrate 310 may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. The conductive pads 320 may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer 330 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. In addition, a post-passivation layer 340 is formed over the passivation layer 330. The post-passivation layer 340 covers the passivation layer 330 and has a plurality of contact openings. The conductive pad 320 is partially exposed from the contact opening of the rear passivation layer 340. The back passivation layer 340 may be a Polyimide (PI) layer, a PBO layer, or a dielectric layer formed of other suitable polymers. In some embodiments, the post-passivation layer 340 may be optional. In addition, a via 350 is formed on the conductive pad 320. In some embodiments, the vias 350 are made of a conductive material and are plated onto the conductive pads 320. A protective layer 360 is formed on the post passivation layer 340 to cover the via hole 350.

As shown in fig. 1B, each die 300 has a back surface 300a and a front surface 300B opposite the back surface 300 a. In some embodiments, the back surface 300a of the die 300 is attached (or adhered) to the rerouting structure 100 by an adhesion layer AD. In some embodiments, the adhesion layer AD may comprise a Die Attach Film (DAF). On the other hand, the front surface 300b of the die 300 faces upward. As shown in fig. 1B, the top surface (front surface 300B) of the die 300 is substantially coplanar with the top surface of the conductive structure 200. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of the die 300 may be positioned at a level below or above the top surface of the conductive structure 200. Although two dies 300 are depicted in fig. 1B, the configuration is used as an exemplary illustration only. In some alternative embodiments, a greater or lesser number of dies may be formed based on requirements.

Referring to fig. 1C, an encapsulation material 400a is formed over the rerouting structure 100 to encapsulate the conductive structure 200 and the die 300. For example, the conductive structure 200 and the protective layer 360 of the die 300 are encapsulated by the encapsulation material 400 a. In other words, the conductive structure 200 and the protective layer 360 of the die 300 are not exposed and are well protected by the encapsulation material 400 a. In some embodiments, the encapsulation material 400a is a molding compound, a molding underfill, a resin (epoxy), or the like. The encapsulation material 400a may be formed by a molding process. For example, the encapsulation material 400a may be formed by a compression molding process.

Referring to fig. 1C and 1D, the encapsulant 400a and protective layer 360 of the die 300 are ground until the top surface of the via 350 is exposed. After the encapsulant material 400a is ground, an encapsulant 400 is formed over the redistribution structure 100 to encapsulate the conductive structure 200 and the die 300. In some embodiments, the encapsulant material 400a is ground by a mechanical grinding process and/or a Chemical Mechanical Polishing (CMP) process. In some embodiments, during the polishing process of the encapsulant material 400a, the protection layer 360 is polished to expose the via 350. In some embodiments, portions of vias 350 and portions of conductive structures 200 are also slightly ground. After grinding, each die 300 has an active surface 300c and a back surface 300a opposite the active surface 300 c. The exposed portions of the vias 350 are located on the active surface 300c of the die 300. It is noted that the top surface of the conductive structure 200, the top surface of the protection layer 360, and the top surface of the via 350 are substantially coplanar with the top surface of the encapsulant 400.

Referring to fig. 1E, a seed material layer 510 is formed on the encapsulant 400, the conductive structure 200, and the die 300. In some embodiments, a seed material layer 510 is blanket formed over encapsulant 400, conductive structure 200, and die 300. For example, the seed material layer 510 is formed to be positioned in both the active area AR and the boundary area BR. In some embodiments, the seed material layer 510 is formed in direct contact with the conductive structure 200, the encapsulant 400, the protection layer 360, and the via 350. For example, the seed layer material 510 may be formed by a sputtering process, a Physical Vapor Deposition (PVD) process, or the like. In some embodiments, the seed layer material 510 may comprise, for example, copper, a titanium copper alloy, or other suitable material selection.

Referring to fig. 1F, a photoresist layer PR1 is formed over the seed material layer 510. In some embodiments, the photoresist layer PR1 may be formed by spin coating or other suitable formation methods. As shown in fig. 1F, the photoresist layer PR1 has a plurality of openings OP1 exposing at least a portion of the seed material layer 510. In some embodiments, the two adjacent openings OP1 in the boundary region BR may be closer than the two adjacent openings OP1 in the active region AR. For example, a distance between two adjacent openings OP1 in the boundary region BR may be smaller than a distance between two adjacent openings OP1 in the active region AR. In some embodiments, some of openings OP1 in active area AR correspond to the locations of conductive structures 200 and vias 350. For example, a vertical projection of some of the openings OP1 along a direction perpendicular to the active surface 300c of the die 300 overlaps with the conductive structure 200. Similarly, vertical projections of some of the openings OP1 in a direction perpendicular to the active surface 300c of the die 300 overlap with the vias 350 of the die 300.

Referring to fig. 1F and 1G, a plurality of conductive patterns 520a, 520b are formed on the seed material layer 510. In some embodiments, a conductive material (not shown) is filled into the opening OP1 of the photoresist layer PR 1. Thereafter, the photoresist layer PR1 is removed to obtain the conductive patterns 520a, 520 b. After the photoresist layer PR1 is removed, portions of the seed material layer 510 not covered by the conductive patterns 520a and 520b are exposed. In some embodiments, the conductive material may be formed by a plating process. For example, the plating process is electroplating, electroless plating, immersion plating (immersion plating), or the like. In some embodiments, the conductive material comprises, for example, copper, a copper alloy, or the like. The photoresist pattern layer PR1 may be removed/stripped by, for example, etching, ashing (ashing), or other suitable removal process. In some embodiments, the conductive pattern 520a is positioned in the active area AR and the conductive pattern 520b is positioned in the border area BR.

Referring to fig. 1G and 1H, the seed material layer 510 not covered by the conductive patterns 520a, 520b is removed to form seed layers 510a, 510 b. That is, the seed material layer 510 under the photoresist layer PR1 is removed. The exposed portions of the seed material layer 510 may be removed by an etching process. In some embodiments, the material of the conductive patterns 520a, 520b may be different from the material of the seed material layer 510, so that the exposed portion of the seed material layer 510 may be removed by selective etching. The seed layer 510a is positioned in the active region AR and the seed layer 510b is positioned in the boundary region BR. In some embodiments, a portion of the seed layer 510a is sandwiched between the conductive structure 200 and the conductive pattern 520a, and another portion of the seed layer 510a is sandwiched between the via 350 and the conductive pattern 520 a. On the other hand, the seed layer 510b is sandwiched between the encapsulant 400 and the conductive pattern 520 b. In some embodiments, the conductive pattern 520a is stacked on the seed layer 510a, and the conductive pattern 520b is stacked on the seed layer 510 b. In some embodiments, the seed layer 510b may include a plurality of seed layer patterns. As shown in fig. 1H, the seed layer pattern is aligned with the conductive pattern 520b in a direction perpendicular to the active surface 300c of the die 300. For example, sidewalls of each seed layer pattern are aligned with sidewalls of each conductive pattern 520 b.

In some embodiments, the conductive pattern 520a and the seed layer 510a positioned in the active area AR are collectively referred to as a first via CV 1. On the other hand, the conductive pattern 520b and the seed layer 510b positioned in the border region BR may be collectively referred to as a first alignment mark AM 1. In some embodiments, the first via CV1 is positioned in the active area AR, and the first alignment mark AM1 is positioned in the border area BR. First via CV1 may electrically connect conductive structure 200 and/or via 350 of die 300 with other subsequently formed elements. On the other hand, the first alignment mark AM1 may ensure that other subsequently formed elements are precisely formed at the designated positions. In some embodiments, the first alignment mark AM1 is electrically floating (floating). For example, the first alignment mark AM1 is electrically insulated from the first via CV1, the conductive structure 200, the via 350 of the die 300, and the rerouting structure 100. In some embodiments, first alignment mark AM1 is in physical contact with enclosure 400. For example, the seed layer 510b of the first alignment mark AM1 may be in direct contact with the encapsulant 400.

As mentioned above, the distance between two adjacent openings OP1 of the photoresist layer PR1 in the boundary region BR may be smaller than the distance between two adjacent openings OP1 of the photoresist layer PR1 in the active region AR. Since the first via CV1 and the first alignment mark AM1 are formed by filling a conductive material into the opening OP1, the first via CV1 and the first alignment mark AM1 may have a shape corresponding to the contour of the opening OP 1. For example, each of the plurality of first via holes CV1 may be a block pattern in a top view, and each of the plurality of first alignment marks AM1 may be a grid pattern in a top view. That is, one first conductive via CV1 includes one conductive pattern 520a, and one first alignment mark AM1 includes a plurality of conductive patterns 520 b. The configuration of the first alignment mark AM1 will be discussed below in conjunction with fig. 2A through 2D.

Fig. 2A to 2D are schematic top views illustrating various configurations of the first alignment mark AM1 in fig. 1H. Referring to fig. 2A, the first alignment mark AM1 forms a square grid pattern and includes a plurality of groups G1, G2, G3, and G4, wherein each group G1, G2, G3, and G4 includes a plurality of grid patterns arranged in parallel to and spaced apart from each other, respectively. The extending direction of the grid patterns in group G1 is substantially parallel to the extending direction of the grid patterns in group G3, the extending direction of the grid patterns in group G2 is substantially parallel to the extending direction of the grid patterns in group G4, and the extending direction of the grid patterns in group G1 and group G3 is not parallel to the extending direction of the grid patterns in group G2 and group G4. For example, the extending direction of the grid patterns in group G1 and group G3 is substantially perpendicular to the extending direction of the grid patterns in group G2 and group G4. In some embodiments, the grid patterns in group G1 and group G3 may extend horizontally, while the grid patterns in group G2 and group G4 may extend vertically. Further, the grid pattern in group G1 is separate from the grid patterns in group G2, group G3, and group G4; the grid pattern in group G2 is separate from the grid patterns in group G1, group G3, and group G4; the grid pattern in group G3 is separate from the grid patterns in group G1, group G2, and group G4; and the grid pattern in group G4 is separate from the grid patterns in group G1, group G2, and group G3. In some embodiments, the group G1, the group G2, the group G3 and the group G4 of the first alignment mark AM1 are distributed in a square area. In some embodiments, the first alignment mark AM1 has a size of 1 micron to 20 microns. Herein, the size refers to a length or a width of the first alignment mark AM1 when viewed from a top view. By adapting the first alignment mark AM1 having a grid pattern, the signal noise on the first alignment mark AM1 can be sufficiently reduced. That is, the machine can precisely detect the first alignment mark AM1, thereby improving overlay accuracy and reducing alignment failure rate. For example, overlay accuracy within 3 microns (e.g., within 0.5 microns) may be achieved by adaptation of the grid pattern.

In some alternative embodiments, the first alignment mark AM1 may have other shapes as viewed from the top. For example, referring to fig. 2B, the first alignment mark AM1 forms a square grid pattern and includes a plurality of groups G1, G2, G3, and G4, wherein each group G1, G2, G3, and G4 includes a plurality of grid patterns arranged in parallel to and spaced apart from each other, respectively. The extending direction of the grid patterns in group G1 is substantially parallel to the extending direction of the grid patterns in group G3, the extending direction of the grid patterns in group G2 is substantially parallel to the extending direction of the grid patterns in group G4, and the extending direction of the grid patterns in group G1 and group G3 is not parallel to the extending direction of the grid patterns in group G2 and group G4. For example, the extending direction of the grid patterns in group G1 and group G3 is substantially perpendicular to the extending direction of the grid patterns in group G2 and group G4. In some embodiments, the grid patterns in group G1, group G2, group G3, and group G4 may extend diagonally. In some embodiments, a machine may detect the profile of the conductive pattern 520b for alignment. Fig. 2A and 2B illustrate that all the conductive patterns 520B in the first alignment mark AM1 are spaced apart from each other, but the present disclosure is not limited thereto. The first alignment mark AM1 shown in fig. 2A and the first alignment mark AM1 shown in fig. 2B are alignment marks having different orientations (orientations) and are considered as alignment marks having different patterns.

Referring to fig. 2C, the first alignment mark AM1 includes a plurality of groups G1, G2, G3, and G4, wherein each group G1, G2, G3, and G4 includes a plurality of grid patterns arranged in parallel to and spaced apart from each other, respectively. The extending direction of the grid patterns in group G1 is substantially parallel to the extending direction of the grid patterns in group G3, the extending direction of the grid patterns in group G2 is substantially parallel to the extending direction of the grid patterns in group G4, and the extending direction of the grid patterns in group G1 and group G3 is not parallel to the extending direction of the grid patterns in group G2 and group G4. For example, the extending direction of the grid patterns in group G1 and group G3 is substantially perpendicular to the extending direction of the grid patterns in group G2 and group G4. In some embodiments, the grid patterns in group G1 and group G3 may extend horizontally, while the grid patterns in group G2 and group G4 may extend vertically. As shown in fig. 2C, the grid patterns in group G1, group G2, group G3, and group G4 may extend radially (radially). Further, the grid pattern in group G1 is separate from the grid patterns in group G2, group G3, and group G4; the grid pattern in group G2 is separate from the grid patterns in group G1, group G3, and group G4; the grid pattern in group G3 is separate from the grid patterns in group G1, group G2, and group G4; and the grid pattern in group G4 is separate from the grid patterns in group G1, group G2, and group G3. In some embodiments, the group G1, the group G2, the group G3 and the group G4 of the first alignment mark AM1 are distributed in a square area. In some embodiments, the first alignment mark AM1 has a size of 1 micron to 20 microns. Herein, the size refers to a length or a width of the first alignment mark AM1 when viewed from a top view. By adapting the first alignment mark AM1 having a grid pattern, the signal noise on the first alignment mark AM1 can be sufficiently reduced. That is, the machine can precisely detect the first alignment mark AM1, thereby improving the overlay accuracy and reducing the alignment failure rate. For example, overlay accuracy within 3 microns (e.g., within 0.5 microns) may be achieved by adaptation of the grid pattern.

In some alternative embodiments, the first alignment mark AM1 may have other shapes as viewed from the top. For example, referring to fig. 2D, the first alignment mark AM1 includes a plurality of groups G1, G2, G3, and G4, wherein each group G1, G2, G3, and G4 respectively includes a plurality of grid patterns arranged in parallel to and spaced apart from each other. The extending direction of the grid patterns in group G1 is substantially parallel to the extending direction of the grid patterns in group G3, the extending direction of the grid patterns in group G2 is substantially parallel to the extending direction of the grid patterns in group G4, and the extending direction of the grid patterns in group G1 and group G3 is not parallel to the extending direction of the grid patterns in group G2 and group G4. For example, the extending direction of the grid patterns in group G1 and group G3 is substantially perpendicular to the extending direction of the grid patterns in group G2 and group G4. In some embodiments, the grid patterns in group G1, group G2, group G3, and group G4 may extend diagonally. In some embodiments, the machine can detect the conductive pattern 520b for alignment. Fig. 2C and 2D illustrate that all the conductive patterns 520b in the first alignment mark AM1 are spaced apart from each other, but the present disclosure is not limited thereto. The first alignment mark AM1 shown in fig. 2C and the first alignment mark AM1 shown in fig. 2D are alignment marks having different orientations and are regarded as alignment marks having different patterns.

It should be noted that the configuration of the first alignment mark AM1 illustrated in fig. 2A to 2D is merely used as an exemplary illustration, and the present disclosure is not limited thereto. The first alignment mark AM1 may have other shapes or take other forms as long as the first alignment mark AM1 includes a multidirectional grid pattern.

Referring to fig. 1I, a dielectric material layer 530a is formed over encapsulant 400, conductive structure 200, and die 300 to encapsulate first via CV1 and first alignment mark AM 1. In other words, the first via hole CV1 and the first alignment mark AM1 are not exposed and are well protected by the dielectric material layer 530 a. In some embodiments, the material of the dielectric material layer 530a includes polyimide, epoxy, acrylic, phenolic, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric material layer 530a may be formed by a suitable fabrication technique such as spin-on coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like.

Referring to FIGS. 1I and 1J, a portion of dielectric material layer 530a is removed to form a top surface T exposing first via CV1_CV1And a top surface T of the first alignment mark AM1_AM1Of the first dielectric layer 530. For example, the dielectric material layer 530a can be polished until the top surface T of the first via CV1 is exposed_CV1And a top surface T of the first alignment mark AM1_AM1. In some embodiments, the dielectric material layer 530a is polished by a Chemical Mechanical Polishing (CMP) process.

In some embodiments, the dielectric material layer 530a is polished to make the top surface T of the first dielectric layer 530₅₃₀And the top surface T of the first via CV1_CV1And a top surface T of the first alignment mark AM1_AM1Are substantially coplanar. For example, the top surface T of the first via CV1_CV1Substantially coplanar with the top surface of the conductive pattern 520b of the first alignment mark AM 1. In some embodiments, the first dielectric layer 530, the first via CV1 and the first alignment mark AM1 may have substantially the same thickness of 2 microns to 10 microns. In some alternative embodiments, the top surface T of the first dielectric layer 530 is at₅₃₀And the top surface T of the first via CV1_CV1And on the top surface T of the first dielectric layer 530₅₃₀With the top surface T of the first alignment mark AM1_AM1A height difference can be seen between. The height difference will be described below in conjunction with fig. 3A and 3B.

Fig. 3A-3B are schematic cross-sectional views illustrating intermediate stages of a fabrication process of an InFO package 10 according to some alternative embodiments of the present disclosure. Referring to FIG. 3A, in some embodiments, the via CV1 and the first alignment mark AM1 are overpolished during a grinding process such that the top surface T of the first dielectric layer 530₅₃₀Positioned higher than top surface T of first via CV1_CV1And a top surface T of the first alignment mark AM1_AM1At the level of (a). For example, the thickness of the first via CV1The degree may be less than the thickness of the first dielectric layer 530. Similarly, the thickness of the first alignment mark AM1 may also be less than the thickness of the first dielectric layer 530. Referring to FIG. 3B, in some alternative embodiments, the first dielectric layer 530 may be over-ground during the grinding process such that the top surface T of the first via CV1_CV1And a top surface T of the first alignment mark AM1_AM1Positioned above the top surface T of the first dielectric layer 530₅₃₀At the level of (a). For example, the thickness of the first via CV1 and the thickness of the first alignment mark AM1 are both greater than the thickness of the first dielectric layer 530. In some embodiments, the first via CV1 and the first alignment mark AM1 are from the top surface T of the first dielectric layer 530₅₃₀And (4) protruding.

In some embodiments where the first dielectric layer 530 is formed by a grinding-back method, the height difference is negligible. For example, the top surface T of the first dielectric layer 530₅₃₀And the top surface T of the first via CV1_CV1The distance (height difference) between them is less than 0.6 micrometer. Similarly, the top surface T of the first dielectric layer 530₅₃₀With the top surface T of the first alignment mark AM1_AM1The distance (height difference) between them can also be less than 0.6 micrometer.

Referring back to fig. 1J, in some embodiments, the top surface T of the first conductive via CV1 is exposed_CV1And a top surface T of the first alignment mark AM1_AM1These surfaces are then further ground to form a smooth profile. For example, the top surface T of the first via CV1_CV1Is in a range between 0.04 micrometers and 0.09 micrometers. Similarly, the top surface T of the first alignment mark AM1_AM1Also in the range between 0.04 and 0.09 micrometers. Since the first alignment mark AM1 has a smooth top surface T_AM1And the top surface T of the first alignment mark AM1_AM1And the top surface T of the first dielectric layer 530 adjacent thereto₅₃₀Substantially coplanar, better resolution of the first alignment mark AM1 may be obtained by the machine during the exposure/alignment process. Thus, subsequently formed components can be accurately formed at designated locations, thereby enhancing the InFO package10 reliability.

In some embodiments, the first via CV1, the first alignment mark AM1, and the first dielectric layer 530 may constitute a first sub-layer of the re-routing structure 500 (shown in fig. 1U) to be formed later. As shown in fig. 1J, a first sublayer is formed over encapsulant 400, die 300, and conductive structure 200. The first dielectric layer 530 is wound around the first via CV1 and the first alignment mark AM 1. That is, the first via CV1 and the first alignment mark AM1 are embedded in the first dielectric layer 530. Referring to fig. 1J, since the first dielectric layer 530 is wound around the sidewalls of the first alignment mark AM1, the first dielectric layer 530 can protect the sidewalls of the first alignment mark AM1 from being damaged by a subsequent process (i.e., an etching process or the like). That is, in some embodiments, each of the plurality of first alignment marks AM1 has substantially straight sidewalls. For example, on the sidewall of the first alignment mark AM1 and along the top surface T parallel to the first alignment mark AM1_AM1May be in a range between 85 deg. and 90 deg..

Referring to fig. 1K, a seed material layer 512 is formed over the first sublayer. The seed material layer 512 may be similar to the seed material layer 510, and thus a detailed description thereof is omitted herein. In some embodiments, the seed material layer 512 is blanket formed in direct contact with the first dielectric layer 530, the first via CV1, and the first alignment mark AM 1. The seed material layer 512 is formed to be positioned in both the active area AR and the boundary area BR.

Referring to fig. 1L, a photoresist layer PR2 is formed over the seed material layer 512. In some embodiments, the photoresist layer PR2 may be formed by spin coating or other suitable formation methods. As shown in fig. 1L, the photoresist layer PR2 has a plurality of openings OP2 exposing at least a portion of the seed material layer 512. In some embodiments, the accuracy of the position of the opening OP2 may be ensured by using the first alignment mark AM1 as an alignment tool. In some embodiments, the opening OP2 in the active area AR corresponds to the position of the first via CV 1. For example, a vertical projection of the opening OP2 in the active area AR in a direction perpendicular to the active surface 300c of the die 300 overlaps the first via CV 1. On the other hand, the opening OP2 in the border region BR does not correspond to the position of the first alignment mark AM 1. For example, a vertical projection of the opening OP2 in the border region BR in a direction perpendicular to the active surface 300c of the die 300 does not overlap the first alignment mark AM 1.

Referring to fig. 1L and 1M, a plurality of conductive patterns 540a, 540b are formed on the seed material layer 512. In some embodiments, a conductive material (not shown) is filled into the opening OP2 of the photoresist layer PR 2. Thereafter, the photoresist layer PR2 is removed to obtain the conductive patterns 540a, 540 b. After removing the photoresist layer PR2, the portions of the seed material layer 512 not covered by the conductive patterns 540a and 540b are exposed. In some embodiments, the conductive material may be formed by a plating process. For example, the plating process is electroplating, electroless plating, immersion plating, or the like. In some embodiments, the conductive material comprises, for example, copper, a copper alloy, or the like. The photoresist pattern layer PR2 may be removed/stripped by, for example, etching, ashing, or other suitable removal process. In some embodiments, conductive pattern 540a is positioned in active area AR and conductive pattern 540b is positioned in border area BR.

Referring to fig. 1N, a photoresist layer PR3 is formed over the seed material layer 512 and the conductive patterns 540a, 540 b. In some embodiments, the photoresist layer PR3 may be formed by spin coating or other suitable formation methods. As shown in fig. 1N, the photoresist layer PR3 has a plurality of openings OP3 exposing at least a portion of the conductive patterns 540a, 540 b. In some embodiments, the accuracy of the position of the opening OP3 may be ensured by using the first alignment mark AM1 as an alignment tool. In some embodiments, the two adjacent openings OP3 in the boundary region BR may be closer than the two adjacent openings OP3 in the active region AR. For example, the distance between two adjacent openings OP3 above conductive pattern 540b may be smaller than the distance between two adjacent openings OP3 above conductive pattern 540 a. In some embodiments, the plurality of openings OP3 in the border region BR expose the same conductive pattern 540b, while each of the plurality of openings OP3 in the active region AR exposes a different conductive pattern 540 a.

Referring to fig. 1N and 1O, a plurality of conductive patterns 522a and a plurality of conductive patterns 522b are formed on the conductive patterns 540a and 540b, respectively. In some embodiments, a conductive material (not shown) is filled into the opening OP3 of the photoresist layer PR 3. Thereafter, the photoresist layer PR3 is removed to obtain the conductive patterns 522a and 522 b. In some embodiments, the conductive material may be formed by a plating process. For example, the plating process is electroplating, electroless plating, immersion plating, or the like. In some embodiments, the conductive material comprises, for example, copper, a copper alloy, or the like. In some embodiments, the plating process of conductive patterns 522a, 522b shares the same seed layer as the plating process of conductive patterns 540a, 540 b. That is, seed material layer 512 may serve as a seed layer for electroplating conductive pattern 540a, conductive pattern 540b and both conductive pattern 522a, 522 b. Thus, the conductive patterns 522a and 522b do not contain a seed layer. That is, there is no seed layer between conductive pattern 522a and conductive pattern 540a and no seed layer between conductive pattern 522b and conductive pattern 540 b. The photoresist pattern layer PR3 may be removed/stripped by, for example, etching, ashing, or other suitable removal process. In some embodiments, the conductive pattern 522a is positioned in the active area AR and the conductive pattern 522b is positioned in the border area BR.

Referring to fig. 1O and 1P, the seed material layer 512 not covered by the conductive patterns 540a, 540b is removed to form seed layers 512a, 512 b. The seed layer 512a is positioned in the active region AR and the seed layer 512b is positioned in the boundary region BR. In some embodiments, the seed layer 512a is sandwiched between the first via CV1 and the conductive pattern 540 a. On the other hand, the seed layer 512b is sandwiched between the first dielectric layer 530 and the conductive pattern 540 b. Further, conductive pattern 540a is sandwiched between conductive pattern 522a and seed layer 512a, and conductive pattern 540b is sandwiched between conductive pattern 522b and seed layer 512 b. The exposed portions of the seed material layer 512 may be removed by an etching process. In some embodiments, the material of the conductive patterns 522a, 522b, 540a, 540b may be different from the material of the seed material layer 512, so that the exposed portions of the seed material layer 512 may be removed by selective etching.

In some embodiments, the conductive pattern 540a and the seed layer 512a positioned in the active area AR are collectively referred to as a first wiring pattern RP 1. In some embodiments, the conductive pattern 522a positioned in the active area AR may be referred to as a second via CV 2. On the other hand, the conductive pattern 522b, the conductive pattern 540b, and the seed layer 512b positioned in the boundary region BR may be collectively referred to as a second alignment mark AM 2. The second alignment mark AM2 is different from the first alignment mark AM1 in size, pattern, and/or orientation from a top view. In an embodiment where the second alignment mark AM2 differs from the first alignment mark AM1 in size, pattern, and/or orientation from a top view, the first alignment mark AM1 and the second alignment mark AM2 positioned at different levels can be easily and effectively identified by the image capturing apparatus to facilitate alignment of the subsequently performed processes. In some embodiments, the first wiring pattern RP1 and the second via CV2 are positioned in the active area AR. On the other hand, the second alignment mark AM2 is positioned in the border region BR. The first wiring pattern RP1 may include wiring traces for signal transmission along a horizontal plane. The second via CV2 may electrically connect the first wiring pattern RP1 with other elements to be formed later. On the other hand, the second alignment mark AM2 can ensure that other subsequently formed elements are precisely formed at the designated positions. In some embodiments, the second alignment mark AM2 is electrically floating. For example, the second alignment mark AM2 is electrically insulated from the first wiring pattern RP1, the second via CV2, the first alignment mark AM1, the first via CV1, the conductive structure 200, the through hole 350 of the die 300, and the rewiring structure 100. In some embodiments, the second alignment mark AM2 is in physical contact with the first dielectric layer 530. For example, the seed layer 512b of the second alignment mark AM2 may be directly in contact with the first dielectric layer 530. In some embodiments, the second alignment mark AM2 does not overlap with the first alignment mark AM 1. For example, a vertical projection of the second alignment mark AM2 in a direction perpendicular to the active surface 300c of the die 300 does not overlap the first alignment mark AM 1. Unlike the first alignment mark AM1 having a double-layered structure, the second alignment mark AM2 may have a triple-layered structure. In some embodiments, each first alignment mark AM1 includes a plurality of conductive patterns 520b stacked on top of a plurality of seed layer patterns (seed layer 510 b). As shown in fig. 1P, the conductive patterns 520b are separated from each other, and the seed layer patterns are also separated from each other. On the other hand, each first alignment mark AM2 includes a plurality of conductive patterns 522b stacked on top of the continuous conductive pattern 540b and the continuous seed layer 512 b.

As mentioned above, the distance between two adjacent openings OP3 above conductive pattern 540b may be less than the distance between two adjacent openings OP3 above conductive pattern 540 a. Since the second via CV2 and the second alignment mark AM2 are formed by filling a conductive material into the opening OP3, the second via CV2 and the second alignment mark AM2 may have a shape corresponding to the contour of the opening OP 3. For example, each of the plurality of second via holes CV2 may be a block pattern in a top view, and each of the plurality of second alignment marks AM2 may be a grid pattern in a top view. That is, one second conductive via CV2 includes one conductive pattern 522a, and one second alignment mark AM2 includes a plurality of conductive patterns 522 b. It should be noted that the second alignment mark AM2 may also be adapted to the configuration shown in fig. 2A to 2D.

Referring to fig. 1Q, a dielectric material layer 532a is formed over the first dielectric layer 530, the first via CV1 and the first alignment mark AM1 to encapsulate the first wiring pattern RP1, the second via CV2 and the second alignment mark AM 2. In other words, the first wiring pattern RP1, the second via hole CV2, and the second alignment mark AM2 are not exposed and are well protected by the dielectric material layer 532 a. The dielectric material layer 532a may be similar to the dielectric material layer 530a, and thus a detailed description thereof is omitted herein.

Referring to FIGS. 1Q and 1R, a portion of dielectric material layer 532a is removed to form a top surface T exposing second via CV2_CV2And the top surface T of the second alignment mark AM2_AM2And a second dielectric layer 530. For example, the dielectric material layer 532a can be polished until the top surface T of the second via CV2 is exposed_CV2And the top surface T of the second alignment mark AM2_AM2. In some embodiments, the dielectric material layer 532a is polished by a Chemical Mechanical Polishing (CMP) process. As shown in fig. 1R, a second dielectric layer 532 is stacked over the first dielectric layer 530.

In some embodiments, the layer of dielectric material 532a is polished such that the top surface T of the first dielectric layer 532₅₃₂And top surface T of second via CV2_CV2And the top surface T of the second alignment mark AM2_AM2Are substantially coplanar. For example, the top surface T of the second via CV2_CV2Substantially coplanar with the top surface of the conductive pattern 522 b. In some alternative embodiments, the top surface T of the second dielectric layer 532 is due to the polishing selectivity between different materials₅₃₂And top surface T of second via CV2_CV2And on the top surface T of the second dielectric layer 532₅₃₂Top surface T of AM2 aligned with the second alignment mark_AM2A height difference can be seen between. In some embodiments where the second dielectric layer 532 is formed by a backgrinding process, the height difference is negligible. For example, the top surface T of the second dielectric layer 532₅₃₂And top surface T of second via CV2_CV2The distance (height difference) between them is less than 0.6 micrometer. Similarly, the top surface T of the second dielectric layer 532₅₃₂Top surface T of AM2 aligned with the second alignment mark_AM2The distance (height difference) between them can also be less than 0.6 micrometer.

In some embodiments, the second via CV2 is exposed at the top surface T_CV2And the top surface T of the second alignment mark AM2_AM2These surfaces are then further ground to form a smooth profile. For example, the top surface T of the second via CV2_CV2Is in a range between 0.04 micrometers and 0.09 micrometers. Similarly, the top surface T of the second alignment mark AM2_AM2Also in the range between 0.04 and 0.09 micrometers. Since the second alignment mark AM2 has a smooth top surface T_AM2And the top surface T of the second alignment mark AM2_AM2And the top surface T of the first dielectric layer 532 adjacent thereto₅₃₂Substantially coplanar, better resolution of the second alignment mark AM2 may be obtained by the machine during the exposure/alignment process. Thus, the subsequently formed element can be accurately formed at a given positionIn position to improve the reliability of the InFO package 10.

In some embodiments, the first wiring pattern RP1, the second via CV2, the second alignment mark AM2, and the second dielectric layer 532 may constitute a second sub-layer (shown in fig. 1T) of the re-wiring structure 500 to be formed later. In some embodiments, the second sub-layer is formed over the first sub-layer. The second dielectric layer 532 is wound around the first wiring pattern RP1, the second via hole CV2, and the second alignment mark AM 2. That is, the first wiring pattern RP1, the second via CV2, and the second alignment mark AM2 are embedded in the second dielectric layer 532. In some embodiments, the second via CV2 is disposed on the first wiring pattern RP 1. In some embodiments, the first wiring pattern RP1 is sandwiched between the first and second via CV1 and CV 2. In some embodiments, the second via CV2 is free of seed layers.

Referring to fig. 1R, since the second dielectric layer 532 is wound around the sidewalls of the second alignment mark AM2, the second dielectric layer 532 can protect the sidewalls of the second alignment mark AM2 from being damaged by a subsequent process (i.e., an etching process or the like). That is, in some embodiments, each of the plurality of second alignment marks AM2 has substantially straight sidewalls. For example, on the sidewall of the second alignment mark AM2 and along the top surface T parallel to the second alignment mark AM2_AM2The included angle formed between the extended virtual lines may be in a range between 85 ° and 90 °.

Referring to fig. 1S, a plurality of second wiring patterns RP2 and a plurality of third alignment marks AM3 are formed on the second via hole CV2 and the second dielectric layer 532, respectively. Each of the plurality of second wiring patterns RP2 includes a seed layer 514a and a conductive pattern 542 a. Each of the plurality of third alignment marks AM3 includes a seed layer 542b and a conductive pattern 514 b. In some embodiments, the second wiring pattern RP2 may be formed by a method similar to that of the first wiring pattern RP1 or the first via CV1, and the third alignment mark AM3 may be formed by a method similar to that of the first alignment mark AM 1. Therefore, detailed description of the second wiring patterns RP2 and the third alignment marks AM3 is omitted herein. In some embodiments, the accuracy of the positions of the second wiring pattern RP2 and the third alignment mark AM3 may be ensured by using the second alignment mark AM2 as an alignment tool. The third alignment mark AM3 is different from the first alignment mark AM1 and the second alignment mark AM2 in size, pattern and/or orientation from a top view. In embodiments where the first alignment mark AM1, the second alignment mark AM2, and the third alignment mark AM3 are different from each other in size, pattern, and/or orientation from a top view, the first alignment mark AM1, the second alignment mark AM2, and the third alignment mark AM3 positioned at different levels may be easily and efficiently recognized by the image capturing apparatus to facilitate alignment of a subsequently performed process. In some embodiments, the second wiring patterns RP2 are positioned in the active area AR, and the third alignment marks AM3 are positioned in the boundary area BR. The second wiring pattern RP2 may include wiring traces for signal transmission along the horizontal plane. On the other hand, the third alignment mark AM3 can ensure that other subsequently formed elements are formed accurately at the specified positions. Similar to the first and second alignment marks AM1 and AM2, the third alignment mark AM3 may be electrically floating and may include a grid pattern. For example, each of the plurality of third alignment marks AM3 is composed of a plurality of conductive patterns 542 b. It should be noted that the third alignment mark AM3 may also be adapted to the configuration shown in fig. 2A to 2D.

Referring to fig. 1T, a third dielectric layer 534 is formed over the second sublayer. For example, a third dielectric layer 534 is stacked on the second dielectric layer 532. The third dielectric layer 534 has a plurality of openings OP 4. In some embodiments, the accuracy of the position of the opening OP4 may be ensured by using the third alignment mark AM3 as an alignment tool. In some embodiments, the opening OP4 partially exposes the conductive patterns 542a of the second wiring pattern RP2 and completely exposes the third alignment mark AM 3. However, the present disclosure is not limited thereto. In some alternative embodiments, the third dielectric layer 534 may completely cover the third alignment mark AM 3. The third dielectric layer 534 may be formed by the following steps. First, a dielectric material layer (not shown) is formed over the second dielectric layer 532 to cover the second wiring patterns RP2 and the third alignment marks AM 3. In some embodiments, the material of the dielectric material layer comprises polyimide, epoxy, acrylic, phenolic, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric material layer may be formed by a suitable fabrication technique such as spin-on coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. Thereafter, the dielectric material layer may be patterned by a photolithography process and an etching process to form the third dielectric layer 534 having the opening OP 4.

Referring to fig. 1U, a plurality of third wiring patterns RP3 are formed on the second wiring patterns RP2 to obtain a rewiring structure 500. In some embodiments, the third wiring pattern RP3 includes a seed layer 516a and a plurality of conductive patterns 544 a. In some embodiments, the third wiring pattern RP3 is positioned in the active area AR. The third wiring pattern RP3 may be formed by the following steps. First, a first mask pattern (not shown) may be used to cover/protect the third alignment mark AM 3. Subsequently, a seed material layer (not shown) extending into the opening OP4 may be formed over the third dielectric layer 534. For example, the seed layer material may be formed by a sputtering process, a Physical Vapor Deposition (PVD) process, or the like. In some embodiments, the seed layer material may comprise, for example, copper, a titanium copper alloy, or other suitable material selection. A second mask pattern (not shown) may then be formed on the seed material layer. The second mask pattern has an opening to expose the seed material layer located inside the opening OP 4. In some embodiments, the openings of the second mask pattern also expose portions of the seed material layer in the vicinity of the opening OP 4. Thereafter, a conductive material (not shown) is filled into the openings of the second mask and the opening OP4 of the third dielectric layer 534 by plating or deposition. Next, the first and second mask patterns and the seed material layer under the second mask pattern are removed to obtain the third wiring pattern RP 3.

In some embodiments, the second wiring pattern RP2, the third wiring pattern RP3, the third alignment mark AM3, and the third dielectric layer 534 may be considered as a third sub-layer of the rewiring structure 500. In some embodiments, the third wiring pattern RP3 may include a plurality of pads. In some embodiments, the pads contain multiple under-ball metal (UBM) patterns for ball mounting.

As shown in fig. 1U, the rewiring structure 500 includes a first dielectric layer 530, a second dielectric layer 532, a third dielectric layer 534, a first via CV1, a second via CV2, a first wiring pattern RP1, a second wiring pattern RP2, a third wiring pattern RP3, a first alignment mark AM1, a second alignment mark AM2, and a third alignment mark AM 3. The first via CV1 and the first alignment mark AM1 are embedded in the first dielectric layer 530. The second via CV2, the first wiring pattern RP1, and the second alignment mark AM2 are embedded in the second dielectric layer 532. The second wiring patterns RP2 are embedded in the third dielectric layer 534, and the third wiring patterns RP3 are partially embedded in the third dielectric layer 534. A portion of the plurality of first via holes CV1 is in physical contact with the conductive structure 200 and the first wiring pattern RP 1. Another portion of the plurality of first via holes CV1 is in physical contact with the through-holes 350 of the die 300 and the first wiring pattern RP 1. That is, the first via CV1 electrically connects the conductive structure 200, the die 300, and the first wiring pattern RP 1. The second via CV2 is in physical contact with the first wiring pattern RP1 and the second wiring pattern RP 2. That is, the second via electrically interconnects the first wiring pattern RP1 and the second wiring pattern RP 2. The second wiring pattern RP2 is in physical contact with the second via CV2 and the third wiring pattern RP 3. That is, the second wiring pattern RP2 is electrically connected to the second via CV2 and the third wiring pattern RP 3.

In some embodiments, the rerouting structure 500 is referred to as a front-side rerouting structure. It should be noted that although the rerouting structure 500 is shown in fig. 1U as having three sub-layers, the present disclosure is not limited thereto. In some alternative embodiments, the rerouting structure 500 may be constructed of more or fewer layers of sub-layers depending on the circuit design.

Referring to fig. 1V, after the rewiring structure 500 is formed, a plurality of conductive terminals 600 are placed on the third wiring pattern RP3(UBM pattern) of the rewiring structure 500. In some embodiments, the conductive terminal 600 is electrically connected to the redistribution structure 500. In some embodiments, the conductive terminals 600 comprise solder balls. In some embodiments, the conductive terminal 600 may be placed on the UBM pattern by a ball placement process.

Referring to fig. 1V and 1W, after the conductive terminal 600 is formed on the rewiring structure 500, the rewiring structure 100 is separated from the peeling layer DB and the carrier 100. In some embodiments, the release layer (e.g., LTHC release layer) may be irradiated by a UV laser such that the release carrier C and release layer DB may be peeled. However, the lift-off process (de-bonding process) is not limited thereto. Other suitable methods of de-loading may be used in some alternative embodiments. After removing the peeling layer DB and the carrier C, the structure is inverted and placed on the carrier tape TP.

Referring to fig. 1X, a plurality of openings OP5 are formed in the dielectric layer 104 to partially expose the redistribution conductive layer 102. In some embodiments, when there are multiple rerouted conductive layers 102, opening OP5 exposes the lowermost rerouted conductive layer 102. In some embodiments, opening OP5 is formed by a laser drilling process, a mechanical drilling process, a photolithography process, or other suitable process. Thereafter, a plurality of conductive terminals 700 are formed over the redistribution structure 100. In some embodiments, at least a portion of the conductive terminal 700 extends into the opening OP5 to contact the rerouting conductive layer 102 to form an electrical connection with the rerouting structure 100. In some embodiments, the conductive terminals 700 are attached to the redistribution conductive layer 102 by a flux (not shown). In some embodiments, the conductive terminals 700 are solder balls, for example. In some embodiments, the conductive terminal 700 may be disposed on the redistribution conductive layer 102 by a ball placement process and/or a reflow process.

Referring to fig. 1X and 1Y, the structure shown in fig. 1X is cut or singulated. Thereafter, the cutting structure is removed from the carrier tape TP to form a plurality of InFO packages 10. In some embodiments, the cutting process or the singulation process generally includes cutting with a rotating blade or a laser beam. In other words, the cutting or singulation process is, for example, a laser cutting process, a mechanical cutting process, or other suitable process.

Fig. 4 is a schematic cross-sectional view illustrating a package on package (PoP) structure 1000. Referring to fig. 4, in some embodiments, the InFO package 10 obtained in fig. 1Y may have a double-sided end design to accommodate other electronic components. For example, a second package 20' may be stacked on the InFO package 10. The second package 20' is, for example, an IC package. Second package 20' is electrically connected to InFO package 10 through conductive terminals 700. In some embodiments, after second package 20 'is stacked on InFO package 10, a reflow process is further performed to enhance adhesion between InFO package 10 and second package 20'. It should be noted that fig. 4 is used only as an exemplary illustration, and the present disclosure is not limited thereto. In some alternative embodiments, other electronic devices, such as an integrated fan out (InFO) package, memory device, Ball Grid Array (BGA) or wafer, may be stacked over the InFO package 10 instead of the second package 20'.

Fig. 5 is a cross-sectional view showing an InFO package 20 according to some alternative embodiments of the present disclosure. Referring to fig. 5, InFO package 20 is similar to InFO package 10 shown in fig. 1Y, and thus a detailed description thereof is omitted herein. However, during the manufacturing process of InFO package 20, alignment marks are formed within the dicing lanes. Thus, after the singulation process, the alignment marks will be cut out of the InFO package 20.

Fig. 6A-6I are schematic cross-sectional views illustrating intermediate stages of a fabrication process of an InFO package 30 according to some alternative embodiments of the present disclosure. In some embodiments, InFO package 30 may be fabricated by performing a process similar to the steps shown in fig. 1A-1Y, except that the steps of forming rerouting structure 500 are modified. That is, the steps shown in fig. 1F to 1U may be replaced with the steps shown in fig. 6A to 6H.

Referring to fig. 6A, the steps shown in fig. 1A through 1E may be performed. Thereafter, a photoresist layer PR1' is formed over the seed material layer 510. In some embodiments, the photoresist layer PR1 may be formed by spin coating or other suitable formation methods. As shown in fig. 6A, the photoresist layer PR1 'has a plurality of openings OP1' exposing at least a portion of the seed material layer 510. In some embodiments, the opening OP1' is positioned in the boundary region BR. On the other hand, the active region AR does not contain the opening OP 1'.

Referring to fig. 6A and 6B, a plurality of conductive patterns 520B are formed on the seed material layer 510. In some embodiments, a conductive material (not shown) is filled into the opening OP1 'of the photoresist layer PR 1'. Thereafter, the photoresist layer PR1 is removed to obtain the conductive pattern 520b positioned in the boundary region BR. After the photoresist layer PR1' is removed, a portion of the seed material layer 510 not covered by the conductive pattern 520b is exposed. In some embodiments, the conductive material may be formed by a plating process. For example, the plating process is electroplating, electroless plating, immersion plating, or the like. In some embodiments, the conductive material comprises, for example, copper, a copper alloy, or the like. The photoresist pattern layer PR1' may be removed/stripped by, for example, etching, ashing, or other suitable removal process.

Referring to fig. 6B and 6C, the seed material layer 510 not covered by the conductive pattern 520B is removed to form a seed layer 510B. That is, the seed material layer 510 under the photoresist layer PR1' is removed. The exposed portions of the seed material layer 510 may be removed by an etching process. In some embodiments, the material of the conductive pattern 520b may be different from the material of the seed material layer 510, and thus the exposed portion of the seed material layer 510 may be removed by selective etching. In some embodiments, the seed layer 510b may include a plurality of seed layer patterns. As shown in fig. 6C, the seed layer pattern is aligned with the conductive pattern 520b in a direction perpendicular to the active surface 300C of the die 300. For example, sidewalls of each seed layer pattern are aligned with sidewalls of each conductive pattern 520 b.

In some embodiments, the conductive pattern 520b and the seed layer 510b positioned in the border region BR may be collectively referred to as a first alignment mark AM 1. The first alignment mark AM1 may ensure that other subsequently formed elements are precisely formed at the designated positions. In some embodiments, the first alignment mark AM1 is electrically floating. For example, the first alignment mark AM1 is electrically insulated from the conductive structure 200, the via 350 of the die 300, and the rerouting structure 100. In some embodiments, first alignment mark AM1 is in physical contact with enclosure 400. For example, the seed layer 510b of the first alignment mark AM1 may be in direct contact with the encapsulant 400. In some embodiments, each of the plurality of first alignment marks AM1 may be a grid pattern in a top view. That is, one first alignment mark AM1 includes a plurality of conductive patterns 520 b.

Referring to fig. 6D, a dielectric material layer 530a is formed over encapsulant 400, conductive structure 200, and die 300 to encapsulate first alignment mark AM 1. In other words, the first alignment mark AM1 is not exposed and is well protected by the dielectric material layer 530 a. In some embodiments, the material of the dielectric material layer 530a includes polyimide, epoxy, acrylic, phenolic, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric material layer 530a may be formed by a suitable fabrication technique such as spin-on coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like.

Referring to fig. 6D and 6E, a portion of the dielectric material layer 530a is removed to form a top surface T exposing the first alignment mark AM1_AM1Of the first dielectric layer 530. For example, the dielectric material layer 530a may be polished until the top surface T of the first alignment mark AM1 is exposed_AM1. In some embodiments, the dielectric material layer 530a is polished by a Chemical Mechanical Polishing (CMP) process.

In some embodiments, the dielectric material layer 530a is polished to make the top surface T of the first dielectric layer 530₅₃₀With the top surface T of the first alignment mark AM1_AM1Are substantially coplanar. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface T of the first dielectric layer 530₅₃₀Can be positioned on the top surface T different from the first alignment mark AM1_AM1At the level of (a). Nevertheless, the height difference is negligible. In some embodiments, the top surface T exposing the first alignment mark AM1_AM1These surfaces are then further ground to form a smooth profile. Since the first alignment mark AM1 has a smooth top surface T_AM1And the top surface T of the first alignment mark AM1_AM1And the top surface T of the first dielectric layer 530 adjacent thereto₅₃₀Substantially coplanar, better resolution of the first alignment mark AM1 may be obtained by the machine during the exposure/alignment process. Thus, the subsequently formed components can be accurately formed at the designated positions, thereby improving the reliability of the InFO package 30.

Referring to fig. 6F, the first dielectric layer 530 is patterned to form a plurality of openings OP2' in the active area AR. In some embodiments, opening OP2' exposes conductive structure 200 and via 350 of die 300 underlying first dielectric layer 530. In other words, the position of opening OP2' corresponds to the positions of conductive structure 200 and via 350. In some embodiments, the boundary region BR is free of the opening OP 2'. In some embodiments, the accuracy of the position of the opening OP2' may be ensured by using the first alignment mark AM1 as an alignment tool. The first dielectric layer 530 may be patterned through a photolithography process and an etching process.

Referring to fig. 6G, a plurality of first wiring patterns RP1' are formed over the first dielectric layer 530. In some embodiments, the first wiring pattern RP1 'extends into the opening OP2' to be in direct contact with the conductive structure 200 and the via 350 of the die 300. In some embodiments, each first wiring pattern RP1' includes a seed layer 510c and a conductive pattern 520 c. In some embodiments, the first wiring pattern RP1' may be formed in the following manner. First, a seed material layer (not shown) may be formed over the first dielectric layer 530. The seed material layer is conformally formed such that the seed material layer extends into the opening OP2 'of the first dielectric layer 530 to cover the bottom surface and sidewalls of the opening OP 2'. For example, the seed layer material may be formed by a sputtering process, a Physical Vapor Deposition (PVD) process, or the like. In some embodiments, the seed layer material may comprise, for example, copper, a titanium copper alloy, or other suitable material selection.

Thereafter, a photoresist pattern layer (not shown) is formed over the seed material layer. In some embodiments, the photoresist pattern layer exposes the seed material layer positioned in opening OP2 'and exposes at least a portion of the seed material layer positioned on first dielectric layer 530 and surrounding opening OP 2'. Subsequently, a conductive material (not shown) is deposited on the exposed seed material layer using the photoresist pattern layer as a mask to form a conductive pattern 520 c. In some embodiments, the conductive material may be formed by a plating process. For example, the plating process is electroplating, electroless plating, immersion plating, or the like. In some embodiments, the conductive material comprises, for example, copper, a copper alloy, or the like. After the conductive pattern 520c is formed, the photoresist pattern layer is removed to expose portions of the seed material layer not covered by the conductive pattern 520 c. Portions of the seed material layer not covered by the conductive patterns 520c are then removed to obtain the seed layers 510c of the first wiring patterns RP 1'. As shown in fig. 6A to 6G, the first alignment mark AM1 is formed before the first wiring pattern RP1' is formed.

Referring to fig. 6H, a process similar to the steps illustrated in fig. 1L to 1R (except that the first wiring pattern RP1 and the second via CV2 are not formed) and fig. 6A to 6G may be repeated to obtain the second wiring pattern RP2', the second alignment mark AM2, and the second dielectric layer 532. Each of the second wiring patterns RP2 'also includes a seed layer 514c and a conductive pattern 542c, similarly to the first wiring patterns RP 1'. In some embodiments, a process similar to the steps illustrated in fig. 1S to 1U (except that the second wiring pattern RP2 is not formed) may be used to form the third wiring pattern RP3, the third alignment mark AM3, and the third dielectric layer 534. In some embodiments, each third wiring pattern RP3 includes a seed layer 516a and a conductive pattern 544 a. In some embodiments, the first wiring pattern RP1', the second wiring pattern RP2, and the third wiring pattern RP3 are electrically connected to each other. In some embodiments, the first wiring pattern RP1', the second wiring pattern RP2', and the third wiring pattern RP3 are also electrically connected to the conductive structure 200 and the vias 350 of the die 300. In some embodiments, the second wiring patterns RP2' are in direct contact with the first wiring patterns RP1', and the third wiring patterns RP3 are in direct contact with the second wiring patterns RP2 '. As shown in fig. 6H, a part of the first wiring patterns RP1 'is embedded in the first dielectric layer 530, and another part of the first wiring patterns RP1' is embedded in the second dielectric layer 532. Similarly, a part of the second wiring patterns RP2 'is embedded in the second dielectric layer 532, and another part of the second wiring patterns RP2' is embedded in the third dielectric layer 543.

Referring to fig. 6I, a process similar to the steps depicted in fig. 1V-1Y may be performed to obtain an InFO package 30.

Fig. 7A-7D are schematic cross-sectional views illustrating intermediate stages of a fabrication process of an InFO package according to other embodiments of the present disclosure. After the steps shown in fig. 1A to 1D are performed, the processes shown in fig. 7A to 7D may be performed.

Referring to fig. 7A, the first dielectric layer 530 is patterned to form a plurality of openings OP2' in the active area AR. In some embodiments, opening OP2' exposes conductive structure 200 and via 350 of die 300 underlying first dielectric layer 530. In other words, the position of opening OP2' corresponds to the positions of conductive structure 200 and via 350. In some embodiments, the boundary region BR is free of the opening OP 2'. The first dielectric layer 530 may be patterned through a photolithography process and an etching process.

Referring to fig. 7B, a plurality of first wiring patterns RP1' and first alignment marks AM1 are formed over the first dielectric layer 530. In some embodiments, the first wiring pattern RP1 'extends into the opening OP2' to be in direct contact with the conductive structure 200 and the via 350 of the die 300. In some embodiments, each first wiring pattern RP1' includes a seed layer 510c and a conductive pattern 520 c. The first alignment mark AM1 is located on the first dielectric layer 530. In some embodiments, the first alignment mark AM1 is electrically insulated from the conductive structure 200, the first wiring pattern RP1', and the via 350 of the die 300. For example, the first alignment mark AM1 is separated from the conductive structure 200, the first wiring pattern RP1', and the via 350 of the die 300 by the first dielectric layer 530. In some embodiments, the first alignment mark AM1 may be electrically floating. In some embodiments, the first wiring pattern RP1' may be formed in the following manner. First, a seed material layer (not shown) may be formed over the first dielectric layer 530. The seed material layer is conformally formed such that the seed material layer extends into the opening OP2 'of the first dielectric layer 530 to cover the bottom surface and sidewalls of the opening OP 2'. For example, the seed layer material may be formed by a sputtering process, a Physical Vapor Deposition (PVD) process, or the like. In some embodiments, the seed layer material may comprise, for example, copper, a titanium copper alloy, or other suitable material selection.

Thereafter, a photoresist pattern layer (not shown) is formed over the seed material layer. In some embodiments, the photoresist pattern layer exposes the seed material layer positioned in opening OP2 'and exposes at least a portion of the seed material layer positioned on first dielectric layer 530 and surrounding opening OP 2'. Subsequently, a conductive material (not shown) is deposited on the exposed seed material layer using the photoresist pattern layer as a mask to form a conductive pattern 520 c. In some embodiments, the conductive material may be formed by a plating process. For example, the plating process is electroplating, electroless plating, immersion plating, or the like. In some embodiments, the conductive material comprises, for example, copper, a copper alloy, or the like. After the conductive pattern 520c is formed, the photoresist pattern layer is removed to expose a portion of the seed material layer not covered by the conductive pattern 520 c. Portions of the seed material layer not covered by the conductive patterns 520c are then removed to obtain the seed layers 510c of the first wiring patterns RP 1'. As shown in fig. 7A to 7B, the first alignment mark AM1 and the first wiring pattern RP1' are simultaneously formed.

Referring to fig. 7C, a process similar to that illustrated in fig. 7A and 7B may be repeated to obtain the second wiring pattern RP2', the second alignment mark AM2, and the second dielectric layer 532. Each of the second wiring patterns RP2 'also includes a seed layer 514c and a conductive pattern 542c, similarly to the first wiring patterns RP 1'. In some embodiments, a process similar to that illustrated in fig. 7A and 7B may be used to form the third wiring pattern RP3, the third alignment mark AM3, and the third dielectric layer 534. In some embodiments, each third wiring pattern RP3 includes a seed layer 516a and a conductive pattern 544 a. In some embodiments, the first wiring pattern RP1', the second wiring pattern RP2, and the third wiring pattern RP3 are electrically connected to each other. In some embodiments, the first wiring pattern RP1', the second wiring pattern RP2', and the third wiring pattern RP3 are also electrically connected to the conductive structure 200 and the vias 350 of the die 300. In some embodiments, the second wiring patterns RP2' are in direct contact with the first wiring patterns RP1', and the third wiring patterns RP3 are in direct contact with the second wiring patterns RP2 '. As shown in fig. 7C, a part of the first wiring patterns RP1 'is embedded in the first dielectric layer 530, and another part of the first wiring patterns RP1' is embedded in the second dielectric layer 532. Similarly, a part of the second wiring patterns RP2 'is embedded in the second dielectric layer 532, and another part of the second wiring patterns RP2' is embedded in the third dielectric layer 543.

Referring to fig. 7D, a process similar to the steps depicted in fig. 1V-1Y may be performed to obtain the InFO package shown in fig. 7D. As shown in fig. 7C and 7D, trenches extending along the scribe lines may be formed in the first and second dielectric layers 530 and 532.

According to some embodiments of the present disclosure, an integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a rerouting structure. The die and the conductive structure are encapsulated by an encapsulant. The conductive structure surrounds the die. The rewiring structure is disposed on the enclosure. The rewiring structure comprises a plurality of wiring patterns, a plurality of via holes and a plurality of alignment marks. A wiring pattern is connected to the via hole. At least one of the alignment marks is in physical contact with the encapsulation.

According to some embodiments of the present disclosure, an integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a rerouting structure. The die and the conductive structure are encapsulated by an encapsulant. The conductive structure surrounds the die. The rewiring structure is disposed on the enclosure. The rewiring structure includes a first dielectric layer, a second dielectric layer, a first alignment mark and a second alignment mark. The second dielectric layer is stacked on the first dielectric layer. The first alignment mark is embedded in the first dielectric layer and the second alignment mark is embedded in the second dielectric layer. The first alignment mark includes a first seed layer and a plurality of first conductive patterns. A first conductive pattern is stacked on the first seed layer. The second alignment mark includes a second seed layer, a second conductive pattern, and a plurality of third conductive patterns. The second conductive pattern is sandwiched between the second seed layer and the third conductive pattern.

According to some embodiments of the present disclosure, a method of manufacturing an integrated fan out (InFO) package includes at least the following steps. A vector is provided. A die and a plurality of conductive structures are formed over the carrier. A plurality of conductive structures surrounds the die. The die and the plurality of conductive structures are encapsulated by an encapsulant. A rewiring structure is formed over the enclosure. The redistribution structure includes a first alignment mark in physical contact with the enclosure.

According to some embodiments, an integrated fan-out package includes an encapsulant, a semiconductor die, and a redistribution structure. The semiconductor die is encapsulated by an encapsulant. The rewiring structure is arranged above the semiconductor die and the encapsulating body and comprises a plurality of wiring patterns, a plurality of through holes and a plurality of alignment marks, the wiring patterns are connected in the through holes, and at least one of the alignment marks comprises a plurality of groups. The first group among the plurality of groups includes a plurality of first grid patterns arranged parallel to and spaced apart from each other, the second group among the plurality of groups includes a plurality of second grid patterns arranged parallel to and spaced apart from each other, and a first extending direction of the plurality of first grid patterns is different from a second extending direction of the plurality of second grid patterns. In an embodiment, each of the plurality of alignment marks comprises a square grid pattern. In an embodiment, the plurality of alignment marks are electrically floating. In an embodiment, the first extending direction of the plurality of first grid patterns is substantially perpendicular to the second extending direction of the plurality of second grid patterns. In an embodiment, the third group among the plurality of groups includes a plurality of third grid patterns arranged parallel to and spaced apart from each other, the fourth group among the plurality of groups includes a plurality of fourth grid patterns arranged parallel to and spaced apart from each other, the plurality of third grid patterns extend in the first extending direction, and the plurality of fourth grid patterns extend in the second extending direction. In an embodiment, the plurality of first grid patterns and the plurality of second grid patterns extend horizontally, and the plurality of third grid patterns and the plurality of fourth grid patterns extend vertically. In an embodiment, the plurality of first grid patterns, the plurality of second grid patterns, the plurality of third grid patterns, and the plurality of fourth grid patterns extend diagonally.

According to some embodiments, an integrated fan-out package includes an encapsulant, a semiconductor die, and a redistribution structure. The semiconductor die is encapsulated by an encapsulant. The rewiring structure is disposed above the enclosure. The rewiring structure includes a first dielectric layer, a second dielectric layer, a first alignment mark, and a second alignment mark. The second dielectric layer is stacked on the first dielectric layer. The first alignment mark is disposed on the first dielectric layer. The second alignment mark is disposed on the second dielectric layer, and each of the first alignment mark and the second alignment mark respectively includes a plurality of groups. The first group among the plurality of groups includes a plurality of first grid patterns arranged parallel to and spaced apart from each other, the second group among the plurality of groups includes a plurality of second grid patterns arranged parallel to and spaced apart from each other, and the first alignment mark is different from the second alignment mark in size, pattern, and/or orientation. In an embodiment, a first extending direction of the plurality of first grid patterns is different from a second extending direction of the plurality of second grid patterns. In an embodiment, a first extending direction of the plurality of first grid patterns is substantially perpendicular to a second extending direction of the plurality of second grid patterns. In one embodiment, the first alignment mark and the second alignment mark are electrically floating. In an embodiment, the third group among the plurality of groups includes a plurality of third grid patterns arranged parallel to and spaced apart from each other, the fourth group among the plurality of groups includes a plurality of fourth grid patterns arranged parallel to and spaced apart from each other, the plurality of third grid patterns extend in the first extending direction, and the plurality of fourth grid patterns extend in the second extending direction. In an embodiment, the plurality of first grid patterns and the plurality of second grid patterns extend horizontally, and the plurality of third grid patterns and the plurality of fourth grid patterns extend vertically. In an embodiment, the plurality of first grid patterns, the plurality of second grid patterns, the plurality of third grid patterns, and the plurality of fourth grid patterns extend diagonally. In an embodiment, the integrated fan-out package further includes a plurality of conductive terminals over the redistribution structure, wherein the plurality of conductive terminals are electrically connected to the redistribution structure.

According to some embodiments, a method of manufacturing an integrated fan-out package comprises: forming a die and a plurality of conductive structures over a carrier, wherein the plurality of conductive structures surround the semiconductor die; encapsulating the die and the plurality of conductive structures by an encapsulant; and forming a rewiring structure over the encapsulation, wherein the rewiring structure includes a plurality of alignment marks, and at least one of the plurality of alignment marks includes a plurality of groups, wherein a first group among the plurality of groups includes a plurality of first grid patterns arranged in parallel to each other and spaced apart from each other, a second group among the plurality of groups includes a plurality of second grid patterns arranged in parallel to each other and spaced apart from each other, and a first extending direction of the plurality of first grid patterns is different from a second extending direction of the plurality of second grid patterns. In an embodiment, the redistribution structure includes a first alignment mark in physical contact with the encapsulation, and the step of forming the redistribution structure includes: forming a first sub-layer over the encapsulant, the die, and the plurality of conductive structures, including: forming a first seed material layer over the encapsulant, the die, and the plurality of conductive structures; forming a first photoresist layer over the first seed material layer, wherein the first photoresist layer includes a plurality of first openings that expose at least a portion of the first seed material layer; filling a first conductive material into the plurality of first openings of the first photoresist layer to form a plurality of first conductive patterns; removing the first photoresist layer and portions of the first seed material layer under the first photoresist layer to form a plurality of first via holes and first alignment marks; forming a first dielectric material layer over the encapsulation body, the die and the conductive structures to encapsulate the first vias and the first alignment marks; and removing a portion of the first dielectric material layer to form a first dielectric layer, the first dielectric layer exposing top surfaces of the plurality of first via holes and top surfaces of the first alignment marks. In an embodiment, a top surface of the first dielectric layer is substantially coplanar with top surfaces of the plurality of first vias and the first alignment mark. In an embodiment, the step of forming the redistribution structure further comprises: forming a second sub-layer over the first sub-layer, comprising: forming a second seed material layer over the first sublayer; forming a second photoresist layer over the second layer of seed material, wherein the second photoresist layer includes a plurality of second openings that expose at least a portion of the second layer of seed material; filling a second conductive material into the plurality of second openings of the second photoresist layer to form a plurality of second conductive patterns; removing the second photoresist layer; forming a third photoresist layer over the second layer of seed material and the plurality of second conductive patterns, wherein the third photoresist layer includes a plurality of third openings exposing at least a portion of the plurality of second conductive patterns; filling a third conductive material into the plurality of third openings of the third photoresist layer to form a plurality of third conductive patterns; removing the third photoresist layer and portions of the second seed material layer exposed by the plurality of second conductive patterns to form a plurality of wiring patterns, a plurality of second via holes disposed on the plurality of wiring patterns, and a second alignment mark; forming a second dielectric material layer over the first sub-layer to encapsulate the plurality of wiring patterns, the plurality of second via holes, and the second alignment marks; and removing a portion of the second dielectric material layer to form a second dielectric layer, the second dielectric layer exposing top surfaces of the plurality of second via holes and top surfaces of the second alignment marks. In an embodiment, a top surface of the second dielectric layer is substantially coplanar with top surfaces of the plurality of second vias and the second alignment mark.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.