阅读说明：本技术 半导体芯片以及包括该半导体芯片的半导体封装件 (Semiconductor chip and semiconductor package including the same ) 是由 郑恩荣 李周益 韩正勋 于 2020-08-26 设计创作，主要内容包括：公开的实施例包括一种半导体芯片和一种包括该半导体芯片的半导体封装件。所述半导体芯片包括半导体基底和保护绝缘层,半导体基底具有顶表面,顶部连接垫设置在顶表面中,保护绝缘层中包括开口,保护绝缘层在半导体基底上不覆盖顶部连接垫的至少一部分。保护绝缘层可以包括：底部保护绝缘层；覆盖绝缘层,包括覆盖底部保护绝缘层的侧表面的至少一部分的侧覆盖部分和与侧覆盖部分分开设置以覆盖底部保护绝缘层的顶表面的至少一部分的顶覆盖部分。保护绝缘层还可以包括位于顶覆盖部分上的顶部保护绝缘层。(The disclosed embodiments include a semiconductor chip and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a top surface in which a top connection pad is disposed, and a protective insulating layer including an opening, the protective insulating layer not covering at least a portion of the top connection pad on the semiconductor substrate. The protective insulating layer may include: a bottom protective insulating layer; and a cover insulating layer including a side cover portion covering at least a portion of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a portion of a top surface of the bottom protective insulating layer. The protective insulating layer may further include a top protective insulating layer on the top cover portion.)

1. A semiconductor chip, the semiconductor chip comprising:

a semiconductor substrate including a top surface in which a top connection pad is disposed; and

a protective insulating layer including an opening, the protective insulating layer not covering at least a portion of the top connection pad on the semiconductor substrate,

wherein the protective insulating layer includes: a bottom protective insulating layer; a cover insulating layer including a side cover portion covering at least a portion of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer on the top cover portion.

2. The semiconductor chip according to claim 1, wherein the bottom protective insulating layer further comprises a protrusion and a step,

wherein the step defines an upper portion of the protrusion adjacent the opening.

3. The semiconductor chip of claim 2, wherein the top cover portion covers a top surface of the protrusion, the top protective insulating layer being disposed on the protrusion.

4. The semiconductor chip according to claim 2, wherein the side cover portion covers at least a part of a side surface of the bottom protective insulating layer, the part of the side surface being lower in elevation than a bottom surface of the step.

5. The semiconductor chip of any one of claims 1 to 4, further comprising a barrier layer,

wherein at least a portion of the barrier layer is disposed between the top connection pad and the bottom protective insulating layer,

wherein the opening passes through the bottom protective insulating layer and the barrier layer.

6. The semiconductor chip of claim 5, wherein the side cover portion is configured to cover all side surfaces of the barrier layer and at least a portion of a side surface of the bottom protective insulating layer between the step and the top surface of the top connection pad.

7. The semiconductor chip of claim 5, wherein the side cover portion comprises:

a first side portion covering a portion of a side surface of the barrier layer; and

a second side portion covering a part of a side surface of the bottom protective insulating layer,

wherein the first side portion and the second side portion are spaced apart from each other.

8. The semiconductor chip of claim 7, wherein the first side is separate from the top connection pad.

9. The semiconductor chip of claim 5, further comprising a sub-step defined in the opening by a side surface of the bottom protective insulating layer and a top surface of the barrier layer.

10. The semiconductor chip of claim 5, wherein the side cover portions are separate from the top connection pads.

11. The semiconductor chip according to claim 5, wherein the side cover portion covers at least a part of a side surface of the bottom protective insulating layer and does not cover a side surface of the barrier layer.

12. A semiconductor package, comprising:

a first semiconductor chip comprising: a first top connection pad and a first bottom connection pad disposed on the top surface and the bottom surface of the first semiconductor substrate, respectively; a first protective insulating layer including a first opening, the first protective insulating layer not covering at least a portion of the first top connection pad on the first semiconductor substrate; and a first through electrode electrically connecting the first top connection pad to the first bottom connection pad; and

at least one second semiconductor chip comprising: a second top connection pad disposed on a top surface of the second semiconductor substrate; a second protective insulating layer including a second opening therein, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate; and internal connection terminals disposed on the second top connection pads and electrically connecting the first semiconductor chip to the at least one second semiconductor chip through the first bottom connection pads of the first semiconductor chip, the internal connection terminals contacting side surfaces of the second protective insulating layer in the second openings,

wherein the at least one second semiconductor chip is stacked on the bottom surface of the first semiconductor chip,

wherein the first protective insulating layer includes: a bottom protective insulating layer; a cover insulating layer including a side cover portion covering at least a portion of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer on the top cover portion.

13. The semiconductor package according to claim 12, wherein the bottom protective insulating layer and the second protective insulating layer comprise the same material.

14. The semiconductor package according to claim 12, wherein the bottom protective insulating layer further comprises a protrusion and a step,

wherein the step defines an upper portion of the protrusion adjacent the first opening,

wherein no step is provided in the second protective insulating layer.

15. The semiconductor package according to claim 14,

a top protective insulating layer is disposed on the protrusion, and

the top cover portion is disposed between the protrusion and the top protective insulating layer.

16. The semiconductor package according to claim 14, wherein an uppermost end of the side cover portion is disposed at the same level as or lower than a bottom surface of the step.

17. The semiconductor package of any of claims 12-16, further comprising a barrier layer, at least a portion of the barrier layer disposed between the first top connection pad and the bottom protective insulating layer,

wherein the first opening penetrates the bottom protective insulating layer and the barrier layer,

wherein the side covering portion covers all side surfaces of the barrier layer and a portion of a side surface of the bottom protective insulating layer between the step and a top surface of the first top connection pad.

18. A semiconductor package, comprising:

a first semiconductor chip comprising: a first top connection pad and a first bottom connection pad disposed on the top surface and the bottom surface of the first semiconductor substrate, respectively; a first barrier layer covering a portion of a top surface of the first top connection pad; a first protective insulating layer including a first opening, the first protective insulating layer not covering at least a portion of the first top connection pad on the first semiconductor substrate; and a first through electrode electrically connecting the first top connection pad to the first bottom connection pad; and

a plurality of second semiconductor chips comprising: a second top connection pad and a second bottom connection pad disposed on the top surface and the bottom surface of the second semiconductor substrate, respectively; a second protective insulating layer including a second opening therein, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate, the plurality of second semiconductor chips being stacked on the bottom surface of the first semiconductor chip; and internal connection terminals electrically connecting the second top connection pad to the first bottom connection pad or electrically connecting the second top connection pad and the second bottom connection pad of a different second semiconductor chip among the plurality of second semiconductor chips,

wherein the first protective insulating layer includes: a bottom protective insulating layer including a protrusion and a step, wherein the step defines an upper portion of the protrusion adjacent to the opening; a cover insulating layer including a side cover portion covering at least a portion of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer on the top cover portion.

19. The semiconductor package according to claim 18,

the bottom protective insulating layer, the cover insulating layer, and the second protective insulating layer each include an inorganic material, and

the top protective insulating layer includes a polymer.

20. The semiconductor package according to claim 18 or 19,

the top protective insulating layer covers the top surfaces of the protrusions of the bottom protective insulating layer, and

the uppermost end of the side cover portion is disposed at the same level as or lower than the bottom surface of the step.

Technical Field

The disclosed inventive concept relates to a semiconductor chip and a semiconductor package including the same, and more particularly, to a semiconductor chip including a connection pad (also referred to as a "pad") and a semiconductor package including the same.

Background

In order to meet the demand for miniaturized, multi-functionalized, and high-performance electronic products, semiconductor packages are required to be thin and lightweight and to have high speed and high performance. Accordingly, demands for semiconductor chips and semiconductor packages including the semiconductor chips for realizing systems with high memory bandwidths are increasing. Since the memory bandwidth is proportional to the data transfer speed and the number of data transfer lines, the memory bandwidth can be increased by increasing the memory operating speed or the number of data transfer lines. Therefore, the number and density of connection bumps attached on connection pads of semiconductor chips are increasing.

Disclosure of Invention

The inventive concept provides a semiconductor chip including a connection pad for enhancing attachment reliability on a connection bump and a semiconductor package including the semiconductor chip.

The inventive concept provides a semiconductor chip and a semiconductor package including the same as described below.

According to an aspect of the inventive concept, there is provided a semiconductor chip including: a semiconductor substrate having a top surface with a top connection pad disposed therein; and a protective insulating layer including an opening, the protective insulating layer not covering at least a portion of the top connection pad on the semiconductor substrate. The protective insulating layer may include: a bottom protective insulating layer; and a cover insulating layer including a side cover portion covering at least a portion of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a portion of a top surface of the bottom protective insulating layer. The protective insulating layer may further include a top protective insulating layer on the top cover portion.

According to another aspect of the inventive concept, there is provided a semiconductor package including a first semiconductor chip having: a first top connection pad and a first bottom connection pad disposed on the top surface and the bottom surface of the first semiconductor substrate, respectively; the first protective insulating layer comprises a first opening, and at least one part of the first top connecting pad is not covered by the first protective insulating layer on the first semiconductor substrate. The first semiconductor chip may further include a first through electrode electrically connecting the first top connection pad to the first bottom connection pad, and the semiconductor package may further include at least one second semiconductor chip. The second semiconductor chip may include: a second top connection pad disposed on a top surface of the second semiconductor substrate; a second protective insulating layer including a second opening therein, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate; and internal connection terminals disposed on the second top connection pads and electrically connecting the first semiconductor chip to the at least one second semiconductor chip through the first bottom connection pads of the first semiconductor chip, the internal connection terminals contacting side surfaces of the second protective insulating layer in the second openings. In some embodiments, the at least one second semiconductor chip is stacked on the bottom surface of the first semiconductor chip. Further, in some embodiments, the first protective insulating layer may include: a bottom protective insulating layer; a cover insulating layer including a side cover portion covering at least a portion of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a portion of a top surface of the bottom protective insulating layer, and a top protective insulating layer on the top cover portion.

According to another aspect of the inventive concept, there is provided a semiconductor package including a first semiconductor chip having first top and bottom connection pads disposed on top and bottom surfaces of a first semiconductor substrate, respectively. The first semiconductor chip may include: a first barrier layer covering a portion of a top surface of the first top connection pad; the first protective insulating layer is provided with a first opening, and the first protective insulating layer does not cover at least one part of the first top connecting pad on the first semiconductor substrate. The first semiconductor chip may further include a first through electrode electrically connecting the first top connection pad to the first bottom connection pad, and the semiconductor package may further include a plurality of second semiconductor chips. The second semiconductor chip may include: a second top connection pad and a second bottom connection pad disposed on the top surface and the bottom surface of the second semiconductor substrate, respectively; a second protective insulating layer including a second opening therein, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate, the plurality of second semiconductor chips being stacked on the bottom surface of the first semiconductor chip. The second semiconductor chip may further include internal connection terminals electrically connecting the second top connection pad to the first bottom connection pad, or electrically connecting the second top connection pad and the second bottom connection pad of a different second semiconductor chip among the plurality of second semiconductor chips. In some embodiments, the first protective insulating layer comprises: and a bottom protective insulating layer including a protrusion and a step defining an upper portion of the protrusion adjacent to the opening. The first protective insulating layer may further include: a cover insulating layer having a side cover portion covering at least a part of a side surface of the bottom protective insulating layer and a top cover portion disposed apart from the side cover portion to cover at least a part of a top surface of the bottom protective insulating layer; and a top protective insulating layer on the top cover portion.

Drawings

Embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a cross-sectional view showing a semiconductor chip according to a disclosed embodiment, and FIG. 1B is a cross-sectional view showing a top connection pad of a semiconductor chip according to a disclosed embodiment;

fig. 2A-2D are cross-sectional views sequentially illustrating a method of fabricating a semiconductor chip including a top connection pad in accordance with a disclosed embodiment;

fig. 3 is a cross-sectional view illustrating a semiconductor package according to a disclosed embodiment;

fig. 4A to 4D are sectional views illustrating connection pads of a semiconductor package according to a disclosed embodiment;

fig. 5 is a cross-sectional view illustrating a system including a semiconductor package according to a disclosed embodiment, and fig. 6A and 6B are enlarged cross-sectional views illustrating a first top connection pad and a second top connection pad each included in the semiconductor package of the system according to a disclosed embodiment;

FIGS. 7A-7D are enlarged cross-sectional views illustrating a first top connection pad included in a semiconductor package of a system in accordance with a disclosed embodiment; and

fig. 8A-8D are enlarged cross-sectional views illustrating a second top connection pad included in a semiconductor package of a system according to a disclosed embodiment.

Detailed Description

Fig. 1A is a cross-sectional view illustrating a semiconductor chip 100 according to a disclosed embodiment, and fig. 1B is a cross-sectional view illustrating a top connection pad of the semiconductor chip 100 according to a disclosed embodiment. In detail, fig. 1B is a cross-sectional view illustrating an enlarged region B of fig. 1A.

Referring to fig. 1A and 1B, the semiconductor chip 100 may include a semiconductor substrate 110 and a top connection pad 122 disposed on an effective surface, which is a top surface of the semiconductor substrate 110.

The semiconductor substrate 110 may include a base substrate on which various conductive and insulating layers are formed and patterned. The base substrate may be cut from a portion of a wafer and may be, for example, a crystalline semiconductor material, such as silicon (Si). Alternatively, the base substrate of the semiconductor substrate 110 may be formed of another crystalline semiconductor material such as germanium (Ge), and/or may include a compound crystalline semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The semiconductor substrate 110 may include an active surface and a non-active surface opposite to the active surface, for example, a bottom surface of the semiconductor substrate 110. For example, the bulk substrate of the semiconductor substrate 110 may include one or more conductive regions (e.g., impurity doped wells) and various isolation structures such as Shallow Trench Isolation (STI) structures for separating/isolating the various conductive regions from each other.

In the specification, the top surface and the bottom surface of the semiconductor substrate may respectively denote an active surface and a non-active surface of the semiconductor substrate. That is, even when the active surface of the semiconductor substrate is disposed below the inactive surface in the final product (i.e., the active surface is oriented to face down in the real world), the active surface of the semiconductor substrate is considered to be the top surface of the semiconductor substrate, and the inactive surface of the semiconductor substrate is considered to be the bottom surface of the semiconductor substrate. Furthermore, the terms "top surface" and "bottom surface" may apply to elements disposed on an active surface and elements disposed on a non-active surface, respectively.

Semiconductor devices 112 may be formed on and within the active surface of semiconductor substrate 110, with semiconductor devices 112 formed as integrated circuits and as a combination of multiple individual electronic components (such as transistors, logic gates, etc.). The semiconductor device 112 may be referred to as a first semiconductor device. The plurality of individual electronic components may include various microelectronic devices (e.g., metal-oxide-semiconductor field effect transistors such as complementary metal-insulator-semiconductor (CMOS) transistors, image sensors such as system Large Scale Integration (LSI) and CMOS Imaging Sensors (CIS), micro-electro-mechanical systems (MEMS), active devices, and passive devices). A plurality of individual electronic components may be electrically connected to and/or formed with portions of the conductive regions of the semiconductor substrate 110. The semiconductor device 112 may be formed as a combination of a plurality of individual electronic components connected together with conductive wiring (which may include conductive plug (s)). Furthermore, each electronic component may be electrically isolated from other respective electronic components adjacent thereto by an insulating layer.

The semiconductor chip 100 may be, for example, a Dynamic Random Access Memory (DRAM) chip, a Static Random Access Memory (SRAM) chip, a flash memory chip, an Electrically Erasable and Programmable Read Only Memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a Magnetic Random Access Memory (MRAM) chip, or a Resistive Random Access Memory (RRAM) chip. The semiconductor chip 100 may be, for example, a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, or an Application Processor (AP) chip.

In some embodiments, the semiconductor chip 100 may be a High Bandwidth Memory (HBM) DRAM semiconductor chip. In some embodiments, the semiconductor chip 100 may be a buffer chip including a serial-to-parallel conversion circuit. In some embodiments, the semiconductor chip 100 may be a buffer chip for controlling the HBMDRAM semiconductor chip. When the semiconductor chip 100 is a buffer chip for controlling the HBM DRAM semiconductor chip, the semiconductor chip 100 may be referred to as a master chip, and the HBM DRAM semiconductor chip may be referred to as a slave chip. Alternatively, the semiconductor chip 100 may be referred to as a first semiconductor chip.

In fig. 1A and 1B, the top connection pad 122 is shown buried into the semiconductor substrate 110, but is not limited thereto. In some embodiments, the top connection pad 122 may protrude from the top surface of the semiconductor substrate 110.

In the specification, the semiconductor substrate 110 may include a base substrate formed of a crystalline semiconductor material (e.g., bulk Si, silicon-on-insulator, etc.) and various layers of conductive material and insulating material formed thereon for forming the semiconductor device 112. That is, the semiconductor substrate 110 may merely represent that its major constituent comprises a semiconductor material (such as comprising a bulk semiconductor substrate as described herein) without requiring that the semiconductor substrate 110 be formed solely of a semiconductor material.

A protective insulating layer 150 exposing the top connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150 may include a bottom protective insulating layer 152, a cap insulating layer 154, and a top protective insulating layer 156. For ease of illustration and ease of description, the cover insulating layer 154 is not shown in fig. 1A but is shown in detail in fig. 1B. For example, the bottom protective insulating layer 152 may include an inorganic material such as an oxide or a nitride. For example, the bottom protective insulating layer 152 may include at least one of silicon oxide and silicon nitride. In some embodiments, the bottom protective insulating layer 152 may include silicon nitride. For example, the capping insulating layer 154 may include silicon nitride. For example, the top protective insulating layer 156 may be and/or include a photosensitive polyimide (PSPI). The protective insulating layer 150 may be referred to as a first protective insulating layer.

The semiconductor chip 100 may include a through electrode 130 disposed on a non-active surface, the through electrode 130 electrically connecting the top connection pad 122 to the bottom connection pad 124 and passing through at least a portion of the semiconductor substrate 110 between the top surface and the bottom surface of the semiconductor substrate 110, the non-active surface may be the bottom surface of the semiconductor substrate 110. The through electrode 130 may be referred to as a first through electrode. The top connection pad 122 may be referred to as a first top connection pad. The bottom connection pad 124 may be referred to as a first bottom connection pad.

The through electrode 130 may include a conductive plug penetrating the semiconductor substrate 110 and a conductive barrier layer surrounding the conductive plug. The conductive plug may have a circular pillar shape, and the conductive barrier layer may have a cylindrical shape surrounding a sidewall of the conductive plug. The via insulating layer may be disposed between the semiconductor substrate 110 and the through electrode 130 and may surround a sidewall of the through electrode 130.

In fig. 1A, the through electrode 130 is illustrated as directly connecting the top connection pad 122 to the bottom connection pad 124, but not limited thereto, the through electrode 130 may be formed to have one of a via-first structure, a via-middle structure, and a via-last structure.

In some embodiments, the barrier layer 123 may be formed at a portion of the top connection pad 122. A barrier layer 123 may be disposed between the top connection pad 122 and the bottom protective insulating layer 152. The barrier layer 123 may include, for example, at least one material selected from among titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), but is not limited thereto. In fig. 1B, the top connection pad 122 is buried into the semiconductor substrate 110 and the barrier layer 123 protrudes from the top surface of the semiconductor substrate 110, but the exemplary embodiment is not limited thereto. In some embodiments, the top connection pad 122 and the barrier layer 123 may both be buried into the semiconductor substrate 110. In some other embodiments, the top connection pad 122 and the barrier layer 123 may protrude from the top surface of the semiconductor substrate 110. The barrier layer 123 may be referred to as a first barrier layer. In some embodiments, barrier layer 123 may be omitted.

The protective insulating layer 150 may include a bottom protective insulating layer 152, a cap insulating layer 154, and a top protective insulating layer 156. The bottom protective insulating layer 152 may include an opening OP1 exposing at least a portion of the top connection pad 122. In some embodiments, the sidewalls of the opening OP1 may extend in a vertical (perpendicular) direction with respect to the main surface of the semiconductor substrate 110. For example, the sidewall of the opening OP1 may extend in a perpendicular direction (vertically) with respect to the upper surface of the substrate 110. The bottom protective insulating layer 152 may include a step ST disposed at a portion of the bottom protective insulating layer 152 adjacent to the opening OP1 and including a relatively low top surface. A portion of the bottom protective insulating layer 152 having a level higher than that of a relatively low top surface (i.e., a bottom surface of the step ST) of the bottom protective insulating layer 152 may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152 may refer to the bottom surface of the step ST and the top surface of the protrusion PRT, respectively. That is, a step ST may be provided at an upper portion of the opening OP1 to restrict the protrusion PRT. A top protective insulating layer 156 may be disposed on the protrusion PRT. For example, in the step ST region, the bottom protective insulating layer 152 may have a top surface that is relatively lower in elevation/height than a top surface of the bottom protective insulating layer 152 in the protruding PRT region. Similarly, in the step ST region, the bottom protective insulating layer 152 may have a bottom surface relatively higher in elevation/height than a bottom surface of the bottom protective insulating layer 152 in the protruding PRT region.

In some embodiments, when the semiconductor chip 100 includes the barrier layer 123, the opening OP1 may pass through the bottom protective insulating layer 152 and the barrier layer 123 to expose a portion of the top surface of the top connection pad 122. The opening OP1 may be referred to as a first opening. At least a portion of the barrier layer 123 may be disposed between the top connection pad 122 and the bottom protective insulating layer 152.

The cover insulating layer 154 may cover a portion of the bottom protective insulating layer 152. In some embodiments, the cover insulating layer 154 may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152. The cover insulating layer 154 may include a side cover portion 154S covering a portion of a side surface of the bottom protective insulating layer 152 and a top cover portion 154T covering a portion of a top surface of the bottom protective insulating layer 152 (i.e., a top surface of the protrusion PRT).

The side cover portion 154S may cover at least a portion of the side surface of the barrier layer 123 and at least a portion of the side surface of the bottom protective insulating layer 152 in the opening OP 1. In some embodiments, the side cover portions 154S may cover a portion of the side surfaces of the barrier layer 123 and a portion of the side surfaces of the bottom protective insulating layer 152 in the opening OP1 (i.e., between the step ST and the top surface of the top connection pad 122). In some embodiments, the bottom surface of the side cover portion 154S may contact a portion of the top surface of the top connection pad 122. The uppermost end of the side cover portion 154S may be disposed at the same level (elevation/height) as the bottom surface of the step ST or may be disposed at a lower level than the bottom surface of the step ST.

The top cover portion 154T may be disposed between the bottom protective insulating layer 152 and the top protective insulating layer 156. The top cover portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152 and the bottom surface of the top protective insulating layer 156. The top cover portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152 (e.g., the top surface of the protrusion PRT of the bottom protective insulating layer 152 (i.e., a relatively high top surface)). Further, the top cover portion 154T may not cover the top surface of the bottom protective insulating layer 152 in the step ST region. The top cover portion 154T may cover the entire bottom surface of the top protective insulating layer 156. As will be described below with reference to fig. 2A to 2D, the cover insulating layer 154 may be first formed to cover all of the top surface and side surfaces of the bottom protective insulating layer 152 and the portion of the top surface of the top connection pad 122 exposed by the bottom surface of the opening OP1, and then may be formed by removing a portion of the cover insulating layer 154 covering at least a portion of the top surface of the top connection pad 122 and a portion of the cover insulating layer 154 covering a portion of the top surface of the bottom protective insulating layer 152. In the process of removing a portion of the capping insulating layer 154 that covers a portion of the top surface of the bottom protective insulating layer 152, a portion of the upper portion of the bottom protective insulating layer 152 may also be removed together, and thus, the step ST and the protrusion PRT may be formed at the bottom protective insulating layer 152. Therefore, the cover insulating layer 154 may not cover the surface of the bottom protective insulating layer 152 in the region corresponding to the step ST.

Fig. 2A to 2D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor chip including a top connection pad according to the disclosed example embodiment. In detail, fig. 2A to 2D are sectional views illustrating enlarged regions corresponding to the region B of fig. 1A.

Referring to fig. 2A, a top connection pad 122 may be formed in the top surface of the semiconductor substrate 110. The top connection pad 122 may comprise a conductive material. In some embodiments, the top connection pad 122 may comprise aluminum (Al). A barrier layer 123 may be formed on the top connection pad 122. The barrier layer 123 may include, for example, at least one material selected from among Ti, TiN, Ta, and TaN. In some embodiments, barrier layer 123 may comprise TiN. In some other embodiments, barrier layer 123 may be omitted.

The through electrode 130 may be formed in the semiconductor substrate 110, and the through electrode 130 may be electrically connected to the top connection pad 122. The through electrode 130 may contact the bottom surface of the top connection pad 122, but is not limited thereto. In some embodiments, wiring patterns and wiring vias may be disposed between the through electrode 130 and the top connection pad 122, and the wiring patterns and wiring vias may electrically connect the through electrode 130 to the top connection pad 122.

A bottom protective insulating layer 152 may be formed on the semiconductor substrate 110 and the top connection pad 122. The bottom protective insulating layer 152 may be formed by, for example, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The bottom protective insulating layer 152 may cover the semiconductor substrate 110 and the top connection pad 122. In embodiments where a barrier layer 123 is formed on the top connection pad 122, a bottom protective insulating layer 152 may cover the semiconductor substrate 110 and the barrier layer 123. For example, the bottom protective insulating layer 152 may include an inorganic material such as an oxide or a nitride. In some embodiments, the bottom protective insulating layer 152 may include silicon nitride.

Referring to fig. 2B, an opening OP1 exposing at least a portion of the top connection pad 122 may be formed by removing a portion of the bottom protective insulating layer 152 over the top connection pad 122. In the case where the barrier layer 123 is formed on the top connection pad 122, the opening OP1 may pass through the bottom protective insulating layer 152 and the barrier layer 123, and thus, a portion of the top surface of the top connection pad 122 may be exposed at the bottom surface of the opening OP 1. In some embodiments, the opening OP1 may be formed such that a sidewall of the opening OP1 extends in a vertical direction with respect to the main surface of the semiconductor substrate 110. For example, the opening OP1 may be formed by removing a portion of the bottom protective insulating layer 152 or removing a portion of each of the bottom protective insulating layer 152 and the barrier layer 123 based on a High Density Plasma (HDP) etching process.

Referring to fig. 2C, a cover insulating layer 154 may be formed on the resultant material formed with the opening OP 1. The cover insulating layer 154 may be formed to conformally cover the sidewalls and the bottom surface of the opening OP1 by a substantially certain thickness, i.e., a portion of the side surface of each of the bottom protective insulating layer 152 and the barrier layer 123, a portion of the top surface of the top connection pad 122, and the top surface of the bottom protective insulating layer 152. The capping insulating layer 154 may include the same material as that of the bottom protective insulating layer 152. For example, the capping insulating layer 154 may include silicon nitride.

Referring to fig. 2D, a top protective insulating layer 156 covering a portion of the cover insulating layer 154 may be formed. The top protective insulating layer 156 may include a polymer. For example, the top protective insulating layer 156 may include photosensitive polyimide (PSPI).

The top protective insulating layer 156 may be formed to be separated from the opening OP 1. For example, the edge of the top protective insulating layer 156 may be spaced apart from the edge of the opening OP 1. The top protective insulating layer 156 may be formed not to cover an inner portion of the opening OP1 and to cover a portion of the insulating layer 154 adjacent to the opening OP 1. The top protective insulating layer 156 may be formed such that the width of a portion of the cover insulating layer 154 where the top protective insulating layer 156 is not disposed has a value greater than that of the width of the opening OP 1.

Referring to fig. 1A, 1B, and 2D, a portion of the capping insulating layer 154 and a portion of an upper portion of the bottom protective insulating layer 152 may be removed by using the top protective insulating layer 156 as an etch mask. A portion of the capping insulating layer 154 and a portion of the upper portion of the bottom protective insulating layer 152 may be removed by an anisotropic etching process. A portion of the cover insulating layer 154 may be removed, and thus, the cover insulating layer 154 may include a side cover portion 154S and a top cover portion 154T that are separated from each other. A portion of the bottom protective insulating layer 152 may be removed, and thus, the bottom protective insulating layer 152 may include a step ST and a protrusion PRT.

A portion of the cover insulating layer 154 not covered with the top cover insulating layer 156 and a portion of the cover insulating layer 154 on the top connection pad 122 in the portion of the cover insulating layer 154 covering the top surface of the bottom cover insulating layer 152 may be removed, a portion of the cover insulating layer 154 disposed between the top cover insulating layer 156 and the bottom cover insulating layer 152 may remain as a top cover portion 154T, and a portion of the cover insulating layer 154 on the side surface of the bottom cover insulating layer 152 and the side surface of the barrier layer 123 in the opening OP1 may remain as a side cover portion 154S, the side cover portion 154S being, for example, a spacer type.

In the process of removing a portion of the cap insulating layer 154, an over etch may be performed to expose a portion of the top surface of the top connection pad 122. Accordingly, a portion of the upper portion of the bottom protective insulating layer 152 not covered by the top protective insulating layer 156 may be removed, and thus a step ST may be formed. In addition, a portion of the upper portion of the bottom protective insulating layer 152 covered by the top protective insulating layer 156 may not be removed, so that the protrusion PRT may be formed.

Referring to fig. 1A to 2D, as shown in fig. 2D, in the process of forming the top protective insulating layer 156, the top connection pad 122 may be covered by the cover insulating layer 154 and may remain unexposed.

For example, by developing the PSPI for forming the top protective insulating layer 156 in a state where the top surface of the top connection pad 122 is exposed, the top surface of the top connection pad 122 may be discolored by a developer. This discoloration can be a problem with some conventional processes.

In the semiconductor chip 100 according to the disclosed embodiment, the top protective insulating layer 156 may be formed in a state where the top connection pad 122 is covered by the cover insulating layer 154 and is not exposed, and thus, the top surface of the top connection pad 122 is not discolored. Accordingly, in the process of forming the connection terminal (140 of fig. 6A) at the top surface of the top connection pad 122, the connection terminal 140 may be precisely attached on the top surface of the top connection pad 122, and thus, the connection reliability of the connection terminal 140 with the top connection pad 122 may be enhanced.

Fig. 3 is a cross-sectional view illustrating a semiconductor package 1000 according to a disclosed embodiment.

Referring to fig. 3, the semiconductor package 1000 may include a first semiconductor chip 100 and a plurality of second semiconductor chips 200. In fig. 3, the semiconductor package 1000 is shown to include four second semiconductor chips 200, but is not limited thereto. For example, the semiconductor package 1000 may include two or more second semiconductor chips 200. In some embodiments, the semiconductor package 1000 may include a multiple of four (4 ×) second semiconductor chips 200, e.g., eight, twelve, sixteen, etc. The semiconductor package 1000 may be referred to as a sub-semiconductor package. The plurality of second semiconductor chips 200 may be sequentially stacked on the first semiconductor chip 100 in a vertical direction. Each of the first semiconductor chip 100 and the plurality of second semiconductor chips 200 may be sequentially stacked such that an effective surface thereof faces a lower portion thereof.

The first semiconductor chip 100 may include a first semiconductor substrate 110 having a first semiconductor device 112 formed on an active surface thereof, a first top connection pad 122 and a first bottom connection pad 124 respectively disposed on the active surface and a non-active surface of the first semiconductor substrate 110, a first through electrode 130 penetrating at least a portion of the first semiconductor substrate 110 to electrically connect the first top connection pad 122 to the first bottom connection pad 124, and a first protective insulating layer 150 exposing at least a portion of the first top connection pad 122 and covering the active surface of the first semiconductor substrate 110.

In some embodiments, the first semiconductor chip 100 may be an HBMDRAM semiconductor chip. In some embodiments, the first semiconductor chip 100 may be a buffer chip including a serial-to-parallel conversion circuit. In some embodiments, the first semiconductor chip 100 may be a buffer chip for controlling the HBMDRAM semiconductor chip.

The first semiconductor chip 100 illustrated in fig. 3 may be the same as the semiconductor chip 100 illustrated in fig. 1A except that an effective surface is disposed at a lower portion and a non-effective surface is disposed at an upper portion, and thus, the same or similar description as that of fig. 1A to 2D may be omitted. That is, the first semiconductor chip 100 included in the semiconductor package 1000 may be a semiconductor chip between which the upper and lower portions of the semiconductor chip 100 shown in fig. 1A are inverted.

The second semiconductor chip 200 may include a second semiconductor substrate 210 having a second semiconductor device 212 formed on an active surface thereof, a second top connection pad 222 and a second bottom connection pad 224 respectively disposed on the active surface and the inactive surface of the second semiconductor substrate 210, a second through electrode 230 penetrating at least a portion of the second semiconductor substrate 210 to electrically connect the second top connection pad 222 to the second bottom connection pad 224, and a second protective insulating layer 250 exposing at least a portion of the second top connection pad 222 and covering the active surface of the second semiconductor substrate 210. The second protective insulating layer 250 may include an inorganic material such as an oxide or a nitride. For example, the second protective insulating layer 250 may include at least one of silicon oxide and silicon nitride. In some embodiments, the second protective insulating layer 250 may include silicon nitride.

The second semiconductor substrate 210, the second top connection pad 222, the second bottom connection pad 224, and the second through electrode 230 may be the same as, substantially the same as, or similar to the first semiconductor substrate 110, the first top connection pad 122, the first bottom connection pad 124, and the first through electrode 130, respectively, and thus, repeated detailed descriptions thereof are omitted.

The second semiconductor chip 200 may be, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip. In some embodiments, the second semiconductor chip 200 may be an HBM DRAM semiconductor chip. The first semiconductor chip 100 may be referred to as a master chip, and the second semiconductor chip 200 may be referred to as a slave chip.

The internal connection terminals 240 may be attached on the second top connection pads 222 of each of the plurality of second semiconductor chips 200. The internal connection terminals 240 may electrically connect the first bottom connection pad 124 of the first semiconductor chip 100 to the second top connection pads 222 of the plurality of second semiconductor chips 200 and may electrically connect the second bottom connection pad 224 and the second top connection pad 222 of each of the plurality of second semiconductor chips 200.

The internal connection terminals 240 may include a base pillar 242 (conductive pillar) under the second top connection pad 222 and a conductive cap 246 on the base pillar 242. In some embodiments, a cover post (244 of fig. 6B) may be disposed between the base post 242 and the conductive cap 246. The internal connection terminal 240 may be referred to as a second connection terminal, and the base pillar 242, the capping pillar 244, and the conductive cap 246 may be referred to as a second conductive pillar, a second capping pillar, and a third conductive cap, respectively. The internal connection terminal 240 and the second protective insulating layer 250 will be described in detail with reference to fig. 6B. The connection terminal 140 illustrated in fig. 6A may be referred to as a first connection terminal, and the internal connection terminal 240 may be referred to as a second connection terminal.

An insulating adhesive layer 350 may be disposed between the first semiconductor chip 100 and each of the plurality of second semiconductor chips 200. For example, the insulating adhesive layer 350 may include a non-conductive film (NFC), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. The insulating adhesive layer 350 may surround the internal connection terminals 240 and may fill a region between the first semiconductor chip 100 and each of the plurality of second semiconductor chips 200.

In some embodiments, the second semiconductor chip 200 disposed at the uppermost end farthest from the first semiconductor chip 100 among the plurality of second semiconductor chips 200 may not include the second bottom connection pad 224 and the second through electrode 230. In some embodiments, the thickness of the second semiconductor chip 200 disposed at the uppermost end farthest from the first semiconductor chip 100 among the plurality of second semiconductor chips 200 may have a value smaller than that of each of the other second semiconductor chips 200.

The width and the area of the first semiconductor chip 100 may each have a corresponding value larger than the corresponding width and the corresponding area of each of the plurality of second semiconductor chips 200. The semiconductor package 1000 may further include a molding layer 300 surrounding side surfaces of the plurality of second semiconductor chips 200 and side surfaces of the insulating adhesive layer 350 on the first semiconductor chip 100. The molding layer 300 may include, for example, an Epoxy Mold Compound (EMC).

Fig. 4A to 4D are sectional views illustrating connection pads of a semiconductor package according to the disclosed embodiment. In detail, fig. 4A to 4D are sectional views illustrating an enlarged region corresponding to the region B of fig. 1A, the same reference numerals as those of fig. 1A and 1B denote the same elements, and a repetitive description thereof may be omitted.

Referring to fig. 4A, a protective insulating layer 150a exposing the connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150a may include a bottom protective insulating layer 152a, a cover insulating layer 154a, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152a may include an inorganic material such as an oxide or a nitride. For example, the bottom protective insulating layer 152a may include at least one of silicon oxide and silicon nitride. In some embodiments, the bottom protective insulating layer 152a may include silicon nitride. For example, the capping insulating layer 154a may include silicon nitride. For example, the top protective insulating layer 156 may include PSPI. The protective insulating layer 150a may be referred to as a first protective insulating layer.

In some embodiments, a barrier layer 123a may be formed on a portion of the connection pad 122. For example, the barrier layer 123a may be formed only at edge portions of the connection pads 122, thus exposing central portions of the connection pads 122. The barrier layer 123a may be disposed between the connection pad 122 and the bottom protective insulating layer 152 a. In some embodiments, barrier layer 123a may be omitted.

The protective insulating layer 150a may include a bottom protective insulating layer 152a, a cover insulating layer 154a, and a top protective insulating layer 156. The bottom protective insulating layer 152a may include an opening OP1a exposing at least a portion of the connection pad 122. The opening OP1a may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the opening OP1a to the upper portion of the opening OP1 a. For example, opening OP1a may have a relatively small width in the horizontal direction at a lowest elevation corresponding to the elevation of the upper surface of connection pad 122 and an increased and relatively larger width in the horizontal direction at various elevations above the lowest elevation. The bottom protective insulating layer 152a and the barrier layer 123a may have a combined horizontal width that decreases from the bottom surface of the opening OP1a to the upper portion of the opening OP1 a. That is, the side surface of the bottom protective insulating layer 152a adjacent to the opening OP1a and the side surface of the barrier layer 123a adjacent to the opening OP1a may be inclined away from the bottom of the opening OP1a and may extend upward.

The bottom protective insulating layer 152a may include a step STa including a relatively low top surface at a portion of the bottom protective insulating layer 152a adjacent to the opening OP1 a. A portion of the bottom protective insulating layer 152a having a level higher than that of a relatively lower top surface (i.e., a bottom surface of the step STa) of the bottom protective insulating layer 152a may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152a may refer to the bottom surface of the step STa and the top surface of the protrusion PRT, respectively.

The opening OP1a may pass through the bottom protective insulating layer 152a and the barrier layer 123a to expose a portion of the top surface of the connection pad 122. The opening OP1a may be referred to as a first opening.

The capping insulating layer 154a may cover a portion of the bottom protective insulating layer 152 a. In some embodiments, the cover insulating layer 154a may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152 a. The cover insulating layer 154a may include a side cover portion 154Sa covering a portion of the side surface of the bottom protective insulating layer 152a and a portion of the side surface of the barrier layer 123a and a top cover portion 154T covering a portion of the top surface of the bottom protective insulating layer 152a (i.e., the top surface of the protrusion PRT).

The side cover portion 154Sa may cover at least a portion of the side surface of the barrier layer 123a and at least a portion of the side surface of the bottom protective insulating layer 152a in the opening OP1 a. In some embodiments, the side cover portions 154Sa may cover all side surfaces of the barrier layer 123a and all side surfaces of the bottom protective insulating layer 152a in the opening OP1 a. In some embodiments, the side cover portion 154Sa may cover a portion of the side surface of the barrier layer 123a and a portion of the side surface of the bottom protective insulating layer 152a in the opening OP1a (i.e., between the step STa and the top surface of the top connection pad 122). In some embodiments, the bottom surface of the side cover portion 154Sa may contact a portion of the top surface of the connection pad 122. The uppermost end of the side cover portion 154Sa may be disposed at the same level (elevation/height) as the bottom surface of the step STa or may be disposed at a lower level (elevation/height) than the bottom surface of the step STa.

The top cover portion 154T may be disposed between the bottom protective insulating layer 152a and the top protective insulating layer 156. The top cover portion 154T may be disposed between a top surface of the protrusion PRT of the bottom protective insulating layer 152a and a bottom surface of the top protective insulating layer 156. The top cover portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152a (e.g., the top surface (i.e., the relatively high top surface) of the protrusion PRT of the bottom protective insulating layer 152 a). Further, the top cover portion 154T may not cover the top surface of the bottom protective insulating layer 152a in the step STa region. The top cover portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

Referring to fig. 4B, a protective insulating layer 150B exposing the connection pads 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150b may include a bottom protective insulating layer 152b, a cover insulating layer 154b, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152b may include silicon nitride. For example, the capping insulating layer 154b may include silicon nitride. The protective insulating layer 150b may be referred to as a first protective insulating layer.

The barrier layer 123b may be formed on a portion of the connection pad 122. For example, the barrier layer 123b may expose a central portion of the connection pad 122 and cover at least a portion of the remaining unexposed area of the connection pad 122. The barrier layer 123b may be disposed between the connection pad 122 and the bottom protective insulating layer 152 b.

The protective insulating layer 150b may include a bottom protective insulating layer 152b, a cover insulating layer 154b, and a top protective insulating layer 156. The bottom protective insulating layer 152b may include an opening OP1b exposing at least a portion of the connection pad 122. The opening OP1b may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the opening OP1b to the upper portion of the opening OP1 b. For example, opening OP1b may have a relatively small width in the horizontal direction at a lowest elevation corresponding to the elevation of the upper surface of connection pad 122 and an increased and relatively larger width in the horizontal direction at various elevations above the lowest elevation. The bottom protective insulating layer 152b and the barrier layer 123b may have a horizontal width that decreases in the distant direction (vertical direction) from the bottom surface of the opening OP1b to the upper portion of the opening OP1 b. That is, the side surface of the bottom protective insulating layer 152b in the opening OP1b and the side surface of the barrier layer 123b in the opening OP1b may be inclined away from the bottom of the opening OP1b and may extend upward.

The bottom protective insulating layer 152b may include a step STb including a relatively low top surface at a portion of the bottom protective insulating layer 152b adjacent to the opening OP1 b. A portion of the bottom protective insulating layer 152b having a level higher than that of a relatively lower top surface (i.e., a bottom surface of the step STb) of the bottom protective insulating layer 152b may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152b may refer to the bottom surface of the step STb and the top surface of the protrusion PRT, respectively.

The opening OP1b may pass through the bottom protective insulating layer 152b and the barrier layer 123b to expose a portion of the top surface of the connection pad 122. The opening OP1b may be referred to as a first opening.

In the process of forming the opening OP1b, a sub-step STsb may be formed between the bottom protective insulating layer 152b and the barrier layer 123b in the opening OP1b due to a difference in etching characteristics between the bottom protective insulating layer 152b and the barrier layer 123 b. The sub-step STsb may be defined by a side surface of the bottom protective insulating layer 152b and the exposed top surface of the barrier layer 123 b. The width of the portion of the opening OP1b at the level where the barrier layer 123b is disposed may have a value smaller than that of the portion of the opening OP1b at the level where the bottom protective insulating layer 152b is disposed.

The cover insulating layer 154b may cover a portion of the bottom protective insulating layer 152 b. In some embodiments, the cover insulating layer 154b may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152 b. The cover insulating layer 154b may include a side cover portion 154Sb covering a portion of the side surface of the bottom protective insulating layer 152b and a portion of the side surface of the barrier layer 123b, and a top cover portion 154T covering a portion of the top surface of the bottom protective insulating layer 152b (i.e., the top surface of the protrusion PRT).

The side cover portion 154Sb may cover each of at least a part of the side surface of the barrier layer 123b and at least a part of the side surface of the bottom protective insulating layer 152b in the opening OP1 b. In some embodiments, the side cover portions 154Sb may include a first side 154Sb1 covering a portion of the side surface of the barrier layer 123b and a second side 154Sb2 covering a portion of the side surface of the bottom protective insulating layer 152b in the opening OP1 b. First side 154Sb1 and second side 154Sb2 can be spaced apart from each other with an exposed portion of the top surface of barrier layer 123b therebetween. In some embodiments, the bottom surface of the first side 154Sb1 may contact a portion of the top surface of the connection pad 122. In some embodiments, the bottom surface of the second side 154Sb2 may contact a portion of the top surface of the barrier layer 123 b. The uppermost end of the first side portion 154Sb1 and the uppermost end of the second side portion 154Sb2 may be disposed at the same level as the bottom surface of the sub step STsb and the bottom surface of the step STb, respectively, or may be disposed at a lower level than the bottom surface of the sub step STsb and the bottom surface of the step STb, respectively.

The top cover portion 154T may be disposed between the bottom protective insulating layer 152b and the top protective insulating layer 156. The top cover portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152b and the bottom surface of the top protective insulating layer 156. The top cover portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152b (e.g., the top surface (i.e., the relatively high top surface) of the protrusion PRT of the bottom protective insulating layer 152 b). Further, the top cover portion 154T may not cover the top surface of the bottom protective insulating layer 152b in the step STb region. The top cover portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

Referring to fig. 4C, a protective insulating layer 150C exposing the connection pads 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150c may include a bottom protective insulating layer 152c, a cover insulating layer 154c, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152c may include silicon nitride. For example, the capping insulating layer 154c may include silicon nitride. The protective insulating layer 150c may be referred to as a first protective insulating layer.

The barrier layer 123c may be formed on a portion of the connection pad 122. For example, the barrier layer 123c may be formed only at edge portions of the connection pads 122, thus exposing central portions of the connection pads 122. The barrier layer 123c may be disposed between the connection pad 122 and the bottom protective insulating layer 152 c.

The protective insulating layer 150c may include a bottom protective insulating layer 152c, a cover insulating layer 154c, and a top protective insulating layer 156. The bottom protective insulating layer 152c may include an opening OP1c exposing at least a portion of the connection pad 122. The opening OP1c may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the opening OP1c to the upper portion of the opening OP1 c. The bottom protective insulating layer 152c and the barrier layer 123c may have a horizontal width that decreases in the distant direction (vertical direction) from the bottom surface of the opening OP1c to the upper portion of the opening OP1 c. That is, the side surface of the bottom protective insulating layer 152c adjacent to the opening OP1c and the side surface of the barrier layer 123c adjacent to the opening OP1c may be inclined away from the bottom of the opening OP1c and may extend upward.

The bottom protective insulating layer 152c may include a step STc, and the step STc includes a relatively low top surface at a portion of the bottom protective insulating layer 152c adjacent to the opening OP1 c. A portion of the bottom protective insulating layer 152c having a level higher than that of a relatively lower top surface of the bottom protective insulating layer 152c (i.e., a bottom surface of the step STc) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152c may refer to the bottom surface of the step STc and the top surface of the protrusion PRT, respectively.

The opening OP1c may pass through the bottom protective insulating layer 152c and the barrier layer 123c to expose a portion of the top surface of the connection pad 122. The opening OP1c may be referred to as a first opening.

In the process of forming the opening OP1c, a sub-step STsc may be formed between the bottom protective insulating layer 152c and the barrier layer 123c in the opening OP1c due to a difference in etching characteristics between the bottom protective insulating layer 152c and the barrier layer 123 c. The sub-step STsc may be defined by a side surface of the bottom protective insulating layer 152c and a top surface of the barrier layer 123 c. The width of the portion of the opening OP1c at the level where the barrier layer 123c is disposed may have a value smaller than that of the portion of the opening OP1c at the level where the bottom protective insulating layer 152c is disposed.

A side surface of the barrier layer 123c facing the barrier layer 123c in the opening OP1c may be more inclined than a side surface of the bottom protective insulating layer 152c facing the bottom protective insulating layer 152 c. That is, an acute angle between the top surface of the barrier layer 123c and the side surface of the bottom protective insulating layer 152c may be greater than an acute angle between the bottom surface of the barrier layer 123c and the side surface of the barrier layer 123 c.

The cover insulating layer 154c may cover a portion of the bottom protective insulating layer 152 c. In some embodiments, the cover insulating layer 154c may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152 c. The cover insulating layer 154c may include a side cover portion 154Sc covering a portion of the side surface of the bottom protective insulating layer 152c and a top cover portion 154T covering a portion of the top surface of the bottom protective insulating layer 152c (i.e., the top surface of the protrusion PRT).

The side cover portion 154Sc may cover at least a portion of the side surface of the bottom protective insulating layer 152c in the opening OP1 c. In some embodiments, the side cover portions 154Sc may cover at least a portion of the side surfaces of the bottom protective insulating layer 152c in the opening OP1c, but may not cover the side surfaces of the barrier layer 123 c.

In an embodiment in which an acute angle between the top surface of the barrier layer 123c and the side surface of the bottom protective insulating layer 152c is greater than an acute angle between the bottom surface of the barrier layer 123c and the side surface of the barrier layer 123c, a portion of the cover insulating layer 154c on the side surface of the bottom protective insulating layer 152c may remain as a side cover portion 154Sc, which may be a spacer type, but may not remain on the side surface of the barrier layer 123 c.

The side cover portions 154Sc may be spaced apart from the connection pads 122. In some embodiments, the bottom surface of the side cover portion 154Sc may contact a portion of the top surface of the barrier layer 123 c. The uppermost end of the side cover portion 154Sc may be disposed at the same level as the bottom surface of the step STc or may be disposed at a lower level than the bottom surface of the step STc.

The top cover portion 154T may be disposed between the bottom protective insulating layer 152c and the top protective insulating layer 156. The top cover portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152c and the bottom surface of the top protective insulating layer 156. The top cover portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152c (e.g., the top surface (i.e., the relatively high top surface) of the protrusion PRT of the bottom protective insulating layer 152 c). Further, the top cover portion 154T may not cover the top surface of the bottom protective insulating layer 152c in the region of the step STc. The top cover portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

Referring to fig. 4D, a protective insulating layer 150D exposing the connection pads 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150d may include a bottom protective insulating layer 152d, a cover insulating layer 154d, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152d may include silicon nitride. For example, the capping insulating layer 154d may include silicon nitride. The protective insulating layer 150d may be referred to as a first protective insulating layer.

The barrier layer 123d may be formed on a portion of the connection pad 122. For example, the barrier layer 123d may be formed only at edge portions of the connection pads 122, thus exposing central portions of the connection pads 122. The barrier layer 123d may be disposed between the connection pad 122 and the bottom protective insulating layer 152 d.

The protective insulating layer 150d may include a bottom protective insulating layer 152d, a cover insulating layer 154d, and a top protective insulating layer 156. The bottom protective insulating layer 152d may include OP1d exposing at least a portion of the connection pad 122. The opening OP1d may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the opening OP1d to the upper portion of the opening OP1 d. The bottom protective insulating layer 152d and the barrier layer 123d may have a horizontal width that decreases in the distant direction (vertical direction) from the bottom surface of the opening OP1d to the upper portion of the opening OP1 d. That is, the side surface of the bottom protective insulating layer 152d in the opening OP1d and the side surface of the barrier layer 123d in the opening OP1d may be inclined away from the bottom of the opening OP1d and may extend upward.

The bottom protective insulating layer 152d may include a step STd, the step STd including a relatively low top surface at a portion of the bottom protective insulating layer 152d adjacent to the opening OP1 d. A portion of the bottom protective insulating layer 152d having a level higher than that of a relatively lower top surface of the bottom protective insulating layer 152d (i.e., a bottom surface of the step STc) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152d may refer to the bottom surface of the step STd and the top surface of the protrusion PRT, respectively.

The opening OP1d may pass through the bottom protective insulating layer 152d and the barrier layer 123d to expose a portion of the top surface of the connection pad 122. The opening OP1d may be referred to as a first opening.

In the process of forming the opening OP1d, a sub-step STsd may be formed between the bottom protective insulating layer 152d and the barrier layer 123d in the opening OP1d due to a difference in etching characteristics between the bottom protective insulating layer 152d and the barrier layer 123 d. The sub-step STsd may be defined by a side surface of the bottom protective insulating layer 152d and a top surface of the barrier layer 123 d. The width of the portion of the opening OP1d at the level where the barrier layer 123d is disposed may have a value smaller than that of the portion of the opening OP1d at the level where the bottom protective insulating layer 152d is disposed.

The cover insulating layer 154d may cover a portion of the bottom protective insulating layer 152 d. In some embodiments, the cover insulating layer 154d may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152 d. The cover insulating layer 154d may include a side cover portion 154Sd covering a portion of the side surface of the bottom protective insulating layer 152d and a portion of the side surface of the barrier layer 123d, and a top cover portion 154T covering a portion of the top surface of the bottom protective insulating layer 152d (i.e., the top surface of the protrusion PRT).

The side cover portion 154Sd may cover each of at least a part of a side surface of the barrier layer 123d and at least a part of a side surface of the bottom protective insulating layer 152d in the opening OP1 d. In some embodiments, the side cover portion 154Sd may include a first side 154Sd1 covering a portion of a side surface of the barrier layer 123d and a second side 154Sd2 covering a portion of a side surface of the bottom protective insulating layer 152d in the opening OP1 d. First side 154Sd1 and second side 154Sd2 may be spaced apart from each other with a portion of the top surface of barrier layer 123d therebetween.

In some embodiments, first side 154Sd1 may be spaced apart from connection pad 122. In some embodiments, the bottom surface of second side 154Sd2 may contact a portion of the top surface of barrier layer 123 d. The uppermost end of the first side 154Sd1 and the uppermost end of the second side 154Sd2 may be disposed at the same level as the bottom surface of the sub-step STsd and the bottom surface of the step STd, respectively, or may be disposed at a lower level than the bottom surface of the sub-step STsd and the bottom surface of the step STd, respectively.

In the side surface of the barrier layer 123d in the opening OP1d, the lower portion may have a gentler slope than the slope of the upper portion. For example, the slope of the lower portion of the barrier layer 123d may be smaller than the slope of the upper portion of the barrier layer 123 d. Further, for example, the slope of the barrier layer 123d may be recessed upward away from the connection pad 122. Barrier 123d can include a tail 123TA adjacent to the bottom surface of opening OP1 d. The tail portion 123TA may be a portion of the lower portion of the barrier 123d adjacent to the bottom surface of the opening OP1d, the lower portion of the barrier 123d including a side surface having a gentler slope than the slope of the side surface of the upper portion of the barrier 123 d.

The first side part 154Sd1 may be disposed on a side surface of an upper portion of the barrier 123d, and may not be disposed at the tail part 123TA of the barrier 123d (i.e., a side surface of a lower portion of the barrier 123 d).

The top cover portion 154T may be disposed between the bottom protective insulating layer 152d and the top protective insulating layer 156. The top cover portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152d and the bottom surface of the top protective insulating layer 156. The top cover portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152d (e.g., the top surface (i.e., the relatively high top surface) of the protrusion PRT of the bottom protective insulating layer 152 d). Further, the top cover portion 154T may not cover the top surface of the bottom protective insulating layer 152d in the region of the step STd. The top cover portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

Fig. 5 is a cross-sectional view illustrating a system 1 including a semiconductor package according to the disclosed embodiment, and fig. 6A and 6B are enlarged cross-sectional views illustrating a first top connection pad and a second top connection pad both included in the semiconductor package of the system 1 according to the disclosed embodiment.

Referring to fig. 5, the system 1 may include a main board 600 on which an interposer 500 is mounted, a semiconductor package 1000 including a first semiconductor chip 100 and a plurality of second semiconductor chips 200 each attached on the interposer 500, and a third semiconductor chip 400. The semiconductor package 1000 has already been described in detail with reference to fig. 3, and therefore, a repetitive description thereof is omitted.

The third semiconductor chip 400 may include a third semiconductor substrate 410, a third top connection pad 420, a third protective insulating layer 450, and a third connection terminal 440. The third connection terminal 440 may include a third conductive pillar 442 on the third top connection pad 420 and a third conductive cap 446 on the third conductive pillar 442. In some embodiments, a third cover post, the same as or similar to the cover post 244 shown in fig. 6B, may be disposed between the third conductive post 442 and the third conductive cap 446. The third semiconductor substrate 410, the third top connection pad 420, the third protective insulating layer 450, and the third connection terminal 440 are substantially similar (or identical) elements to the first semiconductor substrate 110, the first top connection pad 122, the first protective insulating layer 150, and the first connection terminal 140, respectively, illustrated in fig. 3, or substantially similar (or identical) elements to the second semiconductor substrate 120, the second top connection pad 222, the second protective insulating layer 250, and the second internal connection terminal 240, respectively, illustrated in fig. 3, respectively, and thus, detailed descriptions thereof are omitted.

The third semiconductor chip 400 may be, for example, a CPU chip, a GPU chip, or an AP chip.

The interposer 500 may include a base layer 510, a first top pad 522 disposed on a top surface of the base layer 510, and a first bottom pad 524 disposed on a bottom surface of the base layer 510.

The substrate layer 510 may comprise a semiconductor, glass, ceramic, or plastic. For example, the base layer 510 may include silicon. Wiring layers connected to the first top pads 522 and/or the first bottom pads 524 may be disposed on the top and/or bottom surfaces of the base layer 510, and internal through electrodes electrically connecting the first top pads 522 to the first bottom pads 524 may be formed in the base layer 510. The first connection terminals 140 electrically connecting the semiconductor package 1000 to the interposer 500 and the third connection terminals 440 electrically connecting the third semiconductor chip 400 to the interposer 500 may be connected to the first top pads 522.

The first underfill layer 380 may be disposed between the semiconductor package 1000 and the interposer 500, and the second underfill layer 480 may be disposed between the third semiconductor chip 400 and the interposer 500. The first and second underfill layers 380 and 480 may surround the first and third connection terminals 140 and 440, respectively. The system 1 may further include an encapsulation molding layer 900, the encapsulation molding layer 900 surrounding a side surface of the semiconductor package 1000 and a side surface of the third semiconductor chip 400 on the interposer 500. The package molding layer 900 may include EMC, for example.

The system connection terminal 540 may be attached to the first bottom pad 524. The system connection terminals 540 may electrically connect the interposer 500 to the motherboard 600.

The motherboard 600 may include a base slab 610, a second top pad 622 disposed on a top surface of the base slab 610, and a second bottom pad 624 disposed on a bottom surface of the base slab 610. In some embodiments, motherboard 600 may be a Printed Circuit Board (PCB). For example, the main board 600 may be a multi-layer PCB. The base plate layer 610 may include at least one material selected from among a phenol resin, an epoxy resin, and a polyimide.

A solder resist layer (not shown) exposing the second top pad 622 and the second bottom pad 624 may be formed on each of the top surface and the bottom surface of the base plate layer 610. The system connection terminal 540 may be connected to the second top pad 622 and the external connection terminal 640 may be connected to the second bottom pad 624. System connection terminals 540 may electrically connect the first bottom pad 524 to the second top pad 622. The external connection terminal 640 connected to the second bottom pad 624 may connect the system 1 to the outside.

In some embodiments, the system 1 may not include the motherboard 600 (and the external connection terminals 640 of the motherboard 600), and the system connection terminals 540 of the interposer 500 may perform similar functions as the external connection terminals 640 without the presence of the external connection terminals 640.

In some embodiments, where system 1 is used as part of a larger system, system 1 may be referred to as a main semiconductor package and semiconductor package 1000 may be referred to as a sub-semiconductor package.

Referring to fig. 6A, the first connection terminal 140 may electrically connect the first top connection pad 122 to the first top pad 522. The first connection terminal 140 may include a first base pillar 142 (first conductive pillar) on the first top connection pad 122 and a first conductive cap 146 on the first base pillar 142. In some embodiments, a first cover post 144 may be disposed between the first substrate post 142 and the first conductive cap 146.

The first substrate pillar 142 may include, for example, copper, and the first capping pillar 144 may include, for example, at least one of nickel, copper, palladium, platinum, and gold. In some embodiments, the first capping post 144 may comprise nickel. In some other embodiments, the first capping post 144 may have a multi-layer structure including a first layer including nickel and a second layer covering the first layer and including copper.

The first conductive caps 146 may contact the first top pads 522 of the interposer 500 to electrically connect the first semiconductor chip 100 to the interposer 500. The first conductive cap 146 may include, for example, at least one of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), gold (Au), zinc (Zn), and lead (Pb).

The first substrate pillar 142 may be formed to fill the first opening OP1 and protrude with respect to the top surface of the bottom protective insulating layer 152 and the top surface of the cover insulating layer 154. In fig. 6A, the top surface of the first substrate pillar 142 is shown disposed at a level higher than the top surface of the cover insulating layer 154 and lower than the top surface of the top protective insulating layer 156, but is not limited thereto. In some embodiments, the top surface of the first substrate pillar 142 may be disposed at a higher level than the top surface of the top protective insulating layer 156.

The first substrate pillar 142 may be formed to be spaced apart from the protrusion PRT of the bottom protective insulating layer 152. The side surface of the lower portion of the first substrate pillar 142 may contact the side covering portion 154S. The side cover portions 154S may be disposed between the first substrate pillars 142 and each of the bottom protective insulating layer 152 and the first barrier layer 123. The first substrate column 142 may be spaced apart from the top cover portion 154T. For example, there may be a gap or opening between first substrate post 142 and top covering portion 154T.

Referring to FIG. 6B, the second internal connection terminals 240 may electrically connect the second top connection pad 222 to the first bottom connection pad 124 or may electrically connect the second top connection pad 222 to the second bottom connection pad 224. The second internal connection terminal 240 may include a second substrate pillar 242 on the second top connection pad 222 and a second conductive cap 246 on the second substrate pillar 242. In some embodiments, the second cover pillar 244 may be disposed between the second substrate pillar 242 and the second conductive cap 246.

The second conductive cap 246 may contact the first bottom connection pad 124 of the first semiconductor chip 100 or the second bottom connection pad 224 of another second semiconductor chip 200 (a different second semiconductor chip 200 of the plurality of second semiconductor chips 200) to electrically connect the second semiconductor chip 200 to the first semiconductor chip 100 or to electrically connect the different second semiconductor chip 200 of the plurality of second semiconductor chips 200.

The second substrate pillar 242 may be formed to fill the second opening OP2 and protrude with respect to the top surface of the second protective insulating layer 250. For example, the second substrate pillar 242 may be formed to completely fill the second opening OP 2. The second protective insulating layer 250 may include the same material as that of the bottom protective insulating layer 152 illustrated in fig. 6A. The side surface of the lower portion of the second substrate pillar 242 may contact the second protective insulating layer 250.

The second protective insulating layer 250 may be formed in a shape similar to that of the intermediate resultant material of the bottom protective insulating layer 152 illustrated in fig. 2B by using the method of manufacturing the bottom protective insulating layer 152 illustrated in fig. 2A and 2B. That is, unlike the first protective insulating layer 150 illustrated in fig. 6A, the second protective insulating layer 250 may not include elements corresponding to the cover insulating layer 154 and the top protective insulating layer 156 and may not include the step ST and the protrusion PRT, both of which are included in the bottom protective insulating layer 152.

Fig. 7A-7D are enlarged cross-sectional views illustrating a first top connection pad included in a semiconductor package of a system according to a disclosed embodiment. Fig. 7A to 7D are substantially the same as fig. 4A to 4D, respectively, except that protective insulating layers 150a to 150D and barrier layers 123a to 123D, respectively, shown in fig. 4A to 4D are provided instead of the first protective insulating layer 150 and the first barrier layer 123 of fig. 6A, respectively, and thus, the same or similar descriptions as those of fig. 4A to 4D and 6A may be omitted.

Referring to fig. 7A, the first substrate pillar 142 may be formed to be separated from the protrusion PRT of the bottom protective insulating layer 152 a. A side surface of a lower portion of the first substrate pillar 142 may contact the side covering portion 154 Sa. The side cover portions 154Sa may be disposed between the first substrate pillars 142 and each of the bottom protective insulating layer 152a and the barrier layer 123 a.

Referring to fig. 7B, the first substrate pillar 142 may be formed to be spaced apart from the protrusion PRT of the bottom protective insulating layer 152B. For example, a gap may exist between the first substrate pillar 142 and the bottom protective insulating layer 152 b. The side surface of the lower portion of the first substrate pillar 142 may contact the first and second side portions 154Sb1 and 154Sb2 disposed apart from each other. The first side portion 154Sb1 may be disposed between the barrier layer 123b and the first substrate pillar 142, and the second side portion 154Sb2 may be disposed between the bottom protective insulating layer 152b and the first substrate pillar 142.

Referring to fig. 7C, the first substrate pillar 142 may be formed to be spaced apart from the protrusion PRT of the bottom protective insulating layer 152C. For example, a gap may exist between the first substrate pillar 142 and the bottom protective insulating layer 152 c. A lowermost side surface of the first substrate pillar 142 may contact the barrier layer 123c, and a lower side surface of the first substrate pillar 142 that does not contact the barrier layer 123c (i.e., an upper side surface instead of the lowermost side surface) may contact the side covering portion 154 Sc. The side cover portions 154Sc may be disposed between the bottom protective insulating layer 152c and the first substrate pillars 142.

Referring to fig. 7D, the first substrate pillar 142 may be formed to be separated from the protrusion PRT of the bottom protective insulating layer 152D. A side surface of a lower portion of the first substrate pillar 142 may contact the first and second side portions 154Sd1 and 154Sd2 disposed apart from each other. The first side portion 154Sd1 may be disposed between the barrier layer 123d and the first substrate pillar 142, and the second side portion 154Sd2 may be disposed between the bottom protective insulating layer 152d and the first substrate pillar 142.

The side surface of the lower portion of the first substrate pillar 142 may sequentially contact the tail portion 123TA of the barrier 123d, the first side portion 154Sd1, a portion of the top surface of the barrier 123d, and the second side portion 154Sd2 from the lowermost portion of the first substrate pillar 142.

Fig. 8A-8D are enlarged cross-sectional views illustrating a second top connection pad included in a semiconductor package of a system according to a disclosed embodiment. Each of fig. 8A to 8D is substantially the same as fig. 6B except that second protective insulating layers 250a to 250D and barrier layers 223a to 223D are provided instead of the second protective insulating layers 250 and the second barrier layers 223 of fig. 6B, and thus, the same or similar description as that of fig. 6B may be omitted.

Referring to fig. 8A, the second protective insulating layer 250a may include a second opening OP2a exposing at least a portion of the second top connection pad 222. The second substrate pillar 242 may be formed to fill the second opening OP2a and protrude with respect to the top surface of the second protective insulating layer 250 a. The second opening OP2a may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the second opening OP2a to the upper portion of the second opening OP2 a. The second protective insulating layer 250a and the second barrier layer 223a may have horizontal widths that decrease in the distant direction (vertical direction) from the bottom surface of the second opening OP2a to the upper portion of the second opening OP2 a. That is, the side surface of the second protective insulating layer 250a in the second opening OP2a and the side surface of the second barrier 223a in the second opening OP2a may be inclined away from the opening OP2a and may extend upward. Side surfaces of the lower portion of the second substrate pillar 242 may contact side surfaces of the second protective insulating layer 250a and side surfaces of the second barrier layer 223 a.

Referring to fig. 8B, the second protective insulating layer 250B may include a second opening OP2B exposing at least a portion of the second top connection pad 222. The second substrate pillar 242 may be formed to fill the second opening OP2b and protrude with respect to the top surface of the second protective insulating layer 250 b. The second opening OP2b may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the second opening OP2b to the upper portion of the second opening OP2 b. The second protective insulating layer 250b and the second barrier layer 223b may have horizontal widths that decrease in the distant direction (vertical direction) from the bottom surface of the second opening OP2b to the upper portion of the second opening OP2 b. That is, the side surface of the second protective insulating layer 250b in the second opening OP2b and the side surface of the second barrier 223b in the second opening OP2b may be inclined away from the second opening OP2b and may extend upward. Side surfaces of the lower portion of the second substrate pillar 242 may contact side surfaces of the second protective insulating layer 250b and side surfaces of the second barrier layer 223 b.

An intermediate step STmb may be formed between the second protective insulating layer 250b and the second barrier layer 223b in the second opening OP2 b. The middle step STmb may be defined by a side surface of the second protective insulating layer 250b and a top surface of the second barrier layer 223b in the second opening OP2 b. The width of the portion of the second opening OP2b at the level where the second barrier 223b is disposed may have a value smaller than that of the portion of the second opening OP2b at the level where the second protective insulating layer 250b is disposed.

Referring to fig. 8C, the second protective insulating layer 250C may include a second opening OP2C exposing at least a portion of the second top connection pad 222. The second substrate pillar 242 may be formed to fill the second opening OP2c and protrude with respect to the top surface of the second protective insulating layer 250 c. The second opening OP2c may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the second opening OP2c to the upper portion of the second opening OP2 c. The second protective insulating layer 250c and the second barrier layer 223c may have horizontal widths that decrease in the distant direction from the bottom surface of the second opening OP2c to the upper portion of the second opening OP2 c. That is, the side surface of the second protective insulating layer 250c in the second opening OP2c and the side surface of the second barrier layer 223c in the second opening OP2c may be inclined away from the second opening OP2c and may extend upward.

A side surface of the second barrier layer 223c adjacent to the second opening OP2c may be inclined less than a side surface of the second protective insulating layer 250c facing the second protective insulating layer 250 c. That is, an acute angle between the top surface of the second barrier layer 223c and the side surface of the second protective insulating layer 250c may be greater than an acute angle between the bottom surface of the second barrier layer 223c and the side surface of the second barrier layer 223 c. Side surfaces of the lower portion of the second substrate pillar 242 may contact side surfaces of the second protective insulating layer 250c and side surfaces of the second barrier layer 223 c.

An intermediate step STmc may be formed between the second protective insulating layer 250c and the second barrier layer 223c in the second opening OP2 c. The middle step STmc may be defined by a side surface of the second protective insulating layer 250c and a top surface of the second barrier layer 223 c. The width of the portion of the second opening OP2c at the level where the second barrier 223c is disposed may have a value smaller than that of the portion of the second opening OP2c at a level above the level where the second barrier 223c is disposed.

Referring to fig. 8D, the second protective insulating layer 250D may include a second opening OP2D exposing at least a portion of the second top connection pad 222. The second substrate pillar 242 may be formed to fill the second opening OP2d and protrude with respect to the top surface of the second protective insulating layer 250 d. The second opening OP2d may have a horizontal width that increases in the distant direction (vertical direction) from the bottom surface of the second opening OP2d to the upper portion of the second opening OP2 d. The second protective insulating layer 250d and the second barrier layer 223d may have horizontal widths that decrease in the distant direction (vertical direction) from the bottom surface of the second opening OP2d to the upper portion of the second opening OP2 d. That is, the side surface of the second protective insulating layer 250d in the second opening OP2d and the side surface of the second barrier layer 223d in the second opening OP2d may be inclined away from the opening and may extend upward.

A side surface of the second barrier layer 223d adjacent to the second opening OP2d may be differently inclined adjacent to a side surface of the second protective insulating layer 250d and the second protective insulating layer 250 d. That is, the slope of the side surface of the second barrier 223d may vary. For example, the slope of the side surface of the second barrier layer 223d at the lower portion closest to the second top connection pad 222 may be smaller than the slope of the side surface of the second barrier layer 223d at the upper portion farther from the second top connection pad 222. An inclination angle of a side surface of the second barrier layer 223d at an upper portion farther from the second top connection pad 222 may be smaller than an inclination angle between a bottom surface of the second barrier layer 223d and the side surface of the second barrier layer 223 d. Side surfaces of the lower portion of the second substrate pillar 242 may contact side surfaces of the second protective insulating layer 250d and side surfaces of the second barrier layer 223 d.

A side surface of the second barrier 223d adjacent to the lower portion of the second opening OP2d may have a gentler slope than that of the upper side surface. The second barrier 223d may include a tail portion 223TA adjacent to the bottom surface of the second opening OP2 d. The tail portion 223TA may be a portion adjacent to a lower portion of the second barrier layer 223d near the second top connection pad 222 and may include a side surface having a gentler slope than that of a side surface of an upper portion of the second barrier layer 223 d.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.