阅读说明：本技术 半导体封装及其制造方法 (Semiconductor package and method of manufacturing the same ) 是由 方绪南 陈建庆 翁振源 于 2019-12-24 设计创作，主要内容包括：本公开提供一种半导体封装,其包含：半导体裸片,其具有第一表面和与所述第一表面相对的第二表面；传导性布线层,其与所述半导体裸片堆叠且接近所述第一表面；封装体,其包封所述半导体裸片且与所述传导性布线层堆叠；以及替换结构,其从所述封装体暴露且无填充物。本公开中还公开了一种用于制造所述半导体封装的方法。(The present disclosure provides a semiconductor package, comprising: a semiconductor die having a first surface and a second surface opposite the first surface; a conductive routing layer stacked with the semiconductor die and proximate the first surface; a package enclosing the semiconductor die and stacked with the conductive routing layer; and a replacement structure exposed from the package body and free of a filler. Also disclosed in the present disclosure is a method for manufacturing the semiconductor package.)

1. A semiconductor package, comprising:

a semiconductor die having a first surface and a second surface opposite the first surface;

a conductive routing layer stacked with the semiconductor die and proximate the first surface;

a package enclosing the semiconductor die and stacked with the conductive routing layer; and

an alternate structure exposed from the package body and free of filler.

2. The semiconductor package of claim 1, wherein the package body comprises the filler.

3. The semiconductor package of claim 1, wherein a side surface of the semiconductor die is spaced apart from the alternative structure by a distance of about 3 μ ι η to about 10 μ ι η, the side surface connecting the first surface and the second surface.

4. The semiconductor package of claim 1, wherein a height of the replacement structure is greater than a distance between the first surface and the second surface.

5. The semiconductor package of claim 1, wherein the replacement structure surrounds four sides of the semiconductor die.

6. The semiconductor package of claim 1, wherein a height of the replacement structure is substantially the same as a height of the package body.

7. The semiconductor package of claim 1, wherein the replacement structure comprises a wider end proximate the first surface of the semiconductor die and a narrower end proximate the second surface of the semiconductor die.

8. The semiconductor package of claim 1, wherein the conductive routing layer is a fan-out redistribution layer (RDL).

9. The semiconductor package of claim 8, further comprising a substrate electrically connected to the fan-out RDL.

10. The semiconductor package of claim 1, wherein the second surface, the package body, and the replacement structure are substantially coplanar.

11. A semiconductor package, comprising:

a semiconductor die having a first surface and a second surface opposite the first surface;

a conductive routing layer stacked with the semiconductor die and proximate the first surface;

a package encapsulating the semiconductor die and stacked with the conductive routing layer, the package having a first modulus; and

an alternate structure exposed from the package body and having a second modulus,

wherein the second modulus is greater than the first modulus.

12. The semiconductor package of claim 11, wherein the conductive routing layer comprises a third modulus, wherein the second modulus is greater than the third modulus.

13. The semiconductor package of claim 11, wherein a side surface of the semiconductor die is spaced apart from the alternative structure by a distance of about 3 μ ι η to about 10 μ ι η, the side surface connecting the first surface and the second surface.

14. The semiconductor package of claim 11, wherein the package body comprises a filler and the replacement structure is free of the filler.

15. The semiconductor package of claim 11, wherein the replacement structure comprises a ceramic, glass, or pre-impregnated composite optical fiber in the form of an epoxy matrix.

16. The semiconductor package of claim 11, wherein the replacement structure surrounds four sides of the semiconductor die.

17. The semiconductor package of claim 11, wherein a height of the replacement structure is greater than a distance between the first surface and the second surface.

18. A method for manufacturing a semiconductor package, comprising:

providing a first carrier having a first surface;

disposing an alternate structure over the first surface; and

engaging the replacement structures on the first carrier to a second carrier carrying a plurality of semiconductor dies, the replacement structures being aligned with regions separating adjacent semiconductor dies.

19. The method of claim 18, further comprising:

attaching a conductive routing layer over a second surface of the second carrier; and

disposing the plurality of semiconductor dies over the conductive routing layer.

20. The method of claim 19, further comprising:

disposing molding stock on the first surface of the first carrier prior to engaging the first carrier to the second carrier; and

singulating the plurality of semiconductor dies and the conductive routing layer by a half-cut operation after engaging the first carrier to the second carrier.

Technical Field

The present disclosure relates to a semiconductor package, and more particularly, to a fan-out package structure.

Background

To accommodate the development of mobile communication devices, volume reduction (e.g., thinning), manufacturing cost reduction, functional flexibility, and accelerated product cycle time are essential to device packaging.

Grinding is a well-known method in semiconductor packaging to reduce package thickness. Generally, semiconductor dies are disposed on a redistribution layer (RDL), encapsulated with a molding compound, ground to thin the package thickness, and then die sawed or singulated. However, this manufacturing sequence has the following problems: first, the mill package is prone to warping due to insufficient structural stability, and when subsequently singulated, the warping feature may degrade the vacuum suction provided by the base, thereby increasing the difficulty of the singulation operation. Secondly, since the roller blade (roller blade) can raise its rotation speed at the moment of completing the complete cutting, cracks may be generated adjacent to the molding material. For half-cut operations, the roller blade may also crack adjacent molding stock due to inevitable vibrations during operation.

Disclosure of Invention

In some embodiments, the present disclosure provides a semiconductor package comprising: a semiconductor die having a first surface and a second surface opposite the first surface; a conductive routing layer stacked with the semiconductor die and proximate the first surface; a package enclosing the semiconductor die and stacked with the conductive routing layer; and a replacement structure exposed from the package body and free of a filler.

In some embodiments, the present disclosure provides a semiconductor package comprising: a semiconductor die having a first surface and a second surface opposite the first surface; a conductive routing layer stacked with the semiconductor die and proximate the first surface; a package encapsulating the semiconductor die and stacked with the conductive routing layer, the package having a first modulus; and a replacement structure exposed from the package body and having a second modulus. The second modulus is greater than the first modulus.

In some embodiments, the present disclosure provides a method for manufacturing a semiconductor package, the method comprising: providing a first carrier having a first surface; disposing an alternate structure over the first surface; and engaging the replacement structures on the first carrier to a second carrier carrying a plurality of semiconductor dies, the replacement structures being aligned with regions separating adjacent semiconductor dies.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 2 illustrates a top view of the semiconductor package in fig. 1, in accordance with some embodiments of the present disclosure.

Fig. 3 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 4 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 5 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 6 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 7 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 8 illustrates a cross-sectional view of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 9A-9C illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package, according to some embodiments of the present disclosure.

Fig. 9C illustrates a top view of the intermediate product in fig. 9C, according to some embodiments of the present disclosure.

Fig. 10A-10L illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package, according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions, such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above," "below," and the like, are specified with respect to a component or group of components or a plane of a component or group of components for orienting one or more components as shown in the associated figures. It is to be understood that the spatial description used herein is for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not so arranged.

The present disclosure provides a fan-out thinned package and a method of manufacturing the same. In contrast to the comparative examples, the package structure of the present disclosure was singulated prior to applying the grinding operation. When in panel or matrix form, the semiconductor package structure is half-cut and then a grinding operation is applied to reduce the package thickness to a desired level. This manufacturing sequence effectively addresses the lack of structural stability after grinding, the deterioration of vacuum suction at the time of singulation, and warpage caused by peeling/cracking of adjacent molding material during roller blading.

The package structures described in this disclosure include alternative structures having a modulus higher than the modulus of the molding compound and the RDL. The replacement structure surrounds the semiconductor die and overlaps the saw streets. The dimensions of the replacement structures are adjustable to achieve an optimal structural balance between the molding compound, the replacement structures, the semiconductor die, and the RDL.

Referring to fig. 1, fig. 1 illustrates a cross-sectional view of a semiconductor package 10, according to some embodiments of the present disclosure. The semiconductor package 10 includes a semiconductor die 100 having a first surface 100A and a second surface 100B opposite the first surface 100A. In some embodiments, the first surface 100A is an active surface, with a plurality of conductive elements 101 adjacent to, embedded below, and/or partially exposed from the active surface. The conductive elements 101 may include conductive pads, conductive pillars, solder bumps, C4 bumps, and equivalents thereof. Conductive elements 101 on the first surface are configured to form electrical connections with conductive routing layers 103 stacked with semiconductor die 100. The conductive routing layer 103 is closer to the first surface 100A than to the second surface 100B of the semiconductor die 100. In some embodiments, conductive routing layer 103 is a redistribution layer (RDL) comprised of a dielectric layer and conductive lines embedded in the dielectric layer. In some embodiments, conductive routing layer 103 is a fan-out RDL that expands the area coverage of conductive elements 101 on first surface 100A of semiconductor die 100.

Package 105 surrounds semiconductor die 100 and conductive element 101, and is disposed on conductive routing layer 103. In some embodiments, the package body 105 is composed of an epoxy compound and a filler. In some embodiments, package 105 is an Encapsulating Molding Compound (EMC) commonly used to protect Integrated Circuit (IC) chips. Its composition always contains a large amount (about 70%) of filler and affects EMC properties. In some embodiments, the filler comprises various types of oxides, silicon oxide, or silica. Alternate structure 107 is partially encapsulated by package 105, surrounds side surface 100C of semiconductor die 100, and is exposed from package 105 on the top and side surfaces of package 105. The side surface 100C of the semiconductor die 10 connects the first surface 100A and the second surface 100B of the semiconductor die 10. In some embodiments, unlike package 105, replacement structure 107 is free of any fillers like those in package 105 described above. Referring to fig. 10A through 10G of the present disclosure, the replacement structure 107 is integrated into the semiconductor package 10 by a molding operation that transfers the replacement structure 107 from another carrier to a space between adjacent semiconductor dies 100. The fillers in the package 105, particularly those adjacent to the replacement structure 107, are intact and do not break. In some comparative embodiments, a fracture filler may be typically observed due to removal of a portion of the package 105 after curing the package 105. The mechanical removal process may create a broken fill at the removal boundary of the package 105. The heterogeneous material may then fill the empty spaces of the package resulting from the removal operation. In other words, in the comparative embodiment, the fracture filler may be observed at the boundary between the cured package and the heterogeneous material. In the present disclosure, since the integration of the replacement structure 107 to the semiconductor die 100 is before the curing of the package 105, the filler in the package 105, even at the boundary between the cured package 105 and the replacement structure 107, is intact and not broken.

In some embodiments, the young's modulus (hereinafter modulus) of the replacement structure 107 is greater than the modulus of the package body 105. In some embodiments, the modulus of the replacement structure 107 is greater than the modulus of the conductive wiring layer 103. For example, the modulus of the package 105 may be in the range of about 20GPa to 30GPa, and the modulus of the conductive routing layer 103 may be in the range of about 3 to 5Mpa or 1 to 3GPa, respectively, depending on whether the ambient temperature is below or above the glass transition temperature (Tg). The modulus of the replacement structure 107 may be greater than 50 GPa. In some embodiments, the replacement structure 107 is comprised of a pre-impregnated composite optical fiber in the form of an epoxy matrix having a modulus of about 60GPa to 70 GPa. In some embodiments, the replacement structure 107 may be comprised of glass having a modulus of about 70GPa to 80 GPa. In some embodiments, the replacement structure 107 may be constructed of a ceramic having a modulus greater than 300 GPa. In some embodiments, the replacement structure 107 may be pre-formed with a desired shape or size, for example, the replacement structure 107 may have a columnar cross-section with a uniform width, as illustrated in fig. 1, or the replacement structure 107 may have a wider bottom and a narrower top, as illustrated in fig. 5.

As illustrated in fig. 1, a distance D1 between side surface 100C of semiconductor die 100 and a side surface of replacement structure 107 is in a range of about 3 μm to about 10 μm. Referring to fig. 10A through 10G of the present disclosure, the replacement structure 107 is integrated into the semiconductor package 10 by a molding operation that transfers the replacement structure 107 from another carrier to a space between adjacent semiconductor dies 100. The distance D1 between the side surface 100C of the semiconductor die 100 and the side surface of the replacement structure 107 may be modified by applying a wider or narrower replacement structure 107. The determination of distance D1 may include the following factors: the modulus of the replacement structure 107, the modulus of the package body 105, the modulus of the conductive wiring layer 103, and the corresponding volume suitable for preventing package warpage from occurring after package thinning operations. The distance D1 in the present disclosure is determined to be in the range of about 3 μm to about 10 μm because the process window for aligning the replacement structures 107 and the semiconductor die 100 on two respective carriers is about 3 μm, and a distance D1 greater than 10 μm may reduce throughput by reducing the total number of packages per operation.

As shown in fig. 1, the second surface 100B, the package body 105, and the alternative structure 107 form a coplanar surface as a result of the backside grinding operation, as will be described in fig. 10L of the present disclosure. The package body 105 is exposed from the package at two different locations, a first portion 105A proximate to the second surface 100B, and a second portion 105B proximate to the conductive routing layer 103. In some embodiments, the surface roughness of the second portion 105B is greater than the surface roughness of the first portion 105A. Referring to fig. 10J and 10L of the present disclosure, the first portion 105A is formed by a backside grinding operation and the second portion 105B is formed by a die sawing operation. Sawing blades generally produce a rougher surface than grinders.

As shown in fig. 1, the thickness or height H2 of semiconductor die 100 may be shorter than the height H1 of alternative structure 107. Height H2 is measured from first surface 100A to second surface 100B of semiconductor die 100. In some embodiments, a height difference dH may be observed in semiconductor package 10 because when a saw blade singulates adjacent semiconductor package 10 from a strip or a panel configuration from the side of conductive routing layer 103, peeling or cracking may easily form at the interface of package body 105 and replacement structure 107. Maintaining this interface at a location away from the first surface 100A of the semiconductor die 100 can reduce the likelihood of crack propagation toward the active surface of the semiconductor die 100. Thus, one end of the displacement structure 107 may not be flush with the first surface 100A of the semiconductor die 100, but extends toward the conductive routing layer 103 in order to keep the interface away from the active surface of the semiconductor die 100.

Referring to fig. 2, fig. 2 illustrates a top view 10T of the semiconductor package 10 in fig. 1, according to some embodiments of the present disclosure. In some embodiments, when the semiconductor die 100 has a quadrilateral layout from a top view perspective, the replacement structure 107 surrounds the four sides of the semiconductor die 100 as an abutting element or ring configuration such that when die sawing is performed from each of the orthogonal saw streets surrounding the quadrilateral semiconductor die 100, the sawing blades will interact with the replacement structure 107 having a modulus greater than the package 105.

Referring to fig. 3, fig. 3 illustrates a cross-sectional view of a semiconductor package 30, according to some embodiments of the present disclosure. The semiconductor package 30 is substantially the same as the semiconductor package 10 of fig. 1, except that a substrate 300 is further provided to electrically connect with the conductive wiring layer 103 or the fan-out RDL. In some embodiments, conductive routing layer 103 is connected to an upper surface of substrate 300, such as a printed circuit board, via solder bumps 301. In some embodiments, conductive routing layer 103 or fan-out RDL has a thickness of about 30 μm. In some embodiments, semiconductor package 30 is a fan-out chip on substrate (FOCOS) package.

Referring to fig. 4, fig. 4 illustrates a cross-sectional view of a semiconductor package 40, according to some embodiments of the present disclosure. Semiconductor package 40 is substantially the same as semiconductor package 10 of fig. 1, except that alternate structure 107 has a height H1 that is substantially the same as height H3 of package body 105. In some embodiments, the height H3 of the package body 105 is about 100 μm. Furthermore, a distance D2 between side surface 100C of semiconductor die 100 and a side surface of replacement structure 107 is greater than distance D1 illustrated in fig. 1. As described earlier, the volume (i.e., height and width) of the dummy structure 107 is determined in consideration of the modulus of the dummy structure 107, the modulus of the package body 105, the modulus of the conductive wiring layer 103, and the corresponding volume suitable for preventing package warpage from occurring after the package thinning operation. Once the foregoing criteria are met, the height and width of the replacement structure 107 may be modified accordingly. In some embodiments, distance D2 is in a range from about 3 μm to about 10 μm. Even though height H1 appears substantially the same as height H3, interface INT at least partially filled with package body 105 is observed between the end of alternate structure 107 proximate conductive routing layer 103 and the upper surface of conductive routing layer 103 that receives this end of alternate structure 107, because alternate structure 107 is integrated into semiconductor package 40 by the molding operation that transfers alternate structure 107 from another carrier to the space between adjacent semiconductor dies 100.

Fig. 5 illustrates a cross-sectional view of a semiconductor package 50, according to some embodiments of the present disclosure. The semiconductor package 50 is substantially the same as the semiconductor package 10 of fig. 1, except that the alternative structure 107 has a wider end 107W proximate the first surface 100A of the semiconductor die 100 and a relatively narrower end 107N proximate the second surface 100B of the semiconductor die 100. In some comparative embodiments, the mold chase is designed to create a recess in the package surrounding the semiconductor die. After the demolding operation, the paraffin wax was detected at the side wall and the bottom of the groove due to the facilitation of the demolding operation. Further, in the comparative embodiment, in order to make it easier for the mold chase to be detached from the package body, the shape of the groove may have a wider top and a narrower bottom. In an embodiment of the present invention, the replacement structure 107 partially encapsulated by the package body 105 has a wider end 107W at the top and a narrower end 107N at the bottom, and paraffin is not detectable at the boundary between the replacement structure 107 and the package body 105. Referring to fig. 10A-10L of the present disclosure, the replacement structure 107 is integrated into the semiconductor package 50 by a molding operation that transfers the replacement structure 107 from another carrier to the space between adjacent semiconductor dies 100, which is a different approach than the previous comparative embodiment that utilizes a mold sleeve having a particular shape to create a recess in the package body and then fills the non-homogeneous material into this recess.

Fig. 6 illustrates a cross-sectional view of a semiconductor package 60, according to some embodiments of the present disclosure. The semiconductor package 60 is substantially the same as the semiconductor package 40 of fig. 4, except that the semiconductor package 60 is manufactured by a chip first operation. As will be described in fig. 10A through 10L, semiconductor package 10 is fabricated by a chip last operation in which conductive wiring layer 103 is formed prior to processing semiconductor die 100. In chip-first operation, the semiconductor die 100 is disposed on a carrier, and then the conductive routing layer 103 is built over the carrier and the disposed semiconductor die 100. As shown in fig. 6, the semiconductor die 100, the replacement structure 107, and the package body 105 are disposed on a carrier (not shown in fig. 6) that is subsequently removed. A planarization operation may be performed to obtain a coplanar surface between conductive elements 101, displacement structures 107, and package body 105 of semiconductor die 100. A conductive routing layer 103 or RDL is built over the coplanar surface. The interface INT between the end of the replacement structure 107 proximate to the conductive wiring layer 103 and the surface of the conductive wiring layer 103 receiving this end of the replacement structure 107 is not filled with the package body 105 because the conductive wiring layer 103 is built up on the coplanar surfaces of the conductive element 101, the replacement structure 107, and the package body 105.

Fig. 7 illustrates a cross-sectional view of a semiconductor package 70 according to some embodiments of the present disclosure. Semiconductor package 70 is substantially the same as semiconductor package 10 of fig. 1, except that semiconductor package 70 is fabricated by a chip-first, active side-up operation and replacement structure 107 is shorter than the height of semiconductor die 100. Chip-first operation is described in fig. 6 and reference may be made to fig. 6. As shown in fig. 7, the second surface 100B of the semiconductor die 100, the replacement structure 107, and the package body 105 are disposed on a carrier (not shown in fig. 7) that is subsequently removed. A planarization operation may be performed to obtain a coplanar surface between conductive elements 101, displacement structures 107, and package body 105 of semiconductor die 100. A conductive routing layer 103 or RDL is built over the coplanar surface. The interface between the end of the replacement structure 107 and the package body 105 is away from the first surface 100A or active surface of the semiconductor die 100 in order to prevent crack propagation toward the active surface during die sawing operations, as previously described in fig. 1.

Fig. 8 illustrates a cross-sectional view of a semiconductor package 80, according to some embodiments of the present disclosure. The semiconductor package 80 is substantially the same as the semiconductor package 10 of fig. 1, except that the semiconductor package 80 is fabricated by a chip-first, active side down operation and the replacement structure 107 is shorter than the height of the semiconductor die 100. Chip-first operation is described in fig. 6 and reference may be made to fig. 6. As shown in fig. 8, the conductive elements 101, the replacement structures 107, and the packages 105 on the first surface 100A of the semiconductor die 100 are disposed on a carrier (not shown in fig. 8) that is subsequently removed. The detachment of the carrier exposes coplanar surfaces between the conductive elements 101, the displacement structures 107, and the package body 105 of the semiconductor die 100. A conductive routing layer 103 or RDL is built over the coplanar surface. The interface INT between the end of the replacement structure 107 proximate to the conductive wiring layer 103 and the surface of the conductive wiring layer 103 receiving this end of the replacement structure 107 is not filled with the package body 105 because the conductive wiring layer 103 is built up on the coplanar surfaces of the conductive element 101, the replacement structure 107, and the package body 105.

Fig. 9A-9C illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package, according to some embodiments of the present disclosure. In fig. 9A, a first virtual carrier 900 having a first surface 900A is provided. In fig. 9B, a release film 901 is disposed on the first surface 900A. In fig. 9C, the replacement structure 107 is disposed over the first surface 900A and in contact with the release film. The replacement structure 107 may have a pillar shape having a uniform width from a cross-sectional view. Each of the dummy structures 107 may be equally spaced apart from adjacent dummy structures 107. However, from a top view perspective, the alternative structure 107 may be an abutting element. As illustrated according to the top view perspective in fig. 9C', the alternative structure 107 has a layout of grids, each of which is configured to surround a semiconductor die to be disposed therein.

Referring to fig. 10A-10L, fig. 10A-10L illustrate cross-sectional views of an intermediate product during various manufacturing operations of a semiconductor package, according to some embodiments of the present disclosure. In fig. 10A, a second carrier 1000 having a first surface 1000A is provided. In fig. 10B, a release film 1001 is disposed on the first surface 1000A. In fig. 10C, a conductive routing layer 103 or RDL is built over the first surface 1000A. As previously discussed, fig. 10A-10L illustrate the last manufacturing sequence of a chip, thus forming conductive routing layer 103 prior to processing the semiconductor die. In fig. 10D, a plurality of semiconductor dies 100 are positioned over the second carrier 1000 and electrically connected to the conductive routing layer 103 via, for example, a flip chip bonding configuration. Subsequently, an underfill material is applied to surround the conductive contacts of semiconductor die 100 that are engaged to conductive routing layer 103.

In fig. 10E, package 105 is applied over first carrier 900 with replacement structure 107 disposed. The package body 105 may be a molding compound that fills the spaces between adjacent dummy structures 107. In fig. 10F, a first surface 900A of first carrier 900 is engaged with a first surface 1000A of second carrier 1000, joined by package 105 previously disposed on first surface 900A. During the bonding operation, the replacement structures 107 are aligned with the regions separating adjacent semiconductor dies 10, such that after the bonding operation, each of the replacement structures 107 separates two adjacent semiconductor dies 100. After the bonding operation, the package body 105 fills the space between each of the replacement structures 107, the adjacent semiconductor die 100, the conductive routing layer 103, and the first surface 900A of the first carrier 900.

In fig. 10H, the first carrier 900 is detached from the package body 105 and the replacement structure 107 by removing the release film 901. In fig. 10I, the second carrier 1000 is detached from the conductive wiring layer 103 by removing the release film 1001. In fig. 10J, a singulation operation is performed to separate adjacent semiconductor dies 100 by aligning the sawing blade 1002 with the sawing marks on the conductive routing layer 103. Saw marks (not shown in fig. 10J) are formed on the surface of conductive routing layer 103 and aligned with each of the replacement structures 107. In some embodiments, the singulation operation is a half-cut operation in which the sawing blade 102 passes through the conductive routing layer 103, the package body 105, and along the longitudinal direction of the replacement structure 107. The closed end is formed after the singulation operation because the sawing blade 1002 stops in the replacement structure 107. In other words, a portion of the replacement structure 107 proximate the second surface 100B of the semiconductor die 100 is connected or not separated after the singulation operation.

In fig. 10K, the intermediate semiconductor package as illustrated in fig. 10J is taped (taped) to the abrasive tape 1003 attached to the conductive wiring layer 103. The backside grinding operation is performed as illustrated in fig. 10L. The package 105 proximate the second surface 100B of the semiconductor die 100 is ground until the second surface 100B is exposed. In some embodiments, the semiconductor die 100 is further removed from the second surface 100B to expose a new surface suitable for die thinning targets. In addition, the grinding operation removes the remaining connected replacement structures 107 that hold adjacent semiconductor dies 100 together in the intermediate semiconductor package. The semiconductor die 100 is completely singulated after the back side grinding operation, and the semiconductor die 100 may be picked from the grinding tape 1003 for further processing or integration.

As used herein, and not otherwise defined, the terms "substantially," "approximately," and "about" are used to describe and contemplate minor variations. When used in conjunction with an event or circumstance, the terms can encompass the occurrence of the event or circumstance specifically and the close approximation of the event or circumstance. For example, when used in conjunction with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may refer to two surfaces located along the same plane within a few microns, for example, within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm located along the same plane.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to be limiting. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a difference between the artistic rendition in this disclosure and the actual device. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation.