阅读说明：本技术 半导体封装件 (Semiconductor package ) 是由 松本学 于 2020-02-07 设计创作，主要内容包括：实施方式提供能够提高可靠性的半导体封装件。实施方式的半导体封装件具备：基板,具有第1面；至少一个存储器芯片,包括设置于第1面上的第1存储器芯片；控制器芯片,从存储器芯片分离地设置于第1面上,能够控制第1存储器芯片；密封部件,将第1存储器芯片和控制器芯片密封；以及第1部件,覆盖控制器芯片的周围的至少一部分,导热率比密封部件低。(Embodiments provide a semiconductor package capable of improving reliability. The semiconductor package of the embodiment includes: a substrate having a 1 st face; at least one memory chip including a 1 st memory chip disposed on the 1 st face; a controller chip which is provided on the 1 st surface separately from the memory chip and can control the 1 st memory chip; a sealing member sealing the 1 st memory chip and the controller chip; and a 1 st member covering at least a part of the periphery of the controller chip, the heat conductivity being lower than that of the sealing member.)

1. A semiconductor package includes:

a substrate having a 1 st face;

at least one memory chip including a 1 st memory chip disposed on the 1 st face;

a controller chip provided on the 1 st surface separately from the 1 st memory chip, the controller chip being capable of controlling the 1 st memory chip;

a sealing member sealing the 1 st memory chip and the controller chip; and

and a 1 st member covering at least a part of the periphery of the controller chip, the heat conductivity being lower than that of the sealing member.

2. The semiconductor package according to claim 1,

the 1 st component is located between the 1 st memory chip and the controller chip.

3. The semiconductor package according to claim 1 or 2,

the heat-insulating member further includes a 2 nd member, the 2 nd member having a lower thermal conductivity than the 1 st member and being disposed between the 1 st member and the sealing member.

4. The semiconductor package according to claim 1 or 2,

the substrate further includes a mounting film that fixes the 1 st memory chip and the controller chip to the 1 st surface, respectively, and has a higher thermal conductivity than the sealing member.

5. The semiconductor package according to claim 1 or 2,

the 1 st memory chip and the controller chip are connected with the 1 st surface.

6. The semiconductor package according to claim 1 or 2,

the substrate has internal wiring and has a solder ball on a 2 nd surface opposite to the 1 st surface,

the controller chip has an electrode pad which is formed on the substrate,

the controller chip is electrically connected with the internal wiring via the electrode pad,

the internal wiring can be electrically connected to an external circuit board via the solder ball.

7. The semiconductor package according to claim 1 or 2,

there are a plurality of the memory chips,

the plurality of memory chips constitute: a 1 st memory chip group including a plurality of the memory chips stacked on the 1 st surface and a 2 nd memory chip group including a plurality of the memory chips stacked on the 1 st surface,

the controller chip is located between the 1 st memory chip group and the 2 nd memory chip group.

8. The semiconductor package according to claim 7,

the plurality of memory chips constituting the 1 st memory chip group include the 1 st memory chip and a 3 rd memory chip,

a distance between the 3 rd memory chip and the controller chip is greater than a distance between the 1 st memory chip and the controller chip in a 1 st direction perpendicular to the substrate,

a distance between the 3 rd memory chip and the controller chip is smaller than a distance between the 1 st memory chip and the controller chip in a 2 nd direction horizontal to the substrate and from the 1 st memory chip group toward the controller chip,

the plurality of memory chips constituting the 2 nd memory chip group include a 2 nd memory chip and a 4 th memory chip,

in the 1 st direction, the distance between the 4 th memory chip and the controller chip is larger than the distance between the 2 nd memory chip and the controller chip,

in a 3 rd direction horizontal to the substrate and from the 2 nd memory chip group toward the controller chip, a distance between the 4 th memory chip and the controller chip is smaller than a distance between the 2 nd memory chip and the controller chip.

9. The semiconductor package according to claim 8,

the plurality of memory chips constituting the 1 st memory chip group further include a 5 th memory chip,

in the 1 st direction, the distance between the 5 th memory chip and the controller chip is larger than the distance between the 3 rd memory chip and the controller chip,

in the 2 nd direction, the distance between the 5 th memory chip and the controller chip is smaller than the distance between the 3 rd memory chip and the controller chip,

the plurality of memory chips constituting the 2 nd memory chip group further include a 6 th memory chip,

in the 1 st direction, the distance between the 6 th memory chip and the controller chip is larger than the distance between the 4 th memory chip and the controller chip,

in the 3 rd direction, the distance between the 6 th memory chip and the controller chip is smaller than the distance between the 4 th memory chip and the controller chip.

10. The semiconductor package according to claim 8,

the controller chip overlaps at least a part of at least 1 memory chip belonging to any of the 1 st memory chip group or the 2 nd memory chip group in a plan view seen from the 1 st direction.

11. A semiconductor package includes:

a substrate having a 1 st face;

a memory chip provided in contact with the 1 st surface;

a controller chip provided in contact with the 1 st surface and capable of controlling the memory chip;

a sealing member sealing the memory chip and the controller chip; and

and a wall member provided on the 1 st surface, disposed between the memory chip and the controller chip, having one end in contact with the 1 st surface, and having a thermal conductivity different from that of the sealing member.

12. The semiconductor package according to claim 11,

a length of the wall member in the 1 st direction is greater than a length of the controller chip in the 1 st direction perpendicular to the substrate, and a length of the wall member in the 3 rd direction is greater than a length of the controller chip in the 3 rd direction that is horizontal to the substrate and orthogonal to a 2 nd direction from the controller chip toward the wall member.

13. The semiconductor package according to claim 11 or 12,

the end of the wall member is exposed to the surface of the sealing member.

14. The semiconductor package according to claim 11 or 12,

the sealing member seals the wall member.

15. The semiconductor package according to claim 11 or 12,

the wall member has a thermal conductivity lower than that of the sealing member.

16. The semiconductor package according to claim 11 or 12,

the wall member has a thermal conductivity higher than that of the sealing member.

17. The semiconductor package according to claim 11 or 12,

the controller chip further includes a 1 st member, wherein the 1 st member covers at least a part of the periphery of the controller chip, and has a lower thermal conductivity than the sealing member.

18. The semiconductor package according to claim 11 or 12,

the substrate further includes a mounting film that fixes the memory chip and the controller chip to the 1 st surface, respectively, and has a higher thermal conductivity than the sealing member.

19. The semiconductor package according to claim 11 or 12,

the substrate has internal wiring and has a solder ball on a 2 nd surface opposite to the 1 st surface,

the controller chip has an electrode pad which is formed on the substrate,

the controller chip is electrically connected with the internal wiring via the electrode pad,

the internal wiring can be electrically connected to an external circuit board via the solder ball.

Technical Field

Embodiments of the invention relate to a semiconductor package.

Background

A semiconductor package is provided which includes a semiconductor memory chip and a controller chip for controlling the semiconductor memory chip.

Disclosure of Invention

Embodiments of the invention provide a semiconductor package capable of improving reliability.

The semiconductor package of the embodiment includes: a substrate having a 1 st face; at least one memory chip including a 1 st memory chip disposed on the 1 st face; a controller chip which is provided on the 1 st surface separately from the 1 st memory chip and can control the 1 st memory chip; a sealing member sealing the 1 st memory chip and the controller chip; and a 1 st member covering at least a part of the periphery of the controller chip, the heat conductivity being lower than that of the sealing member.

Drawings

Fig. 1 is a diagram schematically showing a part of the configuration of an electronic device including a circuit board on which a semiconductor package according to embodiment 1 is mounted.

Fig. 2 is a block diagram showing an example of the structure of the semiconductor package according to embodiment 1.

Fig. 3A is a sectional view of the semiconductor package of embodiment 1.

Fig. 3B is a sectional view of the semiconductor package of embodiment 1.

Fig. 4 is a plan view of the semiconductor package of embodiment 1.

Fig. 5 is a sectional view of a semiconductor package according to a modification of embodiment 1.

Fig. 6 is a sectional view of the semiconductor package of embodiment 2.

Fig. 7 is a plan view of the semiconductor package according to embodiment 2 except for a part of the structure thereof.

Fig. 8 is a plan view of the semiconductor package of embodiment 2.

Fig. 9 is a sectional view of a semiconductor package according to a modification of embodiment 2.

Fig. 10 is a sectional view of the semiconductor package of embodiment 3.

Fig. 11 is a sectional view of the semiconductor package of embodiment 3.

Fig. 12 is a plan view of the semiconductor package of embodiment 3.

Fig. 13 is a plan view of the semiconductor package of embodiment 3.

Fig. 14 is a sectional view of the semiconductor package of embodiment 3.

Fig. 15 is a sectional view of the semiconductor package of embodiment 3.

Fig. 16 is a plan view of the semiconductor package of embodiment 3.

Description of the reference numerals

1: semiconductor package, 2: circuit board, 3: host controller, 4: signal line, 5: power supply circuit, 6: power supply line, 11: controller chip, 12: semiconductor memory chip (NAND chip), 13: DRAM chip, 14: oscillator (OSC), 15: EEPROM, 16: temperature sensor, 21: substrate, 22: seal member, 23: part 1, 24: assembly film, 25: solder ball, 26: internal wiring, 27: electrode pad, 28: electrode pad, 29: part 2, 201: lead (wire), 202: lead, 31: wall member, 311: 1 st end, 312: end 2, 313: end 3, 314: end part 4

Detailed Description

Hereinafter, embodiments for carrying out the present invention will be described.

In the present specification, a plurality of expressions are given to several elements. Examples of these expressions are merely illustrative, and other expressions are not given to the above-described elements. Further, elements to which a plurality of expressions are not assigned may be assigned with another expression.

The drawings are schematic, and the relationship between the thickness and the planar size, the ratio of the thicknesses of the respective layers, and the like may be different from the actual ones. In addition, the drawings may include portions having different dimensional relationships and ratios from each other.

First, the + X direction, -X direction, + Y direction, -Y direction, + Z direction, and-Z direction are defined. The + X direction is a direction horizontal to the substrate 21 described later and directed from the controller chip 11 toward the semiconductor memory chip 12. the-X direction is the opposite of the + X direction. In the case where the + X direction and the-X direction are not distinguished, they are referred to as only the "X direction". The + Y direction is a direction horizontal to the substrate 21 and intersecting (e.g., substantially orthogonal to) the X direction. the-Y direction is the opposite of the + Y direction. In the case where the + Y direction and the-Y direction are not distinguished, they are referred to as only the "Y direction". The + Z direction is a direction perpendicular to the substrate 21, is a direction intersecting (e.g., substantially orthogonal to) the X direction and the Y direction, and is a direction from the substrate 21 toward the controller chip 11. the-Z direction is a direction from the substrate 21 toward the solder ball 25, and is a reverse direction of the + Z direction. In the case where the + Z direction and the-Z direction are not distinguished, they are simply referred to as "Z direction". The Z direction is, for example, a thickness direction of the substrate 21.

(embodiment 1)

Fig. 1 to 5 show a semiconductor package 1 of embodiment 1. The semiconductor package 1 is an example of a semiconductor device. The semiconductor package according to the present embodiment is, for example, a BGA-SSD (Ball Grid Array-Solid State Drive), and is integrally configured as one BGA-type package by at least 1 semiconductor memory chip and a controller chip for controlling the semiconductor memory chip. Such a semiconductor package is mounted on an electronic device such as a Personal Computer (PC) or a mobile phone, and functions as a storage device for the electronic device.

Fig. 1 schematically shows a part of the structure of a circuit board 2 used when a semiconductor package 1 is mounted on an electronic device. The circuit board 2 includes a host controller 3, a signal line 4, a power supply circuit 5, and power supply lines 6(6a, 6 b). The host controller 3 and the semiconductor package 1 according to the present embodiment have interfaces conforming to the PCI express (pcie) (registered trademark) standard. A plurality of signal lines 4 are provided between the host controller 3 and the semiconductor package 1. The semiconductor package 1 transmits and receives high-speed signals conforming to the PCIe standard to and from the host controller 3 via the signal line 4. The power supply circuit 5 is connected to the host controller 3 and the semiconductor package 1 via power supply lines 6(6a, 6b), respectively. The power supply line 6a connects the power supply circuit 5 and the host controller 3, and the power supply line 6b connects the power supply circuit 5 and the semiconductor package 1. The power supply circuit 5 supplies power for operating the electronic device to the host controller 3 and the semiconductor package 1.

Other standards such as sas (Serial Attached scsi), sata (Serial Advanced Technology attachment), usb (universal Serial bus), and the like may be used for the communication interface of the host controller 3 and the semiconductor package 1.

The host controller 3 mounted on the electronic device is, for example, a CPU, and controls the entire electronic device including a storage device connected to or mounted on the electronic device.

Next, the structure of the semiconductor package 1 will be described.

Fig. 2 is a block diagram showing an example of the structure of the semiconductor package 1. The semiconductor package 1 has a controller chip (controller) 11, a semiconductor memory chip 12, a DRAM chip 13, an Oscillator (OSC)14, an eeprom (electrically Erasable and Programmable rom)15, and a temperature sensor 16.

The controller chip 11 is a semiconductor chip that controls the operation of the semiconductor memory chip 12. The semiconductor memory chip 12 is, for example, a NAND-type flash memory chip (NAND chip). The NAND chip is a nonvolatile memory and holds data even in a state where power is not supplied. The DRAM chip (DRAM)13 is used for storing management information of the semiconductor memory chip 12, caching data, and the like.

The Oscillator (OSC)14 supplies an operation signal of a predetermined frequency to the controller chip 11. The EEPROM15 is an example of a nonvolatile memory in which a control program and the like are stored. The temperature sensor 16 detects the temperature inside the semiconductor package 1 and notifies the controller chip 11.

The controller chip 11 consumes a large amount of power among the semiconductor chips mounted on the semiconductor package 1, and therefore tends to be at a higher temperature than other semiconductor chips. If the heat of the controller chip 11 is transferred to other semiconductor chips, the performance of the other semiconductor chips is degraded.

For example, in the DRAM chip 13, if the temperature rises, the efficiency of the refresh cycle is lowered, and data is likely to be lost. In addition, in a nonvolatile semiconductor memory chip such as the NAND chip 12, when the temperature rises, the data retention capability is lowered, and the reliability of the stored data is lowered.

Next, the structure of the semiconductor package 1 according to embodiment 1 will be described.

Fig. 3A and 3B are sectional views of the semiconductor package 1, and fig. 4 is a plan view of the semiconductor package 1. In fig. 3A, 3B, and 4, for convenience of explanation, the oscillator 14, the EEPROM15, and other parts included in the semiconductor package 1 are omitted. Hereinafter, the semiconductor memory chip is also referred to as a memory chip.

The semiconductor package 1 includes a substrate 21, a controller chip 11, at least 1 or more semiconductor memory chips 12, a sealing member 22, a 1 st member 23, and a plurality of solder balls 25.

The substrate 21 has a mount film 24 on the surface thereof and an internal wiring 26 therein. The substrate 21 has a 1 st surface 21a and a 2 nd surface 21b located on the opposite side of the 1 st surface 21 a.

The controller chip 11 is disposed on the 1 st surface 21 a. The controller chip 11 is fixed on the substrate 21 by a mount film 24. The controller chip 11 has electrode pads 28 and is electrically connected to the internal wiring 26. The controller chip 11 is connected by wire bonding (wire bonding) based on the leads 202 as shown in fig. 3A or flip chip bonding as shown in fig. 3B, for example.

The semiconductor memory chip 12 and the controller chip 11 are provided on the 1 st surface 21a with a space in the X direction, and are fixed to the substrate 21 by a mount film 24. The semiconductor memory chip 12 has electrode pads 27. For example, the semiconductor memory chip 12 is electrically connected to the internal wiring 26 by wire bonding in which the wire 201 and the electrode pad 27 are connected. The semiconductor memory chip 12 is electrically connected to the controller chip 11 via internal wiring 26.

The sealing member 22 is a member that seals the controller chip 11 and the semiconductor memory chip 12 on the substrate 21.

The mounting film 24 to which the controller chip 11 is fixed may have a higher thermal conductivity than the sealing member 22. In this case, the controller chip 11 functions to efficiently transfer heat to the substrate 21.

The 1 st member 23 is provided on the 1 st surface 21a, and covers at least a part of the periphery of the controller chip 11. The periphery here refers to a surface other than the surface where the controller chip 11 and the substrate 21 are in contact with each other. Also, the 1 st component 23 is located between the controller chip 11 and the semiconductor memory chip 12 in the X direction. The 1 st member 23 has lower thermal conductivity than the sealing member 22, and is difficult to transmit heat generated from the controller chip 11 to the semiconductor memory chip 12.

The substrate 21 includes a solder ball 25 on the 2 nd surface 21b, and can be electrically connected to the circuit board 2 of the electronic device via the solder ball 25.

According to the above configuration, heat of the controller chip 11 is hard to be transmitted to the sealing member 22 due to the 1 st member 23, and similarly, to other semiconductor chips such as the semiconductor memory chip 12. Heat of the controller chip 11 is radiated toward the circuit board 2 through the mount film 24, the substrate 21, and the solder balls 25. Therefore, the influence of heat conduction to other semiconductor chips in the semiconductor package 1 such as the semiconductor memory chip 12 can be suppressed, and the function degradation due to heat can be prevented.

(modification example)

The semiconductor package 1 of the present embodiment may include the 2 nd member 29 as shown in fig. 5. The 2 nd part 29 is arranged to also cover at least a part of the circumference of the 1 st part 23. The periphery referred to herein means a surface other than the surface of the 1 st member 23 in contact with the substrate 21. Also, the 2 nd component 29 is located between the 1 st component 23 and the semiconductor memory chip 12 in the X direction. The 2 nd member 29 may have a lower thermal conductivity than the sealing member 22 and a lower thermal conductivity than the 1 st member 23, for example.

In the case where the 2 nd component 29 has a lower thermal conductivity than the 1 st component 23, heat of the controller chip 11, which cannot be completely insulated by the 1 st component 23, can be suppressed from being transferred to other semiconductor chips. The heat insulation referred to herein is to make it more difficult to conduct the heat of the controller chip 11 to the semiconductor chip including the semiconductor memory chip 12 through the 1 st member 23 or the 2 nd member 29 than through the sealing member 22.

With these configurations, heat of the controller chip 11 is also difficult to be transmitted to the sealing member 22 due to the 1 st member 23 and the 2 nd member 29, and similarly, to other semiconductor chips including the semiconductor memory chip 12. Heat of the controller chip 11 is radiated toward the circuit board 2 through the mount film 24, the substrate 21, and the solder balls 25. Therefore, the influence of heat conduction to other semiconductor chips in the semiconductor package 1 such as the semiconductor memory chip 12 can be suppressed, and the function degradation due to heat can be prevented.

The sealing member 22, the 1 st member 23, and the 2 nd member 29 may be made of, for example, a phenol resin, an epoxy resin, PET (polyethylene terephthalate), carbon black (fine particles of carbon having a diameter of about 3 to 500 nm), silica (silicon dioxide), or a mixture thereof. By changing the mixing ratio, the content of a material having high thermal conductivity (for example, a metal such as carbon black or silica) can be reduced, and the thermal conductivity can be lowered.

In this embodiment, 1 or more semiconductor memory chips 12 may be stacked.

(embodiment 2)

Next, the structure of the semiconductor package 1 according to embodiment 2 will be described.

Fig. 6 is a cross-sectional view of the semiconductor package 1 of the present embodiment, and fig. 7 and 8 are plan views of the semiconductor package 1 of the present embodiment. In fig. 6 to 8, for convenience of explanation, the oscillator 14, the EEPROM15, and other parts of the semiconductor package 1 are omitted. The same parts as those of the semiconductor package 1 of embodiment 1 are denoted by the same reference numerals as those of the semiconductor package 1 of embodiment 2.

The semiconductor package 1 includes a substrate 21, a controller chip 11, a plurality of semiconductor memory chips 12, a sealing member 22, a 1 st member 23, a mounting film 24, and a plurality of solder balls 25.

The substrate 21 includes internal wiring 26 therein. The substrate 21 has a 1 st surface 21a and a 2 nd surface 21b located on the opposite side of the 1 st surface 21 a.

As shown in fig. 6 to 8, the semiconductor memory chips 12 provided on the 1 st surface 21a are stacked at 2. The 1 st memory chip group 12a and the 2 nd memory chip group 12b are provided, respectively. These memory chip groups are fixed to the 1 st surface 21a by a mount film 24, for example. For convenience of explanation, the semiconductor memory chip 12 closest to the substrate 21 in the Z direction among the plurality of semiconductor memory chips 12 constituting the 1 st memory chip group 12a is referred to as a memory chip 12aW, and the semiconductor memory chip 12 stacked on the memory chip 12aW is referred to as a memory chip 12 aV. Further, the semiconductor memory chip 12 stacked on the memory chip 12aV is referred to as a memory chip 12 aU. Among the plurality of semiconductor memory chips 12 constituting the 2 nd memory chip group 12b, the semiconductor memory chip 12 closest to the substrate 21 in the Z direction is referred to as a memory chip 12bW, and the semiconductor memory chip 12 stacked on the memory chip 12bW is referred to as a memory chip 12 bV. Further, the semiconductor memory chip 12 stacked on the memory chip 12bV is referred to as a memory chip 12 bU.

The controller chip 11 is provided on the 1 st surface 21a and is located between the memory chips 12aW and 12bW in the X direction. The controller chip 11 is fixed to the 1 st surface 21a by, for example, a mounting film 24. The controller chip 11 has electrode pads 28 and is electrically connected to the internal wiring 26 in the substrate 21 by, for example, wire bonding or flip chip bonding.

Fig. 7 is a diagram showing only the memory chips 12aW, 12bW closest to the substrate 21 in the Z direction among the stacked plurality of semiconductor memory chips 12. In the present embodiment, the controller chip 11 is mounted in the region B between the memory chip 12aW and the memory chip 12bW in the X direction. In fig. 7, the region B is a region surrounded by a one-dot chain line.

The distance between the components in the Z direction will be described with reference to fig. 6. The distance between the components in the Z direction is, for example, the minimum distance between the center point and the center point in the Z direction of each component (for example, the controller chip 11 and the memory chip 12) included in the semiconductor package 1. As shown in fig. 6, in the Z direction perpendicular to the substrate 21, the distances a between the memory chips 12aV, 12bV and the controller chip 11 are larger than the distances C between the memory chips 12aW, 12bW and the controller chip 11, respectively. In addition, in the Z direction perpendicular to the substrate 21, the distances H between the memory chips 12aU, 12bU and the controller chip 11 are larger than the distances a between the memory chips 12aV, 12bV and the controller chip 11, respectively.

Similarly, the distance between the components in the X direction will be described with reference to fig. 8. The distance between the components in the X direction is, for example, the minimum distance between the center point and the center point in the X direction of each component (for example, the controller chip 11 and the memory chip 12) included in the semiconductor package 1. Here, the center point of the memory chip 12aU is u, the center point of the memory chip 12aV is v, and the center point of the memory chip 12aW is w. Similarly, the center point of the memory chip 12bU is denoted by u ', the center point of the memory chip 12bV is denoted by v ', and the center point of the memory chip 12bW is denoted by w '. The distance E between the memory chip 12aV and the controller chip 11 is smaller than the distance D between the memory chip 12aW and the controller chip 11. The distance G between the memory chip 12bV and the controller chip 11 is smaller than the distance F between the memory chip 12bW and the controller chip 11. In addition, the distance I between the memory chip 12aU and the controller chip 11 is smaller than the distance E between the memory chip 12aV and the controller chip 11. The distance J between the memory chip 12bU and the controller chip 11 is smaller than the distance G between the memory chip 12bV and the controller chip 11.

In other words, the (i + 1) th semiconductor memory chip 12 is stacked on the i-th semiconductor memory chip 12 from the side closer to the substrate 21 among the at least n semiconductor memory chips 12 included in each of the memory chip groups 12a and 12 b. At this time, the i +1 th semiconductor memory chip 12 is stacked in a state where the distance from the controller chip 11 in the X direction is smaller than that of the i-th semiconductor memory chip 12. N is an integer of 2 or more, and i is an integer smaller than n.

As shown in fig. 8, when the semiconductor package 1 is viewed from the Z direction, at least a part of at least 1 semiconductor memory chip 12 constituting the memory chip groups 12a and 12B may overlap with the region B including the controller chip 11 in the X direction and the Y direction.

At least 1 or more semiconductor memory chips 12 constituting the memory chip groups 12a, 12b have electrode pads 27. For example, the semiconductor memory chips 12 are electrically connected to each other by wire bonding in which the wires 201 are connected to the electrode pads 27. At least 1 or more semiconductor memory chips 12 constituting the memory chip groups 12a, 12b are electrically connected to the internal wiring 26 in the substrate 21 via the electrode pad 27. The controller chip 11 has electrode pads 28, and is electrically connected to the internal wiring 26 by, for example, wire bonding or flip chip bonding. At least 1 or more semiconductor memory chips 12 constituting the memory chip groups 12a, 12b can be electrically connected to the controller chip 11 via the internal wiring 26.

The sealing member 22 is a member for sealing the controller chip 11 and the memory chip groups 12a and 12b on the substrate 21.

The mounting film 24 to which the controller chip 11 is fixed may have a higher thermal conductivity than the sealing member 22. In this case, the controller chip 11 functions to efficiently transfer heat to the substrate 21.

The 1 st member 23 is provided on the 1 st surface 21a, and covers at least a part of the periphery of the controller chip 11. The periphery here refers to a surface other than the surface where the controller chip 11 and the substrate 21 are in contact with each other. Also, the 1 st component 23 is located between the controller chip 11 and the semiconductor memory chip 12 in the X direction. The 1 st member 23 has lower thermal conductivity than the sealing member 22, and is difficult to transmit heat generated from the controller chip 11 to the semiconductor memory chip 12.

The substrate 21 includes a solder ball 25 on the 2 nd surface 21b, and can be electrically connected to the circuit board 2 of the electronic device via the solder ball 25.

According to the above configuration, heat of the controller chip 11 is hard to be transmitted to the sealing member 22 due to the 1 st member 23, and similarly, to other semiconductor chips such as the semiconductor memory chip 12. Heat of the controller chip 11 is radiated toward the circuit board 2 through the mount film 24, the substrate 21, and the solder balls 25. Therefore, the memory chip groups 12a and 12B having a structure in which at least a part of at least 1 semiconductor memory chip 12 overlaps with the region B including the controller chip 11 in the X direction and the Y direction when the semiconductor package 1 is viewed from the Z direction are less susceptible to heat. Therefore, the influence of heat conduction to other semiconductor chips in the semiconductor package 1 such as the semiconductor memory chip 12 can be suppressed, and the function degradation due to heat can be prevented.

(modification example)

As shown in fig. 9, the semiconductor package 1 according to the present embodiment may include a 2 nd member 29 between the 1 st member 23 and the sealing member 22.

(embodiment 3)

Next, the structure of the semiconductor package 1 according to embodiment 3 will be described.

Fig. 10, 11, 14, and 15 are sectional views of the semiconductor package 1 according to the present embodiment, and fig. 12, 13, and 16 are plan views of the semiconductor package 1 according to the present embodiment. In fig. 10 to 16, for convenience of explanation, the oscillator 14, the EEPROM15, and other parts of the semiconductor package 1 are omitted.

Regarding each part of the semiconductor package 1 of embodiment 3, the same parts as those of the semiconductor package 1 of embodiment 1 are denoted by the same reference numerals. As shown in fig. 10 to 16, the semiconductor package 1 of embodiment 3 differs from that of embodiment 1 in that: instead of the 1 st member 23 covering at least a part of the periphery of the controller chip 11, a wall member 31 is arranged between the semiconductor memory chip 12 and the controller chip 11.

Wall member 31 has a 1 st end 311, a 2 nd end 312, a 3 rd end 313, and a 4 th end 314. The end portion contacting the 1 st surface 21a of the substrate 21 is referred to as a 1 st end portion 311, and the end portion facing the 1 st end portion 311 is referred to as a 2 nd end portion 312. One of the end portions substantially perpendicular to the 1 st surface 21a is a 3 rd end portion 313, and the end portion opposite to the 3 rd end portion 313 is a 4 th end portion 314. The wall member 31 is a wall-shaped member provided for the purpose of preventing heat generated from the controller chip 11 from being transmitted to another semiconductor chip in the semiconductor package 1 via the sealing member 22.

As shown in fig. 10, the wall member 31 may extend in the Z direction as compared with the thickness of the controller chip 11 in the Z direction. Thus, the 2 nd end 312 may also be sealed by the sealing member 22 in the Z direction. As shown in fig. 11, the 2 nd end 312 may be exposed to the surface of the sealing member 22 in the Z direction.

Fig. 12 and 13 are views of the semiconductor package 1 of the present embodiment as viewed from the Z direction, and the sealing member 22 is omitted for convenience of explanation. The width of the wall member 31 in the Y direction may extend more than the width of the controller chip 11 in the Y direction. Therefore, as shown in fig. 12, the 3 rd end 313 and the 4 th end 314 may be sealed by the sealing member 22 in the Y direction. As shown in fig. 13, the 3 rd end portion 313 and the 4 th end portion 314 may be exposed to the surface of the sealing member 22 in the Y direction. The 3 rd end portion 313 and the 4 th end portion 314 may be exposed to the surface of the sealing member 22 in the Y direction, and one of them may be sealed by the sealing member 22.

The thermal conductivity of the wall member 31 is different from that of the sealing member 22. The wall member 31 may be made of, for example, phenol resin, epoxy resin, PET (polyethylene terephthalate), carbon black (fine particles of carbon having a diameter of about 3 to 500 nm), silica (silicon dioxide), or a mixture thereof. When the content of a material having high thermal conductivity (for example, metal such as carbon black or silica) is small, the thermal conductivity of the wall member 31 becomes lower than that of the sealing member 22. Since the wall member 31 has lower thermal conductivity than the sealing member 22, heat generated from the controller chip 11 is less likely to be transmitted to other semiconductor chips in the semiconductor package 1 including the semiconductor memory chip 12. Heat of the controller chip 11 is radiated toward the circuit board 2 through the mount film 24, the substrate 21, and the solder balls 25.

The wall member 31 may be made of a synthetic metal such as Al — Sic. At this time, the thermal conductivity of the wall member 31 is higher than that of the sealing member 22. After the heat generated from the controller chip 11 is transmitted to the wall member 31, the heat is radiated in the direction of the substrate 21 when the end portion other than the 1 st end portion 311 is sealed by the sealing member 22, and the heat is radiated in the direction of the substrate 21 and outside the semiconductor package 1 when the end portion other than the 1 st end portion 311 is exposed on the surface of the sealing member 22.

As described above, even when the thermal conductivity of the wall member 31 is higher or lower than that of the sealing member 22, the influence of heat conduction to other semiconductor chips in the semiconductor package 1 such as the semiconductor memory chip 12 can be suppressed, and the function degradation due to heat can be prevented.

As shown in fig. 14 to 16, in the semiconductor package 1 of the present embodiment, the 1 st member 23 may be provided around the controller chip 11 as in embodiment 1.

In the semiconductor package 1 of the present embodiment, the 2 nd member 29 may be provided between the 1 st member 23 and the sealing member 22 in the X direction, as in embodiment 1.

Several embodiments of the present invention have been described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.