阅读说明：本技术 半导体装置封装及其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由 凃顺财 林泓均 邱苡棠 吴怡君 于 2020-03-12 设计创作，主要内容包括：本公开提供了一种半导体装置封装,其包括衬底、重新分布结构、导电衬垫、导电元件和导电通孔。所述重新分布结构设置在所述衬底之上,并且包含第一电介质层与第一导电层。所述导电衬垫设置在所述第一电介质层的第一表面上。所述导电元件设置在所述第一电介质层中,且电连接到所述导电衬垫。所述导电通孔从所述导电衬垫穿过所述导电元件和所述第一电介质层向所述衬底延伸。所述第一导电层与所述导电通孔分离。(The present disclosure provides a semiconductor device package including a substrate, a redistribution structure, a conductive pad, a conductive element, and a conductive via. The redistribution structure is disposed over the substrate and includes a first dielectric layer and a first conductive layer. The conductive pad is disposed on a first surface of the first dielectric layer. The conductive element is disposed in the first dielectric layer and electrically connected to the conductive pad. The conductive via extends from the conductive pad through the conductive element and the first dielectric layer toward the substrate. The first conductive layer is separated from the conductive via.)

1. A semiconductor device package, comprising:

a substrate;

a redistribution structure disposed over the substrate and comprising a first dielectric layer and a first conductive layer;

a conductive pad disposed on a first surface of the first dielectric layer;

a conductive element disposed in the first dielectric layer and electrically connected to the conductive pad; and

a conductive via extending from the conductive pad through the conductive element and the first dielectric layer toward the substrate,

wherein the first conductive layer is separated from the conductive via.

2. The semiconductor device package of claim 1, wherein the first conductive layer directly contacts the conductive element.

3. The semiconductor device package of claim 1, wherein the conductive pad is separate from the conductive element.

4. The semiconductor device package of claim 1, wherein the first conductive layer comprises:

a first portion disposed substantially on the second surface of the first dielectric layer;

a third portion disposed at a higher elevation relative to the substrate than the first portion;

wherein the first portion and the third portion extend in a direction different from the conductive via.

5. The semiconductor device package of claim 4, wherein the first conductive layer further comprises:

a second portion extending in a direction substantially parallel to the conductive via, wherein the second portion connects the first portion and the third portion.

6. The semiconductor device package of claim 5, wherein the first conductive layer further comprises a seed layer that is substantially conformal with the first portion, the second portion, and the third portion.

7. The semiconductor device package of claim 1, wherein the conductive via is electrically connected with the first conductive layer through the conductive element.

8. The semiconductor device package of claim 1, wherein the conductive element surrounds a top of the conductive via.

9. The semiconductor device package of claim 1, further comprising a first seed layer disposed on the first surface of the first dielectric layer and a second surface of the conductive element; and

a second seed layer having a smooth contour of a side surface of the conductive via.

10. The semiconductor device package of claim 1, wherein the conductive via has a side surface that traverses a single material along a thickness of the redistribution structure.

11. The semiconductor device package of claim 1, wherein the first conductive element has a ring or ring-like structure.

12. The semiconductor device package of claim 1, wherein the redistribution structure further comprises:

a second dielectric layer disposed between the first dielectric layer and the substrate; and

a second conductive layer disposed in the first dielectric layer and the second dielectric layer and electrically connected to the conductive element;

wherein the conductive via extends through the second dielectric layer, an

Wherein the second conductive layer is separated from the conductive via.

13. The semiconductor device package of claim 12, further comprising:

a third dielectric layer disposed on the second dielectric layer and the substrate;

a third conductive layer disposed in the first, second, and third dielectric layers and electrically connected to the conductive elements;

wherein the conductive via extends through the third dielectric layer, an

Wherein the third conductive layer is separated from the conductive via.

14. A semiconductor device package, comprising:

a substrate;

a first dielectric layer disposed over the substrate and having a top surface, a bottom surface, and side surfaces;

a conductive element disposed in the first dielectric layer;

a first conductive layer disposed on the bottom surface and the side surfaces of the first dielectric layer and electrically connected with the conductive elements;

a conductive via disposed on the substrate; and

a second dielectric layer disposed between the first conductive layer and the conductive via;

wherein the second dielectric layer surrounds the conductive via, an

Wherein the first conductive layer has a portion extending along a bottom surface of the conductive element toward the conductive via.

15. The semiconductor device package of claim 14, further comprising a first conductive pad extending along the top surface of the first dielectric layer, wherein the first conductive pad is electrically connected to the conductive via and the conductive element.

16. The semiconductor device package of claim 14, wherein the conductive element has an inside surface in electrical contact with the conductive via and an outside surface in contact with the first dielectric layer.

17. The semiconductor device package of claim 14, further comprising:

a third dielectric layer disposed on the bottom surface of the first dielectric layer and having a bottom surface and side surfaces;

a fourth dielectric layer disposed between the second conductive layer and the conductive via; and

a second conductive layer disposed on the bottom surface and the side surfaces of the third dielectric layer,

wherein the second conductive layer extends through the second dielectric layer and is electrically connected to the conductive element, an

Wherein the fourth dielectric layer surrounds the conductive via.

18. A method of forming a semiconductor device package, the method comprising:

providing a vector;

forming a dielectric layer on the carrier;

forming a conductive element in the dielectric layer;

forming a conductive layer on the dielectric layer and a portion of the conductive element; and

forming a conductive via through the conductive element and the dielectric layer;

wherein the conductive layer and the conductive via directly contact the conductive element.

19. The method of claim 18, wherein forming a conductive via through the conductive element and the dielectric layer comprises:

by carbon dioxide CO₂Laser drilling an opening through the dielectric layer; and

filling the opening with a conductive material, wherein the opening has a continuous profile.

20. The method of claim 18, further comprising:

forming a first conductive pad on the dielectric layer, the conductive pad being electrically connected to the conductive via; and

attaching the dielectric layer to a substrate having a second electrically conductive pad, the first electrically conductive pad being electrically connected to the second electrically conductive pad.

Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same.

Background

The semiconductor device package may include a substrate and a redistribution structure attached to the substrate. The redistribution structure may include a dielectric layer and one or more conductive layers in the dielectric layer. To electrically connect the substrate and the redistribution structure, a laser drilling process may be performed followed by an electroplating process. The laser drilling penetrates the dielectric layer and the conductive layer of the redistribution structure.

Disclosure of Invention

According to some example embodiments of the present disclosure, a semiconductor device package includes a substrate, a redistribution structure, a conductive pad, a conductive element, and a conductive via. The redistribution structure is disposed over the substrate and includes a first dielectric layer and a first conductive layer. The conductive pad is disposed on a first surface of the first dielectric layer. The conductive element is disposed in the first dielectric layer and electrically connected to the conductive pad. The conductive via extends from the conductive pad through the conductive element and the first dielectric layer toward the substrate. The first conductive layer is separated from the conductive via.

According to some example embodiments of the present disclosure, a semiconductor device package includes a substrate, a first dielectric layer, a conductive element, a first conductive layer, a conductive via, and a second dielectric layer. The first dielectric layer has a top surface, a bottom surface, and side surfaces. The conductive element is disposed in the first dielectric layer. The first conductive layer is disposed on the bottom surface and the side surfaces of the first dielectric layer and electrically connected with the conductive elements. The conductive via is disposed on the substrate. A second dielectric layer is disposed between the first conductive layer and the conductive via. A second dielectric layer surrounds the conductive via.

According to some example embodiments of the present disclosure, a method of manufacturing a semiconductor device package includes: providing a vector; forming a dielectric layer on the carrier; forming a conductive element in the dielectric layer; forming a conductive layer on the dielectric layer and a portion of the conductive element; and forming a conductive via through the conductive element and the dielectric layer; wherein the conductive layer and the conductive via directly contact the conductive element.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a cross-sectional view of a semiconductor device package according to an embodiment.

Fig. 1B is a cross-sectional view of a semiconductor device package according to another embodiment.

Fig. 1C is a cross-sectional view of a semiconductor device package according to yet another embodiment.

Fig. 1D is a cross-sectional view of a semiconductor device package according to yet another embodiment.

Fig. 2A is a cross-sectional view of a semiconductor device package according to an embodiment.

Fig. 2B is a cross-sectional view of a semiconductor device package according to another embodiment.

Fig. 2C is a cross-sectional view of a semiconductor device package according to yet another embodiment.

Fig. 3A is a cross-sectional view of a semiconductor device package according to an embodiment.

Fig. 3B is a cross-sectional view of a semiconductor device package according to another embodiment.

Fig. 4A to 4U illustrate various stages of a method for manufacturing a semiconductor device package according to an embodiment.

Fig. 5A-5H illustrate various stages of a method for fabricating the semiconductor package assembly of fig. 1D.

Fig. 6A-6D illustrate various stages of a method for manufacturing the semiconductor device package of fig. 3A.

Fig. 6E illustrates a semiconductor device package fabricated in the method illustrated in fig. 6A-6D.

Fig. 7A-7D illustrate various stages of a method for manufacturing the semiconductor device package of fig. 3B.

Fig. 7E illustrates a semiconductor device package fabricated in the method illustrated in fig. 7A-7D.

Detailed Description

In a semiconductor package, a dielectric layer may be includedAnd a redistribution structure of the conductive layer in the dielectric layer is attached to the substrate. To electrically connect the substrate and the redistribution structure, a laser drilling process may be performed, e.g. CO₂Laser drilling followed by an electroplating process. In particular, the conductive layer may be designed with a via pad for electrical connection purposes. Then, CO₂The laser drilling penetrates the dielectric layer and the via liner of the conductive layer of the redistribution structure. Due to CO₂The laser via etches the dielectric material at a greater rate than the conductive material, and thus removes more dielectric material than conductive material. Thus, the dielectric layer on the walls of the drilled via tends to recess inward as compared to the via liner. During subsequent electroplating, the uneven or discontinuous profile on the walls of the drilled through holes can cause problems, such as poor adhesion between the plating material and the dielectric layer or through hole liner, resulting in cracking or delamination therebetween.

A semiconductor device package according to an embodiment of the present disclosure includes a substrate and a redistribution structure attached to the substrate. The redistribution structure includes a dielectric layer and a conductive layer in the dielectric layer. The conductive layer facilitates fan-out of signals from a first conductive pad on the substrate to a second conductive pad on the redistribution structure. The semiconductor device package also includes conductive elements and conductive vias. The conductive elements disposed in the redistribution structure are electrically connected between the second conductive pad and each of the conductive layers. The conductive via is electrically connected between the first and second conductive pads and electrically connected with the conductive element. However, the conductive via electrically connected to the conductive layer through the conductive element is separated from the conductive layer. Specifically, the conductive vias extend through the dielectric layer without physically contacting the conductive layer. With this design, during the manufacturing of the semiconductor device package, especially during the formation of the conductive vias by using a drilling process, only the dielectric layer is penetrated while drilling through the redistribution structure, and the conductive layer in the dielectric layer remains intact. In contrast, in some prior approaches, both the dielectric layer and the conductive layer in the redistribution structure are penetrated, resulting in an uneven distribution or even a discontinuous connection between the conductive layers on the walls of the drilled through holes. The semiconductor device package according to the present disclosure solves this problem.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, in the following description, references to forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Fig. 1A is a cross-sectional view of a semiconductor device package 100A according to an embodiment.

Referring to fig. 1A, a semiconductor device package 100A includes a substrate 10, a redistribution structure 50, a conductive pad 14, a conductive via 15, and a conductive element 17.

The substrate 10 includes a conductive pad 10c on its surface 10 s. An adhesive layer 10a is disposed between the substrate 10 and the redistribution structure 50. The conductive pad 10c is embedded in the adhesive layer 10 a.

The redistribution structure 50 comprises a first dielectric layer 11, a second dielectric layer 12 and a third dielectric layer 13. The first dielectric layer 11 is disposed on the second dielectric layer 12, the second dielectric layer 12 is disposed on the third dielectric layer 13, and the third dielectric layer 13 is disposed on the adhesive layer 10a over the substrate 10. Specifically, the first dielectric layer 11 has a first surface 111 and a second surface 112 opposite to the first surface 111. The second dielectric layer 12 is disposed on the second surface 112. The second dielectric layer 12 has a surface 121 facing the conductive pad 10 c. The third dielectric layer 13 is disposed on the surface 121 of the second dielectric layer 12. The third dielectric layer 13 has a surface 131 facing the conductive pad 10 c. The adhesive layer 10a is disposed on the surface 131 of the third dielectric layer 13.

In an embodiment, the first dielectric layer 11 may include borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, Undoped Silicate Glass (USG), any combination thereof, and the like. Suitable materials for the second and third dielectric layers 12, 13 may be similar or identical to the material of the first dielectric layer 11 and will therefore not be discussed further.

The redistribution structure 50 further comprises a conductive layer 16a disposed in the dielectric layer 11. The first conductive layer 16a directly contacts the conductive element 17, and the conductive element 17 in turn directly contacts the conductive via 15. However, the first conductive layer 16a is separated from the conductive via 15. Suitable materials for the first conductive layer 16a may include, but are not limited to, nickel, copper, gold, titanium, tungsten, or platinum.

The first conductive layer 16a includes first, second and third portions 16a1, 16a2 and 16a 3. The first portion 16a1 substantially disposed on the second surface 112 extends in a direction different from the conductive via 15 extending in the first direction. The third portion 16a3, which is disposed at a height higher than the first portion 16a1 with respect to the substrate 10, also extends in a direction different from the first direction. The second portion 16a2 extends in a direction substantially parallel to the first direction. Second portion 16a2 connects first portion 16a1 and third portion 16a 3. First conductive layer 16a further includes seed layer 16s1 that is substantially conformal with first portion 16a1, second portion 16a2, and third portion 16a 3. A portion of seed layer 16s1 disposed on third portion 16a3 directly contacts first surface 17s2 of conductive element 17 and electrically connects first conductive layer 16a to conductive element 17.

The conductive pads 14 are disposed on the first surface 111 of the first dielectric layer 11. The conductive pad 14 is electrically connected to and disposed on the conductive via 15. Also, the conductive pad 14 is electrically connected to and disposed on a second surface 17s1 (e.g., a top surface) of the conductive element 17. Furthermore, the conductive pad 14 may cover the conductive element 17. The conductive pad 14 comprises a seed layer 14s on the first surface 111 of the first dielectric layer 11 and the second surface 17s1 of the conductive element 17. The material of the conductive pad 14 may include, but is not limited to, nickel, copper, gold, titanium, tungsten, or platinum. In some embodiments, conductive pad 14 may exclude seed layer 14s, provided conductive pad 14 is formed by electroless plating.

The conductive vias 15 are electrically connected to conductive elements 17, the conductive elements 17 being disposed in the first dielectric layer 11 of the redistribution structure 50. The conductive via 15 extends from the conductive pad 14 through the conductive element 17 and the redistribution structure 50 to the conductive pad 10c of the substrate 10. Specifically, the conductive via 15 extends through the first, second, and third dielectric layers 11, 12, and 13. The top of the conductive via 15 is surrounded by the conductive element 17 and the rest of the conductive via 15 is surrounded by the redistribution structure 50.

In the examples, by CO₂Laser drilling forms openings through the redistribution structure, which may then be filled with a conductive material to form conductive vias 15. The diameter of the opening is determined by the hollow structure defined by the conductive element 17. In CO₂In laser drilling, openings are formed by penetrating or drilling through a single material (e.g., a dielectric material) in the redistribution structure 50. The drilling through the single material (e.g., dielectric material) in the redistribution structure 50 provides an opening having a continuous profile that subsequently provides a continuous profile along the side surface 15a of the conductive via 15. For example, a continuous profile may comprise a substantially linear profile (e.g., a smooth profile). Advantageously, the continuous profile of the side surface 15a prevents gaps between the conductive vias 15 and the redistribution structure 50. Accordingly, the seed layer 15 of the conductive via 15, which is subsequently formed by, for example, a sputtering process, may have a smooth profile of the side surface 15a and may have a relatively strong adhesion to a single material (dielectric material) in the redistribution structure 50. Advantageously, the well-formed seed layer prevents electromigration between the conductive via 15 and the redistribution structure 50. In some embodiments, the conductive via 15 may exclude the seed layer 15s, provided that the conductive via 15 is formed by electroless plating.

In terms of electrical connection, the conductive member 17 is used to electrically connect the first conductive layer 16a to the conductive via 15, assuming that the first conductive layer 16a is separated from the conductive via 15. Conductive vias 15 are used to electrically connect redistribution layer 50 to substrate 10. In particular, the first conductive layer 16a of the redistribution layer 50 is electrically connected to the conductive pad 10c of the substrate 10 via the conductive element 17 and the conductive via 15.

In some embodiments, the conductive element 17 may have a ring or ring-like structure. In some embodiments, the conductive element 17 may have a horseshoe-like structure. In some embodiments, the conductive element 17 may have a hollow structure.

The material of the conductive via 15 may include, but is not limited to, nickel, copper, gold, titanium, tungsten, or platinum. Also, the conductive element 17 may comprise a single layer or a multi-layer structure. The material of the conductive element 17 may include, but is not limited to, nickel, copper, gold, titanium, tungsten, or platinum.

Fig. 1B is a cross-sectional view of a semiconductor device package 100A' according to another embodiment. Referring to fig. 1B, a semiconductor device package 100A 'is similar to the semiconductor device package 100A in fig. 1A except, for example, the redistribution structure 50' further includes a second conductive layer 16B and a third conductive layer 16 c.

The second conductive layer 16b is disposed in the first and second dielectric layers 11, 12. The second conductive layer 16b directly contacts the conductive element 17, and the conductive element 17 in turn directly contacts the conductive via 15. However, the second conductive layer 16b is separated from the conductive via 15. In addition, the second conductive layer 16b is separated from the first conductive layer 16 a. The second conductive layer 16b is disposed between the conductive via 15 and the first conductive layer 16a, and is thus positioned closer to the conductive via 15 than the first conductive layer 16 a. Suitable materials for the second conductive layer 16b may include, but are not limited to, nickel, copper, gold, titanium, tungsten, or platinum.

The second conductive layer 16b includes first, second and third portions 16b1, 16b2 and 16b 3. The first portion 16b1, which is substantially disposed on the surface 121 of the second dielectric layer 12, extends in a direction different from the conductive via 15 extending in the first direction. The third portion 16b3, which is disposed at a height higher than the first portion 16b1 with respect to the substrate 10, also extends in a direction different from the first direction. The second portion 16b2 extends in a direction substantially parallel to the first direction. Second portion 16b2 connects first portion 16b1 and third portion 16b 3. Second conductive layer 16b further includes seed layer 16s2 that is substantially conformal with first portion 16b1, second portion 16b2, and third portion 16b 3. A portion of seed layer 16s2 disposed on third portion 16b3 directly contacts first surface 17s2 of conductive element 17 and electrically connects second conductive layer 16b to conductive element 17. The length of portion 16b2 in the second direction is greater than the length of second portion 16a 2.

The third conductive layer 16c is disposed in the first, second and third dielectric layers 11, 12 and 13. The third conductive layer 16c directly contacts the conductive element 17, and the conductive element 17 in turn directly contacts the conductive via 15. However, the third conductive layer 16c is separated from the conductive via 15. Further, the third conductive layer 16c is separated from the first conductive layer 16a and the second conductive layer 16 b. The third conductive layer 16c is disposed between the conductive via 15 and the second conductive layer 16b, and is thus positioned closer to the conductive via 15 than the first and second conductive layers 16a and 16 b. Suitable materials for the third conductive layer 16c may include, but are not limited to, nickel, copper, gold, titanium, tungsten, or platinum.

The third conductive layer 16c includes first, second and third portions 16c1, 16c2 and 16c 3. The first portion 16c1, which is disposed substantially above the surface 131 of the second dielectric layer, extends in a direction different from the conductive via 15 extending in the first direction. The third portion 16c3, which is disposed at a height higher than the first portion 16c1 with respect to the substrate 10, also extends in a direction different from the first direction. The second portion 16c2 extends in a direction substantially parallel to the first direction. Second portion 16c2 connects first portion 16c1 and third portion 16c 3. Third conductive layer 16c further includes seed layer 16s3 that is substantially conformal with first portion 16c1, second portion 16c2, and third portion 16c 3. A portion of seed layer 16s3 disposed on third portion 16c3 directly contacts first surface 17s2 of conductive element 17 and electrically connects third conductive layer 16c to conductive element 17. The length of portion 16c2 in the second direction is greater than the length of second portion 16b 2.

In terms of electrical connection, the conductive member 17 is used to electrically connect the second conductive layer 16b to the conductive via 15, assuming that the second conductive layer 16b is separated from the conductive via 15. The conductive member 17 is used to electrically connect the third conductive layer 16c to the conductive via 15, provided that the third conductive layer 16c is separated from the conductive via 15.

Fig. 1C is a cross-sectional view of a semiconductor device package 100A' according to yet another embodiment. Referring to fig. 1C, a semiconductor device package 100A ″ is similar to the semiconductor device package 100A' in fig. 1B except, for example, each of the conductive layers 16a, 16B, and 16C does not surround the conductive via 15. Specifically, the first conductive layer 16a and the second conductive layer 16b are located on one side (left side in the present embodiment) of the conductive through hole 15, and the third conductive layer 16c is located on the other side (right side) of the conductive through hole 15. It should be appreciated that the first, second and third conductive layers 16a, 16b and 16c may have different arrangements depending on the circuitry in the redistribution structure 50 ".

Fig. 1D is a cross-sectional view of a semiconductor package assembly 200a according to an embodiment.

As shown in fig. 1D, semiconductor package assembly 200a includes a plurality of semiconductor device packages, substrate 10, redistribution structure 60, semiconductor devices 20 and 20', connection elements 21 and 23, insulator 23, and carrier 24. The semiconductor devices 20 and 20' are attached to the redistribution structure 60 by connection elements 21. As shown in fig. 1D, the semiconductor package assembly 200a includes different semiconductor device packages. Some semiconductor device packages have multiple conductive layers, such as semiconductor device package 100A' shown in fig. 1B, while other semiconductor device packages have a single conductive layer, such as semiconductor device package 100A shown in fig. 1A. In the present embodiment, the semiconductor device 20 is attached to a semiconductor device package having a plurality of conductive layers in the redistribution structure 60 via the connection element 21. The plurality of conductive layers may include at least two of the first, second, and third conductive layers 16a, 16b, and 16 c. Furthermore, the semiconductor device 20' is attached to a semiconductor device package having a single conductive layer in the redistribution structure 60 via the connection element 21. The single conductive layer may comprise only one of the first, second or third conductive layers 16a, 16b and 16 c. In other embodiments, the redistribution structure 60 of the semiconductor package assembly 200a may include more than three conductive layers.

The substrate 10 includes a plurality of interconnect structures 101 connecting the semiconductor device package 100A' and the connection elements 23, the interconnect structures 101 in turn being connected with a carrier 24, such as a Printed Circuit Board (PCB). The connection elements 21 and 23 may each comprise, for example, but not limited to, solder, adhesive, or other suitable bonding material. The insulator 22 is disposed between the semiconductor device package 100A' and the semiconductor device 20. In some embodiments, suitable materials for the insulator 22 may include molding material, such as epoxy molding material (EMC).

Fig. 2A is a cross-sectional view of a semiconductor device package 100B, according to some embodiments of the present disclosure. Referring to fig. 2A, a semiconductor device package 100B includes a substrate 10, dielectric layers 11, 11', 12, and 13, a conductive pad 14, a conductive via 15, a conductive layer 16a, and a conductive element 17. For the materials of the components (e.g., substrate, dielectric layers, conductive vias, and conductive layers) in the semiconductor device package 100B, reference is made to the corresponding components described and illustrated with respect to fig. 1A.

Dielectric layer 11 has a top surface 111, a bottom surface 112 and side surfaces 113. The conductive element 17 is disposed below the top surface 111. The first conductive layer 16a is disposed on the bottom surface 112 and the side surface 113. The first conductive layer 16a is disposed on the first surface 17s2 of the conductive element 17. The first conductive layer 16a includes portions 16a1, 16a2, and 16a 3. The portion 16a1 is disposed on the bottom surface 112. The portion 16a2 is provided on the side surface 113. The portion 16a3 is disposed on the conductive element 17.

The dielectric layer 11' is disposed between the conductive via 15 and the conductive layer 16a and on the conductive element 17. In an embodiment, the dielectric layer 11' may surround a portion of the conductive via 15 between the conductive element 17 and the dielectric layer 12.

The conductive pads 14 extend along the top surface 111. The conductive pad 14 is electrically connected to the conductive via 15 and the conductive element 17. Conductive vias 15 extend through the dielectric layers 11', 12 and 13. The conductive via 15 is surrounded by dielectric layers 11', 12 and 13. The top of the conductive via 15 is surrounded by a conductive element 17.

The conductive member 17 has an inner side surface 17s3 directly contacting the conductive via 15. The conductive element 17 has an outer side surface 17s4 that directly contacts the first dielectric layer 11. The conductive layer 16a is electrically connected to the conductive via 15 and the conductive element 17 via the conductive element 17.

Fig. 2B is a cross-sectional view of a semiconductor device package 100B' according to some embodiments of the present disclosure. Referring to fig. 2B, a semiconductor device package 100B' is similar to the semiconductor device package 100B in fig. 2A except, for example, a second conductive layer 16B disposed on the bottom surface 122 and the side surface 123 of the dielectric layer 12. The second conductive layer 16b extends through the dielectric layer 11'. The second conductive layer 16b is electrically connected to the conductive member 17. A dielectric layer 12' is disposed between the conductive via 15 and the second conductive layer 16 b. A dielectric layer 12 'is disposed on the dielectric layer 11'. Conductive vias 15 extend through the dielectric layers 11', 12', and 13. The conductive via 15 is surrounded by a dielectric layer 11', 12' or 13.

Fig. 2C is a cross-sectional view of a semiconductor device package 100B "according to some embodiments of the present disclosure. Referring to fig. 2C, a semiconductor device package 100B ″ is similar to the semiconductor device package 100B in fig. 2A except, for example, a conductive layer 16C disposed on the bottom surface 132 and the side surface 133 of the dielectric layer 13. The conductive layer 16c extends through the dielectric layers 11 'and 12'. The conductive layer 16c is electrically connected to the conductive member 17.

The dielectric layer 12' is disposed between the conductive via 15 and the conductive layer 16 c. A dielectric layer 13 'is disposed on the dielectric layer 12'. The conductive vias 15 extend through the dielectric layers 11', 12' and 13 '. The conductive via 15 is surrounded by a dielectric layer 11', 12' or 13 '.

Fig. 3A is a cross-sectional view of a semiconductor device package 100C according to yet another embodiment. Referring to fig. 3A, a semiconductor device package 100C includes a substrate 10, a conductive pad 14, a conductive via 15, a conductive element 17, and a redistribution structure 51 including first, second, and third dielectric layers 11, 12, 13 and conductive layers 16C', 18a, and 18 b. For the materials of the components (e.g., substrate, dielectric layers, conductive vias, and conductive layers) in the semiconductor device package 100C, reference is made to the respective components described with respect to fig. 1A.

The first dielectric layer 11 has a surface 111 and a surface 112 opposite the surface 111. A second dielectric layer 12 having a surface 121 is disposed on the surface 112. A third dielectric layer 13 having a surface 131 is disposed on the surface 121 of the second dielectric layer 12. The adhesive layer 10a is disposed on the surface 131 of the third dielectric layer 13. The substrate 10 is attached to the third dielectric layer 13 via an adhesive layer 10 a.

The conductive layer 18a is disposed in the first dielectric layer 11 and is separated from the conductive via 15. The conductive layer 18b is disposed in the second dielectric layer 12 and is separated from the conductive via 15.

A conductive pad 14 is disposed on a surface 111 of the first dielectric layer 11. The conductive pad 14 is electrically connected to and disposed on the conductive via 15. The conductive pad 14 comprises a seed layer 14s on the first surface 111 of the first dielectric layer.

The conductive vias 15 are electrically connected to the conductive elements 17 disposed in the first and second dielectric layers 11, 12 of the redistribution structure 50. The conductive via 15 extends from the conductive pad 14 through the conductive element 17 and the redistribution structure 50 to the conductive pad 10c of the substrate 10. Specifically, the conductive via 15 extends through the first, second, and third dielectric layers 11, 12, and 13. The top of the conductive via 15 is surrounded by the conductive element 17 and the rest of the conductive via 15 is surrounded by the redistribution structure 50. In contrast to the semiconductor device package 100A in fig. 1A, the conductive pad 14 in fig. 3A, the conductive element 17 is separated from the conductive pad 14. The conductive element 17 is electrically connected to the conductive via 15. The conductive element 17 extends along the surface 112. The conductive element 17 includes a seed layer 17s that is substantially conformal to the conductive element 17 and the protrusions 171 of the conductive element 17. The protrusion 171 abuts and is electrically connected to the conductive layer 18 a. Assuming that the conductive layer 18a is separated from the conductive via 15, the conductive element 17 provides the conductive layer 18a with an electrical connection to the conductive via 15.

A conductive layer 16c' is disposed in the dielectric layers 12 and 13. Conductive layer 16c' is separate from conductive via 15, but is electrically connected to conductive element 17. Conductive layer 16c 'includes portions 16c1', 16c2', and 16c 3'. The first portion 16c1' disposed substantially above the surface 131 of the second dielectric layer extends in a direction different from the conductive via 15 extending in the first direction. The third portion 16c3', which is disposed at a higher level than the first portion 16c1' with respect to the substrate 10, also extends in a direction different from the first direction. The second portion 16c2' extends in a direction substantially parallel to the first direction. Second portion 16c2' connects first portion 16c1' and third portion 16c3 '.

The conductive layer 16c is electrically connected to the conductive via 15 via the conductive member 17. The conductive member 17 is used to electrically connect the conductive layers 18a and 16c to the conductive via 15 when the conductive layers 18a and 16c are separated from the conductive via 15.

In the examples, by CO₂Laser drilling forms openings through the distribution structure, which are then filled with a conductive material to form conductive vias 15. The diameter of the opening is determined by the hollow structure defined by the conductive element 17. In CO₂In laser drilling, the openings are formed by penetrating or drilling through a single material (e.g., a dielectric material) in the redistribution structure 51. The drilling through the single material (e.g., dielectric material) in the redistribution structure 51 provides an opening having a continuous profile that subsequently provides a continuous profile along the side surface 15a of the conductive via 15. For example, a continuous profile may comprise a substantially linear profile (e.g., a smooth profile). Advantageously, the continuous profile of the side surface 15a prevents gaps between the conductive vias 15 and the redistribution structure 51. Accordingly, the seed layer 15s, which is subsequently formed by, for example, a sputtering process, may have a smooth profile of the side surface 15a and may have a relatively strong adhesion to a single material (dielectric material) in the redistribution structure 51. Advantageously, the well-formed seed layer prevents electromigration between the conductive via 15 and the redistribution structure 51.

Fig. 3B is a cross-sectional view of a semiconductor device package 100D according to another embodiment. Referring to fig. 3B, the semiconductor device package 100D is similar to the semiconductor device package 100C of fig. 3A, except for example: conductive element 17 is disposed on surface 121 and redistribution structure 51 further comprises conductive layers 18b1 and b2 between conductive layer 18a and conductive element 17, while conductive layer 16c' is omitted. Conductive layer 18b1 is electrically connected to conductive layer 18 a. The seed layer 17s is substantially conformal with the conductive element 17 and the protrusions 171 and 172 of the conductive element 17. The conductive layers 18b1 and 18b2 are electrically connected to the conductive element 17 via the protrusions 171 and 172, respectively.

Fig. 4A-4U illustrate various stages of a method for fabricating a semiconductor device package, according to some embodiments of the present disclosure.

Referring to fig. 4A, a carrier 40 is provided. Carrier 40 is used to support semiconductor components, devices or structures to be subsequently formed thereon. In an embodiment, carrier 40 comprises a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate.

Subsequently, a seed layer 41 is formed on the support 40 in, for example, a Physical Vapor Deposition (PVD) process. The seed layer 41 is used to provide a barrier layer between the metallic material and the dielectric material.

Referring to fig. 4B, a patterned first dielectric layer 110 is formed on the seed layer 41 by using, for example, a coating process and a subsequent photolithography process. The patterned first dielectric layer 110 includes island regions 11a and exposes a portion of the seed layer 41 not covered by the island regions 11 a.

Referring to fig. 4C, a first conductive layer 17 is formed on the exposed portion of the seed layer 41 by, for example, an electroplating process. The first conductive layer 17 is lower than the patterned first dielectric layer 110. As shown in fig. 1A, the conductive layer 17 serves as the conductive member 17, and is therefore hereinafter referred to as the conductive member 17.

Referring to fig. 4D, another patterned dielectric layer 110' is formed on the patterned first dielectric layer 110 except the island region 11a to increase the total thickness of the first patterned dielectric layer 110. Next, seed layer 16s1 is formed on first dielectric layer 110, electrically conductive layer 17, and island region 11a in, for example, a PVD process.

Referring to fig. 4E, a photoresist PR is formed over the conductive elements 17 and the island regions 11a through, for example, a coating process and a subsequent exposure process. Referring to fig. 4F, a conductive layer 160a is formed on seed layer 16s1 exposed from photoresist PR. As shown in fig. 1A, conductive layer 160a and seed layer 16s1 are collectively denoted as first conductive layer 16 a.

Referring to fig. 4G, photoresist PR is removed by, for example, a plasma ashing process, exposing a portion of seed layer 16s1 not covered by conductive layer 160 a. Referring to fig. 4H, the exposed areas of seed layer 16s1 are removed by, for example, a wet clean process. Then, the first region of the conductive element 17 having the radius R1 and the island region 11a are exposed.

Further, the angular relationship between the first patterned dielectric layer 110 and the first conductive layer 16a may be determined for ease of manufacturing. Specifically, the bottom surface of the first patterned dielectric layer 110 and the side surface of the first conductive layer 16a define an angle Θ. The angle Θ may exceed 47 °. The angle Θ may exceed 65 °. The angle Θ may exceed 73 °. The angle Θ may exceed 77. The angle Θ may exceed 79 °. The angle Θ may be in the range of 81 ° to 91 °. Angle Θ may prevent a discontinuous profile of electroplating material in the PVD process of seed layer 16s 1.

Referring to fig. 4I, a patterned second dielectric layer 120 is formed over the first conductive layer 16a and a portion of the conductive element 17 using, for example, a coating process followed by a photolithography process. Next, seed layer 16s2 is formed on patterned second dielectric layer 120, conductive elements 17, and island regions 11a in, for example, a PVD process.

Referring to fig. 4J, a photoresist PR is formed over the conductive elements 17 and the island regions 11a through, for example, a coating process and a subsequent exposure process. Referring to fig. 4K, a conductive layer 160b is formed on seed layer 16s2 exposed from photoresist PR. As shown in fig. 1B, conductive layer 160B and seed layer 16s2 are collectively denoted as second conductive layer 16B.

Referring to fig. 4L, the photoresist is removed by, for example, a plasma ashing process, exposing a portion of seed layer 16s2 not covered by conductive layer 160 a. Next, the exposed areas of seed layer 16s2 are removed by, for example, a wet clean process. Then, the second region of the conductive element 17 having the radius R2 and the island region 11a are exposed.

Referring to fig. 4M, a patterned third dielectric layer 130 is formed on the second conductive layer 16b and a portion of the conductive element 17 by using, for example, a coating process and a subsequent photolithography process. Next, seed layer 16s3 is formed on patterned third dielectric layer 130, conductive layer 17, and island region 11a in, for example, a PVD process.

Referring to fig. 4N, a photoresist PR is formed over the conductive elements 17 and the island regions 11a through, for example, a coating process and a subsequent exposure process. Referring to fig. 4O, a conductive layer 160c is formed on seed layer 16s3 exposed from photoresist PR. As shown in fig. 1B, conductive layer 160c and seed layer 16s3 are collectively denoted as third conductive layer 16 c.

Referring to fig. 4P, the photoresist is removed by, for example, a plasma ashing process, exposing a portion of seed layer 16s1 not covered by conductive layer 160 a. Next, the exposed areas of seed layer 16s3 are removed by, for example, a wet clean process. Then, the third region of the conductive element 17 having the radius R3 and the island region 11a are exposed. In an embodiment, radius D1 is greater than radius D2 and radius D2 is greater than radius D3.

Referring to fig. 4Q, a dielectric layer 42 is formed on the third conductive layer 16c, the conductive elements 17, and the island regions 11a by using, for example, a coating process and a subsequent grinding process. As shown in FIG. 1A, the bottom of the first patterned dielectric layer 110, the bottom of the second patterned dielectric layer 120, the bottom of the third patterned dielectric layer 130, and the bottom of the dielectric layer 42 are collectively referred to as a first dielectric layer 11. As shown in fig. 1A, the top of the second dielectric layer 120, the middle of the third dielectric layer 130, and the middle of the dielectric layer 42 are collectively denoted as the second dielectric layer 12. As shown in fig. 1A, the top of the third dielectric layer 130 and the top of the dielectric layer 42 are collectively denoted as a third dielectric layer 13.

Referring to fig. 4R, the substrate 10 is provided, and then the substrate 10 is attached to the third dielectric layer 13 through the adhesive layer 10 a. The substrate 10 includes a conductive pad 10 c. Referring to fig. 4S, the carrier 40 and the seed layer 41 are removed.

Referring to FIG. 4T, by way of example CO₂Laser drilling forms an opening 43 through island 11a, first, second and third dielectric layers 11, 12 and 13 and terminating on conductive pad 10 c. CO 2₂The laser etches the conductive elements 17 at a relatively low rate, and thus the conductive elements 17 can be a hard mask in laser drilling. In laser drilling, the opening 43 is provided with a continuous profile using the conductive element 17 as a hard mask. In addition, the opening 43 having a relatively small diameter is provided using the conductive member 17 as a hard mask. The opening 43 having a relatively small diameter provides a relatively large footprint for the circuitry embedded in the first, second or third dielectric layers 11, 12 or 13And (4) counting a window.

Referring to fig. 4U, in, for example, a PVD process, a seed layer 15s is formed to form a profile of the opening 43. A seed layer 14s is formed on the conductive element 17 in, for example, a PVD process. Seed layer 15s and seed layer 14s may be formed simultaneously. Then, in, for example, an electroplating process, the conductive pad 14 is formed on the seed layer 14 s. A conductive via 15 is formed on the seed layer 15s by, for example, an electroplating process, filling the opening. In an embodiment, the conductive via 15 and the conductive pad 14 may be formed by electroplating copper, silver, nickel, gold, or a suitable metal. In some embodiments, conductive pad 14 may be formed directly on conductive element 17 without seed layer 14s by, for example, electroless plating. In some embodiments, conductive vias 15 may be formed directly in openings 43 without seed layer 15 by, for example, electroless plating.

Fig. 5A-5G illustrate various stages of a method for manufacturing the semiconductor package assembly 200A of fig. 1D.

Referring to fig. 5A, a substrate 10 is provided. The substrate 10 includes a plurality of interconnect structures 101 and a plurality of conductive pads 10C. The adhesive layer 10a is provided on the substrate 10.

Referring to fig. 5B, a redistribution structure 60 attached on a carrier 40 via a seed layer 41 is provided. The redistribution structure 60 is attached to the substrate 10 via the adhesive layer 10a by using, for example, a Flip Chip Bonding (FCB) process. Redistribution structure 60 comprises a variation of the structure shown in fig. 4Q. Referring to fig. 5C, the carrier 40 and the seed layer 41 are removed.

Referring to FIG. 5D, by using, for example, CO₂The laser drilling process forms a plurality of openings 43. In CO₂During the laser drilling process, the conductive elements 17 act as a hard mask and the conductive layers (e.g., first, second, and third conductive layers) remain free of CO₂The influence of the laser. Therefore, assuming that the layout in the redistribution structure 60 in each region is different, the shape of each of the plurality of openings 43 is substantially the same. Advantageously, the setup of the recipe for the laser drilling process may be simplified and the throughput of the laser drilling process may be increased.

Referring to fig. 5E, a conductive structure 70 is disposed in the opening and surface of the redistribution structure 60. The conductive structure 70 includes a seed layer 70 s. Referring to fig. 5F, a photoresist PR is formed on the conductive structure 70 through, for example, a coating process and a subsequent exposure process. Referring to fig. 5G, the exposed regions of the conductive structure 70 are removed by, for example, a wet etching process. As a result, a plurality of conductive pads 14 and a plurality of conductive vias 15 are defined. Referring to fig. 5H, the photoresist PR is removed through, for example, a plasma ashing process.

One or more semiconductor devices may then be attached to the conductive pads 14 by a plurality of connection elements (e.g., solder). Further, another plurality of connection elements may be provided on the substrate 10 to form the semiconductor device package 100D described and illustrated with reference to fig. 1D.

Fig. 6A-6D illustrate various stages of a method for manufacturing the semiconductor device package 100C of fig. 3A.

Referring to fig. 6A, a carrier 40 is provided. A seed layer 41 is formed on the carrier 40. A dielectric layer is formed on the seed layer 41. A conductive layer 18a is disposed on the dielectric layer. Another dielectric layer is formed over conductive layer 18a and patterned to form trench t1, exposing a portion of conductive layer 18 a. These two dielectric layers are collectively referred to as dielectric layer 11.

Referring to fig. 6B, conductive elements 17 are formed on the dielectric layer 11. The conductive member 17 includes a protrusion 171 formed in the groove t 1. A patterned dielectric layer 12 is formed over dielectric layer 11 and a portion of conductive element 17.

Referring to fig. 6C, a dielectric layer is formed on the surface 121 of the dielectric layer 12. In a similar manner to that shown in fig. 4C to 4H, a conductive layer 16C' is formed on the dielectric layer. The conductive layer 16c contacts the conductive member 17. Next, another dielectric layer is formed to cover the conductive element 17 and the conductive layer 16 c'.

Referring to fig. 6D, the conductive pad 14 and the conductive via 15 are formed in a series of processes similar to those shown in fig. 4R to 4U.

Fig. 6E illustrates the semiconductor package assembly 200b manufactured in the method illustrated in fig. 6A to 6D. The semiconductor package assembly 200b includes the redistribution structure 70 and the substrate 10, the redistribution structure 70 and the substrate 10 including variations of the semiconductor device package 100C of fig. 3A.

Fig. 7A-7D illustrate various stages of a method for manufacturing the semiconductor device package 100D of fig. 3B.

Referring to fig. 7A, a carrier 40 is provided. A seed layer 41 is formed on the carrier 40. A dielectric layer is formed on the seed layer 41. A conductive layer 18a is formed on the dielectric layer. Another dielectric layer is formed over conductive layer 18a and patterned to form trench t2, exposing a portion of conductive layer 18 a. These two dielectric layers are collectively referred to as dielectric layer 11.

Referring to fig. 7B, a dielectric layer 12 is formed on the dielectric layer 11. Conductive layers 18b1 and 18b2 are formed in dielectric layer 12. A conductive layer 18b1 is formed in the trench t 1. Conductive layer 18b1 directly contacts conductive layer 18 a. Dielectric layer 12 is patterned to form trench t2 to expose conductive layer 18b 1. Dielectric layer 12 is patterned to form trench t3 to expose conductive layer 18b 2.

Referring to fig. 7C, conductive elements 17 are formed on the dielectric layer 12. Conductive element 17 includes protrusion 171 in trench t2 to contact conductive layer 18b 1. Conductive element 17 includes a protrusion 172 in trench t3 to contact conductive layer 18b 2. Next, the dielectric layer 13 is formed on the conductive element 17 and the dielectric layer 12.

Referring to fig. 7D, the conductive pad 14 and the conductive via 15 are formed in a series of processes similar to those shown in fig. 4R to 4U.

Fig. 7E illustrates a semiconductor package assembly 200c manufactured in the method illustrated in fig. 7A through 7D. The semiconductor device package 200c of fig. 7E includes the redistribution structure 80 and the substrate 10, the redistribution structure 80 and the substrate 10 including a variation of the semiconductor device package 100D of fig. 3B.

Spatial descriptions, such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "above," "below," and the like, unless otherwise specified, are indicated with respect to the orientation shown in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner provided that such arrangements still retain the advantages of the embodiments of the present disclosure.

As used herein, the terms "about," "substantially," "essentially," and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or environment, the terms may refer to the exact occurrence of the event or environment and the approximate occurrence of the event or environment. For example, when used in conjunction with numerical values, the terms can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, a first value can be considered "substantially" the same as or equal to a second value if the first value varies from less than or equal to ± 10% of the second value, e.g., from less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, "substantially" perpendicular may refer to a range of angular variation relative to 90 ° of less than or equal to ± 10 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface may be considered substantially flat if the displacement between the highest and lowest points of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms "a" and "the" can include the plural referents unless the context clearly dictates otherwise.

As used herein, the terms "conductive" and "conductivity" refer to the ability to transmit electrical current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electrical current. One measure of conductivity is siemens per meter (S/m). Typically, the conductivity of the conductive material is greater than about 104S/m, such as at least 105S/m or at least 106S/m. The conductivity of a material can sometimes vary with temperature. Unless otherwise indicated, the electrical conductivity of the material was measured at room temperature.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such a range format is used for convenience and brevity, and should be interpreted flexibly to include numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be considered in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The drawings are not necessarily to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic reproduction of the present disclosure and actual equipment. There may be other embodiments of the disclosure that are not specifically shown. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless explicitly indicated herein, the order and grouping of operations is not a limitation of the present disclosure.

The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the present disclosure.