阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 陈则 于 2020-10-20 设计创作，主要内容包括：提供提高了耐湿性的半导体装置。在半导体基板的厚度方向流过主电流,半导体基板具有流过主电流的有源区域及在有源区域外侧包围有源区域的终端区域,半导体装置具有：第1主电极,设于有源区域之上；第2主电极,设于半导体基板的与第1主电极相反侧；杂质区域,设置在位于终端区域最外周的半导体基板的上层部；第1绝缘膜,在终端区域的外侧端缘部从杂质区域的内侧端缘部之上至半导体基板的一部分上部而设置；第2绝缘膜,从终端区域的内侧端缘部之上至有源区域的端缘部之上而设置；第1半绝缘膜,从杂质区域的未被第1绝缘膜覆盖的部分起覆盖至第1绝缘膜的至少一部分上部；及第2半绝缘膜,从第1半绝缘膜之上起覆盖至第1主电极的一部分上部。(A semiconductor device having improved moisture resistance is provided. A semiconductor device includes a semiconductor substrate, a main current flowing in a thickness direction of the semiconductor substrate, the semiconductor substrate including an active region in which the main current flows and a termination region surrounding the active region outside the active region, the semiconductor device including: a 1 st main electrode disposed over the active region; a 2 nd main electrode provided on the opposite side of the semiconductor substrate from the 1 st main electrode; an impurity region provided in an upper layer portion of the semiconductor substrate located at an outermost periphery of the termination region; a 1 st insulating film provided on an outer edge portion of the termination region from above an inner edge portion of the impurity region to a part of an upper portion of the semiconductor substrate; a 2 nd insulating film provided from above an inner edge portion of the termination region to above an edge portion of the active region; a 1 st semi-insulating film covering at least a part of the 1 st insulating film from a part of the impurity region not covered by the 1 st insulating film; and a 2 nd semi-insulating film covering from above the 1 st semi-insulating film to a part of the upper portion of the 1 st main electrode.)

1. A semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate,

the semiconductor substrate has:

an active region in which the main current flows; and

a termination region surrounding the active region on an outer side than the active region,

the semiconductor device includes:

a 1 st main electrode disposed over the active region;

a 2 nd main electrode provided on the semiconductor substrate on the opposite side of the 1 st main electrode;

an impurity region provided at an upper layer portion of the semiconductor substrate located at an outermost periphery of the termination region;

a 1 st insulating film provided on an outer edge of the termination region from above an inner edge of the impurity region to a part of an upper portion of the semiconductor substrate;

a 2 nd insulating film provided from above an inner edge portion of the termination region to above an edge portion of the active region;

a 1 st semi-insulating film covering from a portion of the impurity region not covered by the 1 st insulating film to at least a part of an upper portion of the 1 st insulating film; and

a 2 nd semi-insulating film covering from above the 1 st semi-insulating film to a part of an upper portion of the 1 st main electrode.

2. The semiconductor device according to claim 1,

the 1 st semi-insulating film covers the outer edge of the 1 st insulating film from the portion of the impurity region not covered by the 1 st insulating film.

3. The semiconductor device according to claim 1,

the 1 st insulating film has a step at an outer edge portion,

the semiconductor device further has a polysilicon film provided over the 1 st insulating film in such a manner as to bury the step,

the 1 st semi-insulating film covers over the polysilicon film and over the 1 st insulating film from a portion of the impurity region not covered by the 1 st insulating film,

the 1 st thickness of the 1 st insulating film between the 2 nd semi-insulating film and the semiconductor substrate is thicker than the 2 nd thickness of the 1 st insulating film between the polysilicon film and the semiconductor substrate.

4. The semiconductor device according to claim 1,

the 1 st insulating film has a step at an outer edge portion thereof, and covers an inner surface of a trench penetrating the impurity region and reaching the semiconductor substrate,

the semiconductor device further has a polysilicon film provided over the 1 st insulating film in such a manner as to bury the step and bury the trench,

the 1 st semi-insulating film covers over the polysilicon film and over the 1 st insulating film from a portion of the impurity region not covered by the 1 st insulating film,

the 1 st thickness of the 1 st insulating film between the 2 nd semi-insulating film and the semiconductor substrate is thicker than the 2 nd thickness of the 1 st insulating film between the polysilicon film and the semiconductor substrate.

5. The semiconductor device according to claim 1,

the 1 st semi-insulating film covers the entire upper portion of the 1 st insulating film from a portion of the impurity region not covered by the 1 st insulating film.

6. The semiconductor device according to any one of claims 2 to 5,

the 1 st semi-insulating film is further provided so as to cover from above the 2 nd insulating film to above the end edge portion of the active region.

7. The semiconductor device according to claim 1,

the 1 st semi-insulating film is made of a material having a chemical bond with Si₃N₄A resistive thin film of silicon nitride having a composition in excess of Si.

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a bipolar transistor having an insulated gate.

Background

The power module includes a power device, an insulating substrate, a resin case, a packaging material, and the like. Power devices are assembled to power modules for various applications. Power modules are sometimes used in harsh environments, such as high humidity environments, and long-term reliability of the power modules is required.

For example, in a high humidity environment, moisture enters from the gap of the resin case, and the moisture gradually enters the sealing material from the surface and the end face of the sealing material, and reaches the surface of the power device after a lapse of time. In "The impedance of humidity on The high voltage blocking Reliability of power IGBT modules and means of protection" (C, Papadopoulos, et al. microelectronics Reliability, 88-90(2018), 470 and 475.) it is disclosed that moisture or mobile ions of moisture decomposed by high electric fields at The end surfaces of The power device erode The aluminum film, resulting in physical or electrical damage to The device.

In addition, fig.1(c) of non-patent document 1 discloses a technique of applying SCC (Surface-Charge-Control) to a structure in which lnflr (linear drained Field Limiting ring) is provided as a terminal structure of a terminal region provided on the outer periphery of an active region in which a unit cell of a transistor is formed, thereby improving the reliability of a power device. In addition, fig.1(c) of non-patent document 1 is hereinafter referred to as a conventional structure.

Non-patent document 1: S.Honda, et al, "High voltage device edge termination for with temperature range plus hub with surface control (SCC) technology", ISPSD2016, pp.291-294, 2016

In the LNFLR to which the SCC disclosed in non-patent document 1 is applied, the termination region is covered with a half insulating film instead of the insulating film, the silicon oxide film covers the high-concentration N-type impurity region provided in the upper layer portion of the silicon substrate in the outermost periphery of the termination region and the silicon substrate in the vicinity thereof, the aluminum electrode connected to the N-type impurity region climbs onto the silicon oxide film, and the aluminum electrode and the silicon oxide film are covered with the half insulating film.

The semi-insulating film functions as a carrier path, and carriers generated under the condition that the power device is electrically biased flow over the semi-insulating film and are discharged, and are not accumulated in the termination region, so that the reliability of the power device is improved.

However, since the aluminum electrode in the terminal region is close to the inner surface of the resin case, it is susceptible to moisture entering through the gap of the resin case, and there is room for improvement in moisture resistance.

Disclosure of Invention

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having improved moisture resistance.

A semiconductor device according to the present invention is a semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate, the semiconductor substrate including: an active region in which the main current flows; and a termination region surrounding the active region on an outer side of the active region, the semiconductor device including: a 1 st main electrode disposed over the active region; a 2 nd main electrode provided on the semiconductor substrate on the opposite side of the 1 st main electrode; an impurity region provided at an upper layer portion of the semiconductor substrate located at an outermost periphery of the termination region; a 1 st insulating film provided on an outer edge of the termination region from above an inner edge of the impurity region to a part of an upper portion of the semiconductor substrate; a 2 nd insulating film provided from above an inner edge portion of the termination region to above an edge portion of the active region; a 1 st semi-insulating film covering from a portion of the impurity region not covered by the 1 st insulating film to at least a part of an upper portion of the 1 st insulating film; and a 2 nd semi-insulating film covering from above the 1 st semi-insulating film to a part of an upper portion of the 1 st main electrode.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the semiconductor device of the present invention, a semiconductor device with improved moisture resistance can be obtained.

Drawings

Fig.1 is a plan view schematically showing the top surface structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 2 is a sectional view showing the structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 3 is a cross-sectional view showing the structure of a semiconductor device according to embodiment 2 of the present invention.

Fig. 4 is a sectional view showing the structure of a semiconductor device according to embodiment 3 of the present invention.

Fig. 5 is a diagram showing an equivalent circuit used in the moisture resistance test.

Fig. 6 is a graph showing the experimental results of the moisture resistance experiment.

Fig. 7 is a graph showing a comparison result of surface electric field distributions of the semiconductor devices according to embodiments 1 and 2 of the present invention.

Fig. 8 is a diagram showing a depth profile of a silicon nitride film.

Fig. 9 is a cross-sectional view showing the structure of a semiconductor device according to a modification of embodiment 1 of the present invention.

Fig. 10 is a cross-sectional view showing the structure of a semiconductor device according to a modification of embodiment 1 of the present invention.

Fig. 11 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 12 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 13 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 14 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 15 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 16 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 17 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 18 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 19 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 20 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 21 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 22 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 23 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Fig. 24 is a sectional view for explaining a method of manufacturing a semi-insulating film.

Description of the reference numerals

3 semiconductor substrate, 4 impurity region, 5, 51 silicon oxide film, 6, 7 semi-insulating film, 8 polysilicon film, 9 trench, 15 emitter electrode, 23 collector electrode.

Detailed Description

< introduction >)

In the following description, the "cell region" refers to a region in which a unit cell, which is the minimum unit structure of a transistor, is formed, and is also an "active region" in which a main current flows in an on state of a semiconductor device. In the following description, "outer" refers to a direction toward the outer periphery of the semiconductor device, and "inner" refers to a direction opposite to the "outer". In the following, the conductivity type of the impurity is generally defined as "1 st conductivity type" and "2 nd conductivity type" as a P type having a conductivity type opposite to the N type, but may be defined as opposite thereto.

The drawings are schematically illustrated, and the relationship between the size and the position of images shown in different drawings is not necessarily described accurately, and may be changed as appropriate. In the following description, the same components are denoted by the same reference numerals and have the same names and functions. Therefore, detailed description thereof may be omitted. In the present specification, the "upper" and the "covering" do not prevent the existence of the inclusions between the constituent elements. For example, the phrase "B provided above a" or "a covers B" may mean that another component C is provided between a and B, or that no other component C is provided between a and B. In the following description, terms indicating specific positions and directions such as "upper", "lower", "side", "bottom", "front", and "back" are used in some cases, but these terms are used for ease of understanding the contents of the embodiments and are used for convenience and are not related to the directions in actual implementation.

< embodiment 1>

Fig.1 is a plan view schematically showing the top surface structure of an igbt (insulated Gate Bipolar transistor)100 according to embodiment 1 of the present invention. As shown in fig.1, the IGBT100 is provided on a semiconductor substrate having a rectangular shape in plan view, and is roughly divided into a cell region CR (active region) in the center portion and a terminal region TR around the cell region CR.

Fig. 2 is a sagittal sectional view taken along line a-a of fig. 1. As shown in fig. 2, the IGBT100 has: an impurity layer 11 selectively provided at 1 × 10¹²～1×10¹³/cm³Concentration (N) of^-) The upper layer part of the semiconductor substrate 3 containing N-type impurities is 1 × 10¹⁵～1×10¹⁶/cm³Contains N-type impurities; a well layer 12 of 1 × 10 on the upper layer of the impurity layer 11¹⁶～1×10¹⁸/cm³Contains a P-type impurity; and a trench gate electrode 16 provided so as to contact the well layer 12 and the side surface of the impurity layer 11 from the outermost surface of the semiconductor substrate 3 and reach the inside of the semiconductor substrate 3. Further, the apparatus comprises: a gate insulating film 161 provided on a side surface of the trench gate electrode 16; an emitter region 13 selectively provided in an upper layer portion of the well layer 12, locally in contact with the gate insulating film 161, and having a thickness of 1 × 10¹⁵～1×10¹⁶/cm³Contains N-type impurities; a contact region 14 selectively provided at an upper layer portion of the well layer 12 by 1 × 10¹⁸～1×10¹⁹/cm³Concentration (P) of (C)⁺⁺) Contains P-type impurities; and a dummy trench gate electrode 160 disposed outside the trench gate electrode 16.

Dummy trench gate electrode 160 has gate insulating film 161 on the side surface, similarly to trench gate electrode 16, but is provided with an emitter potential, similarly to contact region 14.

Of the two dummy trench gate electrodes 160, the inner dummy trench gate electrode 160 is directly connected to the emitter electrode 15 (1 st main electrode), but the outer dummy trench gate electrode 160 is connected to the emitter electrode 15 via a contact hole (not shown) provided in the extending direction of the trench.

Further, the trench gate electrode 16 is covered with the interlayer insulating film 162, and the emitter electrode 15 is covered with the interlayer insulating film 162.

Dummy trench gate electrode 160 is provided for the purpose of maintaining the breakdown voltage of IGBT100 and preventing oscillation, but it is not essential and dummy trench gate electrode 160 may not be provided.

Further, a guard ring 17 is provided on the upper layer of the semiconductor substrate 3 from the outer edge of the cell region CR to the inner edge of the termination region TR, and the guard ring 17 is formed to have a size of 1 × 10¹⁷～1×10¹⁸/cm³Concentration (P) of (C)⁺) Contains P-type impurities.

Guard ring 17 is provided for the purpose of maintaining the breakdown voltage of the IGBT, and suppresses electric field concentration from occurring at the bottom of trench gate electrode 16 at the outermost periphery of cell region CR.

Contact region 14 is also selectively provided in an upper layer portion of guard ring 17, and contact region 14 is connected to emitter electrode 15 to apply an emitter potential to guard ring 17.

In addition, a 1 × 10 protective ring is provided so as to partially cover the outer edge of the protective ring 17¹⁵～1×10¹⁶/cm³Concentration (P) of (C)^-) A RESURF layer containing a P-type impurity (RESURF: reduced Surface Field) 18. The resurf layer 18 is provided for the purpose of maintaining a withstand voltage, and reduces an electric field at the outer edge of the guard ring 17.

Further, a plurality of resurf layers 181 having a length in the horizontal direction shorter than that of the resurf layer 18 are disposed outside the resurf layer 18 so that the interval therebetween increases toward the outside. The P-type impurity concentration of the resurf layer 181 is substantially the same as the P-type impurity concentration of the resurf layer 18. The resurf layer 181 is also provided for the purpose of maintaining a withstand voltage, and the breakdown voltage is maintained by sharing a voltage between the respective resurf layers and the PN junction of the semiconductor substrate 3. The resurf layers 18 and 181 are also referred to as jte (junction Termination extension) layers.

In addition, the semiconductor substrate 3 at the outermost periphery of the termination region TR is provided at its upper layer portion with a high concentration (N)⁺⁺) An impurity region 4 containing an N-type impurity. The impurity region 4 is provided as a channel stopper, and by providing the impurity region 4, the depletion layer is prevented from reaching the end of the chip, and the deterioration of the withstand voltage holding capability is prevented.

In addition, a lower layer portion of the semiconductor substrate 3 is provided with a thickness of 1 × 10¹⁵～1×10¹⁶/cm³A buffer layer 2 containing N-type impurities at a concentration (N), and a buffer layer 2 having a thickness of 1X 10¹⁶～1×10¹⁸/cm³Collector layer 1 containing P-type impurities at concentration (P) of (2) and collector electrode 23 (2 nd main electrode) connected to collector layer 1.

A silicon oxide film 51 (2 nd insulating film) is provided on the guard ring 17 and on the inner edge of the resurf layer 18. A gate wiring 22 is provided on the silicon oxide film 51. Gate wiring 22 is provided along cell region CR in the same manner as guard ring 17, and gate wiring 22 is connected to gate wiring electrode 221 provided on silicon oxide film 51. The gate wiring electrode 221 is an aluminum electrode and is electrically connected to the outside via a lead wire not shown. The silicon oxide films 5 and 51 can be formed of, for example, a silicon oxide film (thermal oxide film) by thermal oxidation, a teos (tetraethyl orthosilicate) oxide film (BPTEOS film) containing boron (B) and phosphorus (P), or a multilayer film of a thermal oxide film and a BPTEOS film.

Further, a silicon oxide film 5 (1 st insulating film) is provided from above the inner edge of the impurity region 4 to above the semiconductor substrate 3 in the vicinity of the impurity region 4. The silicon oxide film 5 functions as a field plate and prevents extension of a depletion layer at the surface of the semiconductor substrate 3.

Further, a semi-insulating film 6 (1 st semi-insulating film) is provided so as to cover the impurity region 4 from above the outer edge of the silicon oxide film 5, and a semi-insulating film 7 (2 nd semi-insulating film) is provided so as to cover the entire region of the termination region TR including above the semi-insulating film 6 and the edge of the cell region CR.

With such a structure, the IGBT100 has improved withstand voltage and moisture resistance. The evaluation of the moisture resistance will be described later.

< embodiment 2>

Fig. 3 is a cross-sectional view of an IGBT 200 according to embodiment 2 of the present invention, which corresponds to a sagittal cross-sectional view of the IGBT100 shown in fig. 2. In fig. 3, the same components as those of the IGBT100 described with reference to fig. 2 are denoted by the same reference numerals, and redundant description thereof is omitted.

As shown in fig. 3, in the IGBT 200, the outer edge of the silicon oxide film 5 provided on the semiconductor substrate 3 from above the inner edge of the impurity region 4 to near the impurity region 4 is formed to have a step, and a polysilicon film 8 having conductivity is provided so as to fill the step. By providing polysilicon film 8, the upper surface of silicon oxide film 5 and the upper surface of polysilicon film 8 are at substantially the same height and become flat. A semi-insulating film 6 is provided so as to cover the impurity region 4 from above the flat surface, and a semi-insulating film 7 is provided so as to cover the entire region of the termination region TR including above the semi-insulating film 6 and the end edge portion of the cell region CR.

By adopting such a structure, the IGBT 200 has improved withstand voltage and moisture resistance. The evaluation of the moisture resistance will be described later.

< embodiment 3>

Fig. 4 is a cross-sectional view of an IGBT 300 according to embodiment 3 of the present invention, which corresponds to a sagittal cross-sectional view of the IGBT100 shown in fig. 2. In fig. 4, the same components as those of the IGBT100 described with reference to fig. 2 are denoted by the same reference numerals, and redundant description thereof is omitted.

As shown in fig. 4, in the IGBT 300, the outer edge of the silicon oxide film 5 provided on the semiconductor substrate 3 from above the inner edge of the impurity region 4 to near the impurity region 4 is formed to have a step, and is formed so as to cover the inner surface of the trench 9 penetrating through the impurity region 4 and reaching the inside of the semiconductor substrate 3. Then, polysilicon film 8 is provided so as to fill the step of silicon oxide film 5 and to fill trench 9 whose inner surface is covered with silicon oxide film 5. By providing polysilicon film 8, the upper surface of silicon oxide film 5 and the upper surface of polysilicon film 8 are at substantially the same height and become flat. A semi-insulating film 6 is provided so as to cover the impurity region 4 from above the flat surface, and a semi-insulating film 7 is provided so as to cover the entire region of the termination region TR including above the semi-insulating film 6 and the end edge portion of the cell region CR.

By adopting such a structure, the IGBT 300 has improved withstand voltage and moisture resistance. The evaluation of the moisture resistance will be described later.

< pressure resistance, moisture resistance >

Next, the withstand voltage and moisture resistance of IGBT100 will be described. Fig. 5 shows an equivalent circuit used for a moisture resistance test for the IGBT 100. As shown in fig. 5, in the moisture resistance test, the gate electrode G and the emitter electrode E of the IGBT100 were short-circuited and connected to ground (0V), thereby connecting the gate-emitter voltage V to ground_GEThe voltage is set to 0V, and the IGBT100 is set to a normally-off state. In addition, a collector voltage V is applied from a DC power supply to the collector electrode C_CC. Fig. 6 shows the results of a moisture resistance test performed at a power supply voltage of 85% of the rated voltage at a temperature of 150 ℃ and a relative humidity of 85%.

Fig. 6 is a graph showing the results of comparison between the IGBTs 100 to 300 of embodiments 1 to 3 described above and the conventional structure in terms of withstand voltage (static withstand voltage), moisture resistance, and termination region width. Fig. 6 shows the results of standardizing the moisture resistance, the voltage resistance, and the terminal region width of embodiments 1 to 3 with respect to the moisture resistance, the voltage resistance, and the terminal region width of the conventional structure.

The evaluation of the moisture resistance was carried out in a state where the temperature was 150 ℃ and the relative humidity was 85%, in a state where the gate electrode G and the emitter electrode E were short-circuited as shown in fig. 5, and the power supply voltage was 85% of the rated voltage, for example, in a case of a device having a rated voltage of 6.5kV class, a power supply voltage of 5525V was applied.

That is, the power supply voltage is continuously applied until the device is subjected to characteristic variation, breakdown, or a predetermined time. For example, the samples that did not suffer from the characteristic fluctuation, the appearance deterioration, and the deterioration even when applied for 1000 hours under the above conditions were evaluated to have 2 times higher moisture resistance and superior moisture resistance than the samples that deteriorated at 500 hours. In this way, the quality of the moisture resistance was evaluated by maintaining a constant performance for a long time.

The withstand voltage is evaluated by a dynamic withstand voltage test of a general semiconductor device, and the termination region width is evaluated by comparing the width of the termination region of each of the IGBTs 100 to 300 of embodiments 1 to 3 with the width of the termination region of a conventional structure.

As shown in fig. 6, the results of the moisture resistance test were better than those of the conventional structures in any of embodiments 1 to 3, and in all of the embodiments, the damage did not occur even when the time taken for the test to damage the conventional structure was 1.5 times longer. This is considered to be because, in the conventional structure, the aluminum electrode is provided in the termination region, whereas in the IGBTs 100 to 300 of embodiments 1 to 3, the half insulating film 6 is provided instead of the aluminum electrode, thereby eliminating the corrosion of moisture to the aluminum electrode and improving the moisture resistance.

In addition, the withstand voltage of embodiment 2 is improved by about 1.2 times as compared with embodiment 1. This is because polysilicon film 8 is provided at the outer edge of silicon oxide film 5 in the termination region, and polysilicon film 8 functions as a field plate.

That is, as shown in fig. 3, in the IGBT 200, the polysilicon film 8 and the semi-insulating film 6 form a 2-stage field plate structure because the thickness t2 (the 2 nd thickness) of the silicon oxide film 5 between the polysilicon film 8 and the surface of the semiconductor substrate 3 is thinner than the thickness t1 (the 1 st thickness) of the silicon oxide film 5 between the semi-insulating film 6 and the surface of the semiconductor substrate 3.

The field plate structure here is a multilayer structure of a conductive film, an insulating film, and a semiconductor layer, and the 2-step field plate structure is a field plate structure in which 2 conductive films are formed on the semiconductor layer with the insulating film interposed therebetween.

The IGBT 200 has the half-insulating film 6 and the 2-layer film composed of the polysilicon film 8 and the half-insulating film 6 on the silicon oxide film 5 having the thickness t1 and the silicon oxide film 5 having the thickness t2, respectively, and has a 2-stage field plate structure with respect to the semiconductor substrate 3.

In the case of the IGBT 200, N is generated at the interface between the semiconductor substrate 3 and the silicon oxide film 5 directly below the silicon oxide film 5 of the field plate structure in the withstand voltage mode^-A type electron storage layer. The electron accumulation layer has a pseudo high concentration of N^-Layer, block N^-The drift layer, i.e., the depletion layer on the surface of the semiconductor substrate 3, extends, but electric field concentration occurs directly below the edge portion of the field plate.

However, in the 2-stage field plate structure, by appropriately setting the length of each field plate and the thickness of the insulating film (silicon oxide film 5) therebelow, the electric field concentration immediately below the field plate can be dispersed. By suppressing local electric field concentration, the withstand voltage can be improved. The larger the number of stages of the field plate, the more the electric field concentration is dispersed, and the breakdown voltage can be improved.

As described above, the IGBT 200 of embodiment 2 having the 2-stage field plate structure has a higher withstand voltage than the IGBT100 of embodiment 1 having the 1-stage field plate structure. As shown in fig. 6, IGBT 300 according to embodiment 3 also has a 2-stage field plate structure, and therefore has a higher withstand voltage than IGBT 100.

In addition, the width of the termination region of the IGBT 300 of embodiment 3 is narrower than those of embodiments 1 and 2. This is because, as shown in fig. 4, IGBT 300 has trench 9 penetrating impurity region 4 and reaching inside semiconductor substrate 3 on the outer peripheral side of the termination region, and polysilicon film 8 is buried inside trench 9 with silicon oxide film 5 interposed therebetween, so that the length of the field plate, here, the creepage distance of polysilicon film 8, becomes long. Therefore, the withstand voltage is constant, and the width of the termination region can be reduced. Further, by adopting this structure, the withstand voltage can be improved even if the termination region has the same width as that of the other embodiments.

Fig. 7 shows a comparison result of the surface electric field distributions of the IGBTs 100 and 200 in embodiments 1 and 2 at the B-B line region shown in fig. 2 and 3, respectively. In fig. 7, the vertical axis (Y axis) represents the electric field intensity (MV/cm), and the horizontal axis (X axis) represents the normalized distance, so that the terminal region width is constant.

In fig. 7, the surface electric field distribution in embodiment 1 is indicated by a solid line, and the surface electric field distribution in embodiment 2 is indicated by a broken line. The portion that becomes the peak in the surface electric field distribution of embodiment 1 is the electric field intensity at the end of the semi-insulating film 6, and the portion that becomes the peak in the surface electric field distribution of embodiment 2 is the electric field intensity at the end of the polysilicon film 8.

The voltage is an integral of the electric field and the distance, and in fig. 7, the area of a region defined by the electric field distribution and the X axis represents the withstand voltage. Fig. 7 shows a local electric field distribution of a portion provided with the field plate structure, and shows that the IGBT 200 of embodiment 2 has a larger electric field distribution area and a larger withstand voltage than the IGBT100 of embodiment 1.

< Material for semi-insulating film >

Next, the materials of the semi-insulating film 6 and the semi-insulating film 7 will be described. In order to use the semi-insulating film 6 as a field plate, it is formed of a material having resistance. As an example, the semi-insulating film 6 is made of silicon nitride (Si)₃N₄A resistive thin film made of silicon nitride having a composition exceeding that of Si. This makes it possible to use the semi-insulating film 6 as a field plate, suppress local electric field concentration in the termination region, and improve the withstand voltage.

If the ratio of Si to N (Si: N) is too small, the hopping conduction of the semi-insulating film 6 is hardly caused, and the field plate does not function as a field plate having conductivity. To function as a field plate, Si: n has no upper limit, but due to limitations of the film formation temperature and the process of chemical reaction at the time of film formation, Si: there is an upper limit for N, roughly Si: n is less than or equal to 1: 2.5.

fig. 8 shows an example of the depth distribution of the semi-insulating film. In fig. 8, the horizontal axis represents depth (nm) and the vertical axis represents the atomic density ratio (%). Fig. 8 is a depth profile of a silicon nitride film formed over silicon, Si: n is 2: about 1.

Since the semi-insulating film 6 is semi-insulating, it is more susceptible to external electric charges and mobile ions inside the power module packaging material than a metal material such as an aluminum electrode. In order to block the influence of external charges, the semi-insulating film 6 is covered by the semi-insulating film 7. The semi-insulating film 7 is in contact with the emitter electrode 15 on the cell region side, and thus the influence of external charge can be suppressed by the skip conduction characteristic of the semi-insulating film.

That is, the semi-insulating film 6 is in a floating state and is easily affected by external charges, but the semi-insulating film 7 is in contact (grounded) with the emitter electrode 15 on the cell region side and has the same potential as the high voltage side via the semi-insulating film 6 on the terminal region side, so the distribution of the internal potential of the semi-insulating film 7 is substantially constant and is not easily affected by external charges. The semi-insulating films 6 and 7 had a resistivity of 10 at 25 ℃ and a voltage of 20V¹³～10¹⁶Ωcm。

Hopping conduction refers to a conduction mechanism resulting from excitation of carriers within the band gap of a material. If there is skip conduction, local charges temporarily induced by an external influence are not always fixed at the same position but gradually move to the ground or high potential side to disappear. If the electric charges are fixed at the same position all the time, the electric field distribution inside the semiconductor substrate is affected by the dielectric phenomenon to lower the withstand voltage, but since the semi-insulating film has a hopping conduction characteristic, the lowering of the withstand voltage can be suppressed.

If it has resistance, the same effect can be obtained whether the semi-insulating film 6 and the semi-insulating film 7 are of the same composition or of different compositions. Even in the case of the same composition, a step is formed with respect to the semi-insulating film 7 at the outer peripheral end portion of the semi-insulating film 6, and the semi-insulating film 6 and the semi-insulating film 7 can be distinguished from each other in a cross-sectional view. Further, since the film thickness of the portion having the 2-layer structure of the semi-insulating film 6 and the semi-insulating film 7 is thicker than the film thickness of the portion having only the semi-insulating film 7, the semi-insulating film 6 and the semi-insulating film 7 can be distinguished from each other in a cross-sectional view.

< modification example >

In the IGBT100 according to embodiment 1 shown in fig.1, the semi-insulating film 6 is provided so as to cover the impurity region 4 from above the outer edge portion of the silicon oxide film 5 in the termination region TR, but may be provided so as to cover the entire upper portion of the silicon oxide film 5 in the termination region, as in the IGBT 100A shown in fig. 9. The effect produced by adopting this configuration is the same as that of the IGBT 100.

In IGBT100 according to embodiment 1 shown in fig.1, half-insulating film 6 is provided so as to cover the impurity region 4 from above the outer edge of silicon oxide film 5 in termination region TR, but as in IGBT 100B shown in fig. 10, half-insulating film 6 may cover the entire upper portion of silicon oxide film 5 in termination region, and may cover the upper portion of silicon oxide film 51 provided from above guard ring 17 to above the inner edge of resurf layer 18 and the edge of cell region CR. The effect produced by adopting this configuration is the same as that of the IGBT 100. In this case, the semi-insulating film 7 is electrically connected to the emitter electrode 15 via the semi-insulating film 6.

As described above, the configuration in which the half insulating film 6 is provided so as to cover the edge portion of the cell region CR from above the silicon oxide film 51 provided from above the guard ring 17 to above the edge portion on the inner side of the resurf layer 18 can be applied to the IGBTs 200 and 300 of embodiments 2 and 3. The effect produced by adopting this configuration is the same as that of IGBTs 200 and 300.

In addition, in all three embodiments 1 to 3, the semi-insulating film 7 is further covered with another semi-insulating film, an insulating film, a polyimide resin, or the like, whereby the moisture blocking effect is enhanced.

The silicon oxide film 5 may be provided continuously over the entire termination region, or may be provided intermittently. Even when these structures are employed, the same effects as those of the IGBTs 100 to 300 of embodiments 1 to 3 are obtained.

< method for Forming semi-insulating film >

Next, a method for manufacturing the semi-insulating film 6 and the semi-insulating film 7 will be described with reference to fig. 11 to 19. Fig. 11 to 19 show cross sections around the outer periphery of termination region TR, and the impurity regions and impurity layers other than impurity region 4 are not shown.

First, in the step shown in fig. 11, after the silicon oxide film 5 is formed on the semiconductor substrate 3, a resist mask RM1 for patterning the silicon oxide film 5 is formed by photolithography.

Next, in the step shown in fig. 12, after the silicon oxide film 5 is patterned by etching using the resist mask RM1, the resist mask RM1 is removed.

Next, in the step shown in fig. 13, N-type impurities are ion-implanted into the semiconductor substrate 3 using the silicon oxide film 5 provided with the opening OP1 for forming the impurity region 4 as an implantation mask, thereby forming the impurity region 4.

Next, in the step shown in fig. 14, a resist mask RM2 for further patterning the silicon oxide film 5 is formed by photolithography.

Next, in the step shown in fig. 15, after the silicon oxide film 5 is patterned by etching using the resist mask RM2, the resist mask RM2 is removed. Through this step, the silicon oxide film 51 is patterned from above the guard ring 17 to above the inner edge of the resurf layer 18.

Next, in the step shown in fig. 16, a semi-insulating film 6 of silicon nitride is formed by cvd (chemical Vapor deposition) to cover the upper surface of the silicon oxide film 5 and the upper surface of the semiconductor substrate 3.

Next, in the step shown in fig. 17, a resist mask RM3 for patterning the semi-insulating film 6 is formed on the semi-insulating film 6 by photolithography. The resist mask RM3 formed here has the following pattern: the semi-insulating film 6 is left from the upper side of the outer edge of the silicon oxide film 5 to the upper side of the impurity region 4.

Next, in the step shown in fig. 18, after patterning the semi-insulating film 6 by etching using the resist mask RM3, the resist mask RM3 is removed.

Next, in the step shown in fig. 19, the semi-insulating film 6 and the semi-insulating film 7 are formed by forming the semi-insulating film 7 of silicon nitride by CVD, for example, so as to cover the upper side of the semi-insulating film 6, the upper side of the silicon oxide film 5, the upper side of the semiconductor substrate 3, and the upper side of the silicon oxide film 51.

In the etching step described with reference to fig. 15 and 18, plasma etching using a reactive gas, wet etching using a chemical solution, or etching combining these 2 methods can be used.

As described with reference to fig. 11, 14, and 17, although 3 photolithography steps are necessary to form the semi-insulating film 6 and the semi-insulating film 7, when selective etching of the semi-insulating film 6 and the silicon oxide film 5 is possible depending on the type of reactive gas or chemical solution, the photolithography step described with reference to fig. 17 can be omitted by using the semi-insulating film 6 as an etching mask for the silicon oxide film 5, and the semi-insulating film 6 and the semi-insulating film 7 can be formed by 2 photolithography steps.

Next, a manufacturing method for forming the semi-insulating film 6 and the semi-insulating film 7 by 2 photolithography steps will be described with reference to fig. 20 to 24.

First, through the steps described with reference to fig. 11 to 13, the impurity region 4 is formed in the semiconductor substrate 3. Next, in the step shown in fig. 20, a semi-insulating film 6 of silicon nitride is formed by CVD, for example, so as to cover the silicon oxide film 5 and the semiconductor substrate 3.

Next, in the step shown in fig. 21, a resist mask RM2 for patterning the semi-insulating film 6 is formed on the semi-insulating film 6 by photolithography. The resist mask RM2 formed here has the following pattern: the semi-insulating film 6 is left on the upper portion of the silicon oxide film 5 and the impurity region 4 in the termination region, and the semi-insulating film 6 is left on the silicon oxide film 51 and the end edge portion of the cell region CR from above the guard ring 17 (not shown) to above the end edge portion inside the resurf layer 18 (not shown).

Next, in the step shown in fig. 22, after patterning the semi-insulating film 6 by etching using the resist mask RM2, the resist mask RM2 is removed.

Next, in the step shown in fig. 23, the silicon oxide film 5 is patterned by etching using the patterned semi-insulating film 6 as a mask. Thereby, the silicon oxide film 5 is left from above the termination region and guard ring 17 (not shown) to above the inner edge of the resurf layer 18 (not shown). The silicon oxide film 5 remaining from above the guard ring 17 to above the inner edge of the resurf layer 18 becomes the silicon oxide film 51.

Next, in the step shown in fig. 24, the semi-insulating film 6 and the semi-insulating film 7 are formed by forming the semi-insulating film 7 of silicon nitride by CVD, for example, so as to cover the upper side of the semi-insulating film 6 and the upper side of the semiconductor substrate 3.

When such a manufacturing method is applied, the IGBT 100B shown in fig. 10 has the following structure: the semi-insulating film 6 covers the impurity region 4 from the upper portion of the silicon oxide film 5 in the termination region, and covers the silicon oxide film 51 provided from the upper portion of the guard ring 17 to the upper portion of the end edge portion inside the resurf layer 18 and the end edge portion of the cell region CR.

< application to other semiconductor device >

In embodiments 1 to 3 and the modified examples described above, an IGBT was described as an example, but if a semiconductor device having a termination region such as a mos (metal Oxide semiconductor) transistor or various diodes is used, the structure of the termination region can be applied to improve moisture resistance while maintaining a static breakdown voltage.

In embodiments 1 to 3 and the modified examples, the trench gate type IGBT was described as an example, but the structure of the termination region may be applied to a planar gate type IGBT or MOS transistor.

In addition, the present invention can freely combine the respective embodiments, or appropriately modify or omit the respective embodiments within the scope of the invention.