阅读说明：本技术 一种芯片封装结构及其加工工艺方法 (Chip packaging structure and processing method thereof ) 是由 刘浩 林建涛 屈海峰 于 2020-12-22 设计创作，主要内容包括：本发明涉及一种芯片封装结构及其加工工艺方法,其中,芯片封装结构,包括芯片,及与所述芯片连接的环氧树脂层；所述芯片上表面还设有若干根金属线,所述金属线的上端突出于所述环氧树脂层的上表面,所述环氧树脂层的上表面还设有线层,所述金属线的上端还与所述线层连接,所述线层的上表面还设有若干个锡球。本发明通过运用临时载板,移除了传统基板载体,降低了封装结构的厚度,运用金属线导通内外线路连接,减少了线路长度,提升了产品性能且降低了生产成本,能够更好地满足需求。(The invention relates to a chip packaging structure and a processing technique method thereof, wherein the chip packaging structure comprises a chip and an epoxy resin layer connected with the chip; the upper surface of the chip is further provided with a plurality of metal wires, the upper ends of the metal wires protrude out of the upper surface of the epoxy resin layer, the upper surface of the epoxy resin layer is further provided with a wire layer, the upper ends of the metal wires are further connected with the wire layer, and the upper surface of the wire layer is further provided with a plurality of solder balls. According to the invention, the temporary carrier plate is used, the traditional substrate carrier is removed, the thickness of the packaging structure is reduced, the inner and outer circuit connection is conducted by using the metal wire, the circuit length is reduced, the product performance is improved, the production cost is reduced, and the requirement can be better met.)

1. A chip packaging structure is characterized by comprising a chip and an epoxy resin layer connected with the chip; the upper surface of the chip is further provided with a plurality of metal wires, the upper ends of the metal wires protrude out of the upper surface of the epoxy resin layer, the upper surface of the epoxy resin layer is further provided with a wire layer, the upper ends of the metal wires are further connected with the wire layer, and the upper surface of the wire layer is further provided with a plurality of solder balls.

2. The chip package structure according to claim 1, wherein the metal lines are vertically disposed on the upper surface of the chip.

3. A processing method of a chip packaging structure is characterized by comprising the following steps:

grinding and cutting the wafer into a plurality of single chips, and then placing the single chips on a temporary carrier plate;

implanting metal wires on the upper surface of the chip;

plastically packaging the chip and the carrier plate with the adhesive surface after the metal wire is implanted;

removing the temporary carrier plate, and then polishing the thickness of the upper surface of the plastic package rubber surface until the contact of the metal wire is exposed out of the upper surface of the plastic package rubber surface;

rewiring the upper surface of the plastic packaging adhesive surface;

implanting a plurality of solder balls on the upper surface of the wire layer to form a whole IC;

the whole board IC is diced to obtain individual IC particles.

4. The processing method of the chip packaging structure according to claim 3, wherein the wafer has a thickness of 0.7mm to 0.8mm, and the wafer has a thickness of 0.05mm to 0.1mm after grinding.

5. The processing method of the chip package structure as claimed in claim 3, wherein the temporary carrier has a circular shape or a square shape.

6. The processing method of the chip packaging structure according to claim 3, wherein the thickness of the temporary carrier plate is 0.1mm-0.2 mm.

7. A processing method of a chip package structure according to claim 3, wherein the thickness of the plastic package adhesive surface is 0.3mm to 1 mm.

8. The processing method of the chip packaging structure according to claim 7, wherein the polishing thickness of the plastic packaging adhesive surface is 0.1mm-0.5 mm.

9. The processing method of the chip packaging structure according to claim 3, wherein the thickness of the wire layer is 0.05mm-0.1 mm.

10. The processing method of the chip package structure as claimed in claim 3, wherein the solder ball has a diameter of 0.3mm to 0.5 mm.

Technical Field

The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a processing method thereof.

Background

The existing traditional DRAM chip packaging process mainly comprises two types: 1) the specific process flow is described as follows:

1. before packaging, the surface of a wafer needs to be planted with balls; 2. then grinding and cutting the wafer into single particles, mounting the single chip on the substrate by flip chip of the crystal grain and performing reflow soldering to weld the chip on the substrate; 3. sealing glue and assembling solder balls after welding, and finally cutting to complete the packaging of the product; the packaging structure needs to plant balls on the surface of the wafer in advance, and meanwhile, the substrate carrier needs to be used for communicating the chip with an external circuit through the planted balls, and the whole thickness of the product is thicker.

2) The specific process flow is described as follows:

1. before packaging, a wafer needs to be ground and cut into single particles, and a single chip is attached to a substrate through flip chip attachment;

2. connecting the I/0 port of the chip and the port of the substrate together by using a metal wire through a wire bonding process after the surface mounting is finished;

3. finally, sealing glue and assembling solder balls, and finally cutting to finish the packaging of the product; the packaging structure needs to communicate the substrate and the chip by a bonding wire mode and then connect the substrate and the chip with an external circuit by a tin ball, and the whole thickness of the product is thicker.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a chip packaging structure and a processing method thereof.

In order to achieve the purpose, the invention adopts the following technical scheme:

a chip packaging structure comprises a chip and an epoxy resin layer connected with the chip; the upper surface of the chip is further provided with a plurality of metal wires, the upper ends of the metal wires protrude out of the upper surface of the epoxy resin layer, the upper surface of the epoxy resin layer is further provided with a wire layer, the upper ends of the metal wires are further connected with the wire layer, and the upper surface of the wire layer is further provided with a plurality of solder balls.

The further technical scheme is as follows: the metal wire is vertically arranged on the upper surface of the chip.

A processing technique method of a chip packaging structure comprises the following steps:

grinding and cutting the wafer into a plurality of single chips, and then placing the single chips on a temporary carrier plate;

implanting metal wires on the upper surface of the chip;

plastically packaging the chip and the carrier plate with the adhesive surface after the metal wire is implanted;

removing the temporary carrier plate, and then polishing the thickness of the upper surface of the plastic package rubber surface until the contact of the metal wire is exposed out of the upper surface of the plastic package rubber surface;

rewiring the upper surface of the plastic packaging adhesive surface;

implanting a plurality of solder balls on the upper surface of the wire layer to form a whole IC;

the whole board IC is diced to obtain individual IC particles.

The further technical scheme is as follows: the thickness of the wafer is 0.7mm-0.8mm, and the thickness of the wafer after grinding is 0.05mm-0.1 mm.

The further technical scheme is as follows: the temporary support plate is round or square.

The further technical scheme is as follows: the thickness of the temporary carrying plate is 0.1mm-0.2 mm.

The further technical scheme is as follows: the thickness of the plastic packaging rubber surface is 0.3mm-1 mm.

The further technical scheme is as follows: the polishing thickness of the plastic packaging rubber surface is 0.1mm-0.5 mm.

The further technical scheme is as follows: the thickness of the wire layer is 0.05mm-0.1 mm.

The further technical scheme is as follows: the diameter of the solder ball is 0.3mm-0.5 mm.

Compared with the prior art, the invention has the beneficial effects that: through the application of the temporary support plate, the traditional substrate carrier is removed, the thickness of the packaging structure is reduced, the metal wire is used for conducting the connection of the inner circuit and the outer circuit, the length of the circuit is reduced, the performance of the product is improved, the production cost is reduced, and the requirement can be better met.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the invention;

fig. 2 is a schematic flow chart of a processing method of a chip package structure according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to the embodiment shown in fig. 1, the present invention discloses a chip package structure, which includes a chip 10, and an epoxy resin layer 20 connected to the chip 10; the upper surface of the chip 10 is further provided with a plurality of metal wires 30, the upper ends of the metal wires 30 protrude out of the upper surface of the epoxy resin layer 20, the upper surface of the epoxy resin layer 20 is further provided with a wire layer 40, the upper ends of the metal wires 30 are further connected with the wire layer 40, and the upper surface of the wire layer 40 is further provided with a plurality of solder balls 50.

The metal wire 30 is vertically arranged on the upper surface of the chip 10, the lower part of the metal wire 30 is connected with the chip 10, the upper part of the metal wire 30 is connected with the wire layer 40, the inner circuit and the outer circuit are directly conducted through the metal wire 30, a substrate is removed as a carrier for conducting the circuit, the length of the circuit is reduced, the thickness of a packaging structure is reduced, the performance of the product is improved, and the cost of the substrate is saved.

Referring to the specific embodiment shown in fig. 2, the invention discloses a processing method of a chip packaging structure, which comprises the following steps:

s1, grinding and cutting the wafer into a plurality of single chips, and then placing the single chips on a temporary carrier plate;

the thickness of the wafer is 0.7mm-0.8mm, the thickness of the wafer after grinding is 0.05mm-0.1mm, and the specific thickness can be selected according to actual needs so as to meet different requirements. In this embodiment, the temporary carrier includes all metal carriers, the temporary carrier is circular or square, and the thickness of the temporary carrier is 0.1mm to 0.2mm, so as to be suitable for different scenes.

S2, implanting metal wires on the upper surface of the chip;

the metal wire is vertically planted on the upper surface of the chip through a wire welding process, and the length of the metal wire is set by stretching according to the thickness of the plastic package rubber surface so as to meet different requirements.

S3, plastic-packaging the chip and the carrier plate with the metal wires implanted on the plastic surface;

the thickness of the plastic packaging rubber surface is 0.3mm-1mm, and the specific thickness can be selected according to actual needs so as to meet different requirements.

And S4, removing the temporary carrier plate, then polishing the thickness of the upper surface of the plastic package rubber surface until the contact of the metal wire is exposed out of the upper surface of the plastic package rubber surface, so that the contact of the metal wire is connected with the wire layer, the inner circuit and the outer circuit are conducted through the metal wire, and the ball planting process on the surface of the wafer can be removed, thereby simplifying the wafer processing flow.

The temporary carrier plate is removed through a stripping process, the polishing thickness of the plastic packaging rubber surface is 0.1-0.5 mm, and the specific polishing thickness can be selected according to actual needs so as to meet different requirements.

S5, rewiring the upper surface of the plastic package rubber surface;

s6, implanting a plurality of solder balls on the upper surface of the wire layer to form a whole IC;

wherein, the contact of the layer connecting metal wire of the wire is welded and distributed in the salient point, implant the tin ball on the salient point of welding, easy to operate, save the cost.

The thickness of the wire layer is 0.05mm-0.1mm, the diameter of the solder ball is 0.3mm-0.5mm, and specific thickness and diameter values can be selected according to actual needs so as to meet different requirements.

And S7, cutting the whole IC board to obtain a plurality of single IC particles.

Wherein, the cutting adopts the diamond blade, and is quick high-efficient, and difficult to deform.

The packaging structure and the process flow include but are not limited to a DRAM chip package, and any chip package realized by adopting the method is included in the structure process.

The packaging structure and the process method provided by the invention can reduce the packaging thickness and the packaging area of the chip, achieve the purposes of lightness, thinness and small size, reduce the use of the substrate, save the processing cost of the product and flexibly design the packaging size of the chip.

The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.