阅读说明：本技术 半导体设备封装 (Semiconductor device package ) 是由 叶昶麟 于 2020-05-29 设计创作，主要内容包括：一种半导体设备封装包括载体、停止层、阻挡层和包封料。所述载体具有第一表面和相对于所述第一表面下凹的第二表面。所述停止层安置在所述载体的所述第二表面上。所述阻挡层安置在所述停止层上并且从所述载体的所述第一表面凸出。所述包封料安置在所述载体的所述第一表面上。此外,所述包封料具有安置在所述阻挡层上的侧表面。(A semiconductor device package includes a carrier, a stop layer, a barrier layer, and an encapsulant. The carrier has a first surface and a second surface that is concave relative to the first surface. The stop layer is disposed on the second surface of the carrier. The barrier layer is disposed on the stop layer and protrudes from the first surface of the carrier. The encapsulant is disposed on the first surface of the carrier. Further, the encapsulant has side surfaces disposed on the barrier layer.)

1. A semiconductor device package, comprising:

a carrier having a first surface and a second surface that is concave relative to the first surface;

a stop layer disposed on the second surface of the carrier;

a barrier layer disposed on the stop layer and protruding from the first surface of the carrier; and

an encapsulant disposed on the first surface of the carrier;

wherein the encapsulant has side surfaces disposed on the barrier layer.

2. The semiconductor device package of claim 1, wherein the stop layer and the barrier layer are made of the same material.

3. The semiconductor device package of claim 1, wherein the barrier layer is comprised of solder balls.

4. The semiconductor device package of claim 1, wherein the stop layer has a third surface and the barrier layer has a fourth surface connected to the third surface of the stop layer, and wherein a portion of the fourth surface of the barrier layer is exposed.

5. The semiconductor device package of claim 4, wherein an entirety of the fourth surface of the barrier layer is exposed.

6. The semiconductor device package of claim 4, further comprising a space between the fourth surface of the barrier layer and the encapsulant.

7. The semiconductor device package of claim 1, wherein a maximum cross-sectional width of the stop layer is greater than a maximum cross-sectional width of the barrier layer.

8. A semiconductor device package, comprising:

a carrier having a first surface and a second surface that is concave relative to the first surface;

a stop layer disposed on the second surface of the carrier;

a first barrier layer disposed on the stop layer and having a third surface that is coplanar with or recessed relative to the first surface; and

an encapsulant disposed on the first surface of the carrier;

wherein the encapsulant has a side surface disposed on the third surface of the barrier layer.

9. The semiconductor device package of claim 8, wherein the stop layer and the first barrier layer are made of the same material.

10. The semiconductor device package of claim 8, wherein the stop layer has a fourth surface and the first barrier layer has a fifth surface connected to the fourth surface of the stop layer, and wherein the fifth surface of the barrier layer is exposed.

11. The semiconductor device package of claim 8, wherein the carrier has a sixth surface connected to the first surface and covered by the encapsulant.

12. The semiconductor device package of claim 8, further comprising a second barrier layer, wherein the first and second barrier layers are disposed on the stop layer and are respectively adjacent to two opposite sides of the stop layer.

13. The semiconductor device package of claim 12, wherein the first and second barrier layers and the stop layer are made of the same material.

14. The semiconductor device package of claim 12, wherein the carrier has a sixth surface connected to the first surface and covered by the encapsulant, and wherein the carrier has a seventh surface opposite the sixth surface and disposed on the second barrier layer.

15. A semiconductor device package, comprising:

a carrier having a first surface, a second surface that is concave relative to the first surface, and a third surface connected to the first surface;

a stop layer disposed on the second surface of the carrier;

an encapsulant disposed on the first surface of the carrier;

wherein the third surface of the carrier is disposed on the stop layer and the encapsulant has side surfaces that are coplanar with the third surface of the carrier.

16. The semiconductor device package of claim 15, wherein the carrier further comprises a fourth surface opposite the third surface and disposed on the stop layer.

17. The semiconductor device package of claim 16, wherein a distance between the third surface and the fourth surface is less than or equal to a cross-sectional width of the stop layer.

18. The semiconductor device package of claim 16, wherein a roughness of the third surface is greater than a roughness of the fourth surface.

19. The semiconductor device package of claim 16, wherein the stop layer comprises a fifth surface adjacent to the third surface and a sixth surface adjacent to the fourth surface and opposite the fifth surface, and wherein a distance between the third surface and the fifth surface is less than a distance between the fourth surface and the sixth surface.

20. The semiconductor device package of claim 16, wherein an angle between the first surface and the third surface is greater than an angle between the first surface and the fourth surface.

Technical Field

The present disclosure relates to a semiconductor device package and a semiconductor device package having an area or space free of an encapsulating material, and the like.

Background

The molding process is a packaging technique for semiconductor packages that is used to protect the substrate and components on the substrate. However, in some embodiments, not all areas of the substrate are covered by the encapsulation material (also referred to as molding compound), as in antenna-on-package (AoP) embodiments where it may be desirable to perform impedance matching of the component-to-antenna path. Accordingly, the semiconductor device package may have a non-molding region or space (a region or space not containing an encapsulation material), and a user may easily adjust impedance matching by adjusting a Surface Mount Technology (SMT) passive component after a molding process.

Disclosure of Invention

According to an example embodiment of the present disclosure, a semiconductor device package includes a carrier, a stop layer, a barrier layer, and an encapsulant. The carrier has a first surface and a second surface that is concave relative to the first surface. The stop layer is disposed on the second surface of the carrier. The barrier layer is disposed on the stop layer and protrudes from the first surface of the carrier. The encapsulant is disposed on the first surface of the carrier. Further, the encapsulant has side surfaces disposed on the barrier layer.

According to another example embodiment of the present disclosure, a semiconductor device package includes a carrier, a stop layer, a first barrier layer, and an encapsulant. The carrier has a first surface and a second surface that is concave relative to the first surface. The stop layer is disposed on the second surface of the carrier. The first barrier layer is disposed on the stop layer and has a third surface that is coplanar with or recessed relative to the first surface. The encapsulant is disposed on the first surface of the carrier. Further, the encapsulant has a side surface disposed on the third surface of the barrier layer.

According to another example embodiment of the present disclosure, a semiconductor device package includes a carrier, a stop layer, and an encapsulant. The carrier has a first surface, a second surface that is concave relative to the first surface, and a third surface connected to the first surface. The stop layer is disposed on the second surface of the carrier. The encapsulant is disposed on the first surface of the carrier. The third surface of the carrier is disposed on the stop layer, and the encapsulant has a side surface that is coplanar with the third surface of the carrier.

For further understanding of the disclosure, the following examples are provided together with the figures to facilitate understanding of the disclosure, however the figures are provided for reference and illustration only and are not intended to limit the scope of the disclosure.

Drawings

Fig. 1 is a schematic perspective view of a semiconductor device package according to an embodiment of the present disclosure.

Fig. 2 is a schematic perspective view of a semiconductor device package according to another embodiment of the present disclosure.

Fig. 3 is a schematic perspective view of a semiconductor device package according to another embodiment of the present disclosure.

Fig. 4A, 4B, 4C, 4D, 4E, and 4F illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present disclosure.

Fig. 5A, 5B, 5C, 5D, 5E, and 5F illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present disclosure.

Fig. 6A, 6B, 6C, 6D, 6E, and 6F illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present disclosure.

Fig. 7A, 7B, 7C, 7D, 7E, and 7F illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present disclosure.

Fig. 8A, 8B, 8C, 8D, 8E, and 8F illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present disclosure.

Fig. 9A, 9B, 9C, 9D, 9E, and 9F illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present disclosure.

Detailed Description

The foregoing illustration and the following detailed description are exemplary for the purpose of further explaining the scope of the present disclosure. Other objects and advantages associated with the present disclosure will be set forth in the description and drawings that follow.

Fig. 1 shows a semiconductor device package 1 according to an embodiment of the present disclosure. Specifically, the semiconductor device package 1 may have a molding region 13 and a non-molding region 15. As used herein, the term "molding region" may refer to a region covered by a molding material (e.g., a region of a substrate), and the term "non-molding region" may refer to a region or space substantially free of a molding material (e.g., a region of a substrate). Referring to fig. 1, a semiconductor device package 1 may include a carrier 10. The carrier 10 has an upper surface 11. An encapsulating material 131 may be disposed on the upper surface 11 of the carrier 10. A die 133 and components 135 (e.g., electronic components such as passive electronic components) are disposed on the upper surface 11 of the carrier 10 and are covered by the encapsulation material 131. As shown in fig. 1, the area covered by the encapsulating material 131 is the molding area 13. Further, referring to fig. 1, a certain area of the upper surface 11 of the carrier 10 is exposed from the encapsulating material 131 (e.g., substantially free of the encapsulating material 131). The region exposed from the encapsulation material 131 is the non-molding region 15. In the non-molding region 15, substantially no encapsulation material 131 is disposed on the upper surface 11 of the carrier 10, and the die 151 and the component 153 disposed on the upper surface 11 of the carrier 10 are not covered by the encapsulation material 131 and are thus exposed. Furthermore, a conductive layer 14 is arranged on the upper surface 11 of the carrier 10. The conductive layer 14 may include a stop layer or a stop layer and a barrier layer. The conductive layer 14 may be positioned substantially at and/or extend along the interface between the molding region 13 and the non-molding region 15. That is, the conductive layer 14 may be positioned substantially between the molding region 13 and the non-molding region 15. Referring to fig. 1, the conductive layer 14 looks like a zigzag stripe, and the molding region 13 and the non-molding region 15 are separated from each other by the zigzag stripe.

Fig. 2 shows a semiconductor device package 2 according to an embodiment of the present disclosure. Specifically, the semiconductor device package 2 may have a molding region 23 and a non-molding region 25. As used herein, the term "molding region" may refer to a region covered by a molding material (e.g., a region of a substrate), and the term "non-molding region" may refer to a region or space substantially free of a molding material (e.g., a region of a substrate). Referring to fig. 2, the semiconductor device package 2 may include a carrier 20. The carrier 20 has an upper surface 21. An encapsulating material 231 may be disposed on the upper surface 21 of the carrier 20. A die 233 and a component 235 (e.g., an electronic component such as a passive electronic component) are disposed on the upper surface 21 of the carrier 20 and are covered by an encapsulation material 231. As shown in fig. 2, the molding region 23 is a region covered by the encapsulating material 231. Further, referring to fig. 2, a certain area of the upper surface 21 of the carrier 20 is exposed from the encapsulant 231 (e.g., substantially free of the encapsulant 231). The region exposed from the encapsulation material 231 is the non-molding region 25. In the non-molding region 25, substantially no encapsulation material 231 is disposed on the upper surface 21 of the carrier 20, and the die 251 and the component 253 disposed on the upper surface 21 of the carrier 20 are not covered by the encapsulation material 231 and are thus exposed. In addition, a connector may be disposed on the upper surface 21 of the carrier 20 and may be left uncovered by the encapsulating material 231 (not shown), wherein the connector may be electrically connected to an external component through a flexible printed circuit board (FPC board). Furthermore, a conductive layer 24 is arranged on the upper surface 21 of the carrier 20. Conductive layer 24 may include a stop layer or a stop layer and a barrier layer. The conductive layer 24 may be positioned substantially at and/or extend along the interface between the molding region 23 and the non-molding region 25. That is, the conductive layer 24 may be positioned substantially between the molding region 23 and the non-molding region 25. Referring to fig. 2, both ends of the conductive layer 24 are positioned at two adjacent sides 201, 202, respectively, of the carrier 20. Thus, the non-molding region 25 is positioned substantially at the corner of the upper surface 21 of the carrier 20.

Fig. 3 shows a semiconductor device package 3 according to an embodiment of the present disclosure. Specifically, the semiconductor device package 3 may have a molding region 33 and a non-molding region 35. As used herein, the term "molding region" may refer to a region covered by a molding material (e.g., a region of a substrate), and the term "non-molding region" may refer to a region or space substantially free of a molding material (e.g., a region of a substrate). Referring to fig. 3, the semiconductor device package 3 may include a carrier 30. The carrier 30 has an upper surface 31. An encapsulating material 331 may be disposed on the upper surface 31 of the carrier 30. A die 333 and a component 335 (e.g., an electronic component such as a passive electronic component) are disposed on the upper surface 31 of the carrier 30 and are covered by an encapsulation material 331. As shown in fig. 3, the area covered by the encapsulating material 331 is the molding area 33. Further, referring to fig. 3, a certain area of the upper surface 31 of the carrier 30 is exposed from the encapsulating material 331 (e.g., substantially free of the encapsulating material 331). The region exposed from the encapsulating material 331 is the non-molding region 35. In non-molding region 35, substantially no encapsulation material 331 is disposed on upper surface 31 of carrier 30, and die 351 and component 353 disposed on upper surface 31 of carrier 30 are not covered by encapsulation material 331 and are therefore exposed. Furthermore, a conductive layer 34 is arranged on the upper surface 31 of the carrier 30. Conductive layer 34 may include a stop layer or a stop layer and a barrier layer. Conductive layer 34 may be positioned substantially at and/or extend along the interface between molding region 33 and non-molding region 35. That is, conductive layer 34 may be positioned substantially between molding region 33 and non-molding region 35. Referring to fig. 3, the conductive layer 34 has a ring shape. Thus, the non-molding region 35 is substantially surrounded by the molding region 33.

Fig. 4A, 4B, 4C, 4D, 4E, and 4F illustrate a method of manufacturing a semiconductor device package 4 (as shown in fig. 4F) according to an embodiment of the present disclosure. As shown in fig. 4A, the carrier 41 has an upper surface 411 and two recesses 410 formed in the upper surface 411. The carrier 41 may have a recessed surface 412 that is recessed relative to the upper surface 411 (e.g., that defines the bottom of the recess 410). The stop layers 42 may be respectively received within the recesses 410 and may thus be respectively disposed on the recessed surfaces 412. In other words, the stop layer 42 may be embedded in the carrier 41. A barrier layer 43 may be disposed on stop layer 42 and may protrude from upper surface 411 of carrier 41. The barrier layer 43 and the stop layer 42 may be integrated with each other. Further, stop layer 42 and barrier layer 43 may be made of the same material. Referring to fig. 4A, the stop layer 42 has a cross-sectional width greater than the cross-sectional width of the barrier layer 43. In particular, the combination of stop layer 42 and barrier layer 43 may be substantially in the shape of an inverted T. At least two electronic components 481, 482 are disposed on the upper surface 411 of the carrier 41.

As shown in fig. 4A, barrier layer 43 may have a side surface 431 connected to upper surface 421 of stop layer 42. Furthermore, a space may exist between side surface 431 of barrier layer 43 and carrier 41. In addition, the barrier layer 43 may further have a side surface 432 opposite the side surface 431. At least a portion of the side surface 432 may be substantially attached to the carrier 41. Furthermore, the portion of the upper surface 411 of the carrier 41 positioned between the recesses 410 may further comprise a wetting layer 49.

Further, referring to fig. 4B, glue is dispensed on the portion of the upper surface 411 of the carrier 41 located between the recesses 410. Since the barrier layer 43 protrudes from the upper surface 411 of the carrier 41, the glue will not flow across the barrier layer 43. That is, a removable/sacrificial layer 47 will be formed between barrier layers 43. Furthermore, glue may flow into the space between the side surface 431 of the barrier layer 43 and the carrier 41. In addition, since the portion of the upper surface 411 of the carrier 41 between the recesses 410 may further comprise the wetting layer 49, the glue will be distributed smoothly and eventually the removable/sacrificial layer 47 will be formed uniformly between the barrier layers 43.

Referring to fig. 4C, an encapsulation material 40 is disposed on carrier 41 and encapsulates upper surface 411 of carrier 41, stop layer 42, barrier layer 43, removable/sacrificial layer 47, and components 481, 482. That is, encapsulation material 40 covers upper surface 411 of carrier 41, stop layer 42, barrier layer 43, removable/sacrificial layer 47, and components 481 and 482.

Referring to fig. 4D, a portion of the encapsulation material 40 is removed by a laser process and thus a portion of the barrier layer 43 is exposed. Thus, the encapsulating material 40 is divided into three portions 44 and 45, wherein the encapsulating material portion 44 is attached to the upper surface 411 of the carrier 41 and the barrier layer 43, and the encapsulating material portion 45 is attached to the removable/sacrificial layer 47. In particular, when the portion of encapsulating material 40 is removed by the laser process, the laser will impinge on barrier layer 43 or on barrier layer 43 and stop layer 42 and will therefore not damage carrier 41.

Referring to fig. 4E, the removable/sacrificial layer 47 is removed by a physical method or a chemical method (e.g., a water washing process). In addition, the portion of encapsulation material 45 attached to the removable/sacrificial layer 47 is removed (e.g., while the removable/sacrificial layer 47 is removed). After removing the removable/sacrificial layer 47 and the encapsulation material portions 45, the encapsulation material portions 44 remain on the carrier 41 and the portions of the upper surface 411 between the recesses 410 and the wetting layer 49 are exposed. In addition, portions of barrier layer 43 that protrude from upper surface 411 of carrier 41 (e.g., portions of side surfaces 431 that are higher than upper surface 411 of carrier 41) will also be exposed. Further, the encapsulating material portion 44 is arranged on the upper surface 411 of the carrier 41.

As shown in fig. 4E, encapsulant portion 44 may have a side surface 441 on barrier layer 43. In addition, glue may flow into the space between the side surface 431 of the barrier layer 43 and the carrier 41. Accordingly, after removing the removable/sacrificial layer 47, the entire side surface 431 of the barrier layer 43 may be exposed.

Referring to fig. 4F, at least one electronic component 483 is positioned on a portion of the upper surface 411 between the recesses 410. Further, a shielding layer 445 may be formed on the encapsulating material portion 44 and connected to the stop layer 42 and the barrier layer 43. Shield 445 may be grounded through stop layer 42 and barrier layer 43.

Fig. 5A, 5B, 5C, 5D, 5E, and 5F illustrate a method of manufacturing a semiconductor device package 5 (as shown in fig. 5F) according to another embodiment of the present disclosure. As shown in fig. 5A, the carrier 51 has an upper surface 511 and two recesses 510 formed in the upper surface 511. The carrier 51 may have a recessed surface 512 that is recessed relative to the upper surface 511 (e.g., that defines the bottom of the recess 510). The stop layers 52 may be respectively received within the recesses 510 and may thus be respectively disposed on the recessed surfaces 512. In other words, the stop layer 52 may be embedded in the carrier 51. A barrier layer 53 may be disposed on the stop layer 52 and may be caused to protrude from the upper surface 511 of the carrier 51. The barrier layer 53 and the stop layer 52 may be integrated with each other. Further, the stop layer 52 and the barrier layer 53 may be made of the same material. Referring to fig. 5A, the stop layer 52 has a cross-sectional width greater than that of the barrier layer 53. In particular, the combination of stop layer 52 and barrier layer 53 may be substantially L-shaped. At least two electronic components 581, 582 are arranged on the upper surface 511 of the carrier 51.

As shown in fig. 5A, barrier layer 53 has a side surface 531 connected to upper surface 521 of stop layer 52. Furthermore, a space may exist between the side surface 531 of the barrier layer 53 and the carrier 51. In addition, the barrier layer 53 may further have a side surface 532 opposite the side surface 531. At least a portion of the side surface 532 may be substantially attached to the carrier 51. Furthermore, the portion of the upper surface 511 of the carrier 51 positioned between the recesses 510 may further comprise a wetting layer 59.

Further, referring to fig. 5B, glue is dispensed on the portion of the upper surface 511 of the carrier 51 located between the recesses 510. Since the barrier layer 53 protrudes from the upper surface 511 of the carrier 51, the glue will not flow across the barrier layer 53. That is, a removable/sacrificial layer 57 will be formed between barrier layers 53. Furthermore, glue may flow into the space between the side surface 531 of the barrier layer 53 and the carrier 51. In addition, since the portion of the upper surface 511 of the carrier 51 between the recesses 510 may further comprise the wetting layer 59, the glue will be distributed smoothly and eventually the removable/sacrificial layer 57 will be formed uniformly between the barrier layers 53.

Referring to fig. 5C, an encapsulant material 50 is disposed on carrier 51 and encapsulates the upper surface 511 of carrier 51, stop layer 52, barrier layer 53, removable/sacrificial layer 57, and components 581, 582. That is, the encapsulating material 50 covers the upper surface 511 of the carrier 51, the stop layer 52, the barrier layer 53, the removable/sacrificial layer 57, and the components 581, 582.

Referring to fig. 5D, a portion of the encapsulation material 50 is removed by a laser process and thus a portion of the barrier layer 53 is exposed. Thereby, the encapsulation material 50 is divided into three portions 54 and 55, wherein the encapsulation material portion 54 is attached to the upper surface 511 of the carrier 51 and the barrier layer 53, and the encapsulation material portion 55 is attached to the removable/sacrificial layer 57. In particular, when the portion of the encapsulating material 50 is removed by the laser process, the laser will impinge on the barrier layer 53 or on the barrier layer 53 and the stop layer 52 and will not damage the carrier 51.

Referring to fig. 5E, the removable/sacrificial layer 57 is removed by a physical method or a chemical method (e.g., a water washing process). In addition, the portion of encapsulation material 55 attached to the removable/sacrificial layer 57 is removed (e.g., while the removable/sacrificial layer 57 is removed). After removing the removable/sacrificial layer 57 and the encapsulation material portions 55, the encapsulation material portions 54 remain on the carrier 51 and the portions of the upper surface 511 between the recesses 510 and the wetting layer 59 are exposed. In addition, portions of barrier layer 53 that protrude from upper surface 511 of carrier 51 (e.g., portions of side surfaces 531 that are higher than upper surface 511 of carrier 51) will also be exposed. Further, an encapsulating material portion 54 is disposed on the upper surface 511 of the carrier 51.

As shown in fig. 5E, encapsulant portion 54 may have side surfaces 541 on barrier layer 53. In addition, glue may flow into the space between the side surface 531 of the barrier layer 53 and the carrier 51. Accordingly, after removing the removable/sacrificial layer 57, the entire side surface 531 of the barrier layer 53 may be exposed.

Referring to fig. 5F, at least one electronic component 583 is disposed on a portion of the upper surface 511 between the recesses 510.

Fig. 6A, 6B, 6C, 6D, 6E, and 6F illustrate a method of manufacturing a semiconductor device package 6 (as shown in fig. 6F) according to another embodiment of the present disclosure. As shown in fig. 6A, the carrier 61 has an upper surface 611 and two recesses 610 formed in the upper surface 611. Carrier 61 may have a recessed surface 612 that is recessed relative to upper surface 611 (e.g., which defines the bottom of recess 610). The stop layers 62 may be respectively received within the recesses 610 and may thus be respectively disposed on the recessed surfaces 612. In other words, the stop layer 62 may be embedded in the carrier 61. A barrier layer 63 may be arranged on the stop layer 62 and may protrude from the upper surface 611 of the carrier 61. Further, the stop layer 62 may be a pad and the barrier layer 63 may be composed of a solder ball. Referring to fig. 6A, the stop layer 62 has a cross-sectional width greater than the maximum cross-sectional width of the barrier layer 63. At least two electronic components 681, 682 are disposed on the upper surface 611 of the carrier 61.

As shown in fig. 6A, the barrier layer 63 has a side surface 631 connected to the upper surface 621 of the stop layer 62. Furthermore, there may be a space between the side surface 631 of the barrier layer 63 and the carrier 61. Furthermore, the portion of the upper surface 611 of the carrier 61 positioned between the recesses 610 may further comprise a wetting layer 69.

Further, referring to fig. 6B, glue is dispensed on the portion of the upper surface 611 of the carrier 61 located between the recesses 610. Since the barrier layer 63 protrudes from the upper surface 611 of the carrier 61, the glue will not flow across the barrier layer 63. That is, a removable/sacrificial layer 67 will be formed between barrier layers 63. Furthermore, glue may flow into the space between the side surface 631 of the barrier layer 63 and the carrier 61. In addition, since the portion of the upper surface 611 of the carrier 61 between the recesses 610 may further comprise the wetting layer 69, the glue will be distributed smoothly and eventually the removable/sacrificial layer 67 will be formed uniformly between the barrier layers 63.

Referring to fig. 6C, an encapsulation material 60 is disposed on the carrier 61 and encapsulates the upper surface 611 of the carrier 61, the stop layer 62, the barrier layer 63, the removable/sacrificial layer 67, and the components 681, 682. That is, the encapsulation material 60 covers the upper surface 611 of the carrier 61, the stop layer 62, the barrier layer 63, the removable/sacrificial layer 67, and the components 681, 682.

Referring to fig. 6D, a portion of the encapsulation material 60 is removed by a laser process and thus a portion of the barrier layer 63 is exposed. Thereby, the encapsulating material 60 is divided into three portions 64 and 65, wherein the encapsulating material portion 64 is attached to the upper surface 611 of the carrier 61 and the barrier layer 63, and the encapsulating material portion 65 is attached to the removable/sacrificial layer 67. In particular, when the portion of encapsulating material 60 is removed by the laser process, the laser will impinge on barrier layer 63 or on barrier layer 63 and stop layer 62 and will not damage carrier 61.

Referring to fig. 6E, the removable/sacrificial layer 67 is removed by a physical method or a chemical method (e.g., a water washing process). In addition, the portion of encapsulation material 65 attached to the removable/sacrificial layer 67 is removed (e.g., while the removable/sacrificial layer 67 is removed). After removal of removable/sacrificial layer 67 and encapsulation material portions 65, encapsulation material portions 64 remain on carrier 61, and the portions of upper surface 611 between recesses 610 and wetting layer 69 are exposed. In addition, the portion of barrier layer 63 that protrudes from upper surface 611 of carrier 61 (e.g., the portion of side surface 631 that is higher than upper surface 611 of carrier 61) will also be exposed. Further, the encapsulating material portion 64 is disposed on the upper surface 611 of the carrier 61.

As shown in fig. 6E, encapsulant portion 64 may have a side surface 641 on barrier layer 63. In addition, glue may flow into the space between side surface 631 of barrier layer 63 and carrier 61. Accordingly, after removing the removable/sacrificial layer 67, the entire side surface 631 of the barrier layer 63 may be exposed.

Referring to fig. 6F, at least one electronic component 683 is positioned on the portion of the upper surface 611 between the recesses 610.

Fig. 7A, 7B, 7C, 7D, 7E, and 7F illustrate a method of manufacturing a semiconductor device package 7 (as shown in fig. 7F) according to an embodiment of the present disclosure. As shown in fig. 7A, the carrier 71 has an upper surface 711 and two recesses 710 formed in the upper surface 711. The carrier 71 has a recessed surface 712 that is recessed relative to the upper surface 711 (e.g., that defines the bottom of the recess 710). The stop layers 72 may be respectively received within the recesses 710 and may thus be respectively disposed on the recessed surfaces 712. In other words, the stop layer 72 may be embedded in the carrier 71. A barrier layer 73 may be disposed on the stop layer 72. The barrier layer 73 and the stop layer 72 may be integrated with each other. Barrier layer 73 has a top surface 733 that may be substantially coplanar with upper surface 711 of carrier 71. Further, the stop layer 72 and the barrier layer 73 may be made of the same material. Referring to fig. 7A, the stop layer 72 has a cross-sectional width greater than the cross-sectional width of the barrier layer 73. In particular, the combination of stop layer 72 and barrier layer 73 may be substantially in the shape of an inverted T. On the upper surface 711 of the carrier 71 at least two electronic components 781, 782 are arranged.

As shown in fig. 7A, barrier layer 73 has a side surface 731 connected to upper surface 721 of stop layer 72. Further, a space may exist between side surface 731 of barrier layer 73 and carrier 71. In addition, barrier layer 73 may further have a side surface 732 opposite side surface 731. Side surface 732 may be substantially attached to carrier 71. Furthermore, the portion of the upper surface 711 of the carrier 71 positioned between the recesses 710 may further comprise a wetting layer 79.

Further, referring to fig. 7B, glue is dispensed on the portion of the upper surface 711 of the carrier 71 between the recesses 710. The glue will flow into the space between the side surface 731 of the barrier layer 73 and the carrier 71 and, therefore, the glue will not flow across the barrier layer 73. That is, a removable/sacrificial layer 77 will be formed between barrier layers 73. In addition, since the portion of the upper surface 711 of the carrier 71 between the recesses 710 may further comprise the wetting layer 79, the glue will be distributed smoothly and eventually the removable/sacrificial layer 77 will be formed uniformly between the barrier layers 73.

Referring to fig. 7C, an encapsulant material 70 is disposed on carrier 71 and encapsulates the upper surface 711 of carrier 71, stop layer 72, barrier layer 73, removable/sacrificial layer 77, and components 781, 782. That is, encapsulation material 70 covers upper surface 711 of carrier 71, stop layer 72, barrier layer 73, removable/sacrificial layer 77, and components 781, 782.

Referring to fig. 7D, a portion of encapsulation material 70 is removed by a laser process and thus a portion of barrier layer 73 is exposed. Thus, the encapsulation material 70 is divided into three portions 74 and 75, wherein the encapsulation material portion 74 is attached to the upper surface 711 of the carrier 71 and the barrier layer 73, and the encapsulation material portion 75 is attached to the removable/sacrificial layer 77. In particular, when the portion of encapsulating material 70 is removed by the laser process, the laser will impinge on barrier layer 73 or on barrier layer 73 and stop layer 72 and will not damage carrier 71.

Referring to fig. 7E, the removable/sacrificial layer 77 is removed by a physical method or a chemical method (e.g., a water washing process). In addition, the portion of the encapsulation material 75 attached to the removable/sacrificial layer 77 is removed (e.g., while the removable/sacrificial layer 77 is removed). After removing the removable/sacrificial layer 77 and the encapsulation material portions 75, the encapsulation material portions 74 remain on the carrier 71 and the portions of the upper surface 711 between the recesses 710 and the wetting layer 79 are exposed. In addition, side surface 731 of barrier layer 73 will also be exposed. Encapsulant portion 74 is disposed on upper surface 711 of carrier 71 and top surface 733 of barrier layer 73. In particular, as shown in fig. 7E, encapsulant portion 74 may have side surfaces 741 on top surface 733 of barrier layer 73.

Referring to fig. 7F, at least one electronic component 783 is disposed on a portion of the upper surface 711 between the recesses 710.

Fig. 8A, 8B, 8C, 8D, 8E, and 8F illustrate a method of manufacturing a semiconductor device package 8 (as shown in fig. 8F) according to an embodiment of the present disclosure. As shown in fig. 8A, the carrier 81 has an upper surface 811 and two recesses 810 formed in the upper surface 811. Carrier 81 may have a recessed surface 812 that is recessed relative to upper surface 811 (e.g., that defines the bottom of recess 810). The stop layers 82 may be respectively received within the recesses 810 and may thus be respectively disposed on the recessed surfaces 812. In other words, the stop layer 82 may be embedded in the carrier 81. Barrier layers 83 and 85 may be disposed on stop layer 82. The barrier layers 83 and 85 and the stop layer 82 may be integrated with each other. Recess 810 has two opposing side surfaces 813, 815 that are connected to upper surface 811 of carrier 81. Side surfaces 813, 815 of recess 810 are located on barrier layers 83, 85, respectively. That is, top surfaces 833, 853 of barrier layers 83, 85 are recessed relative to upper surface 811 of carrier 81. Further, the stop layer 82 and the barrier layers 83, 85 may be made of the same material. Referring to fig. 8A, barrier layers 83 and 85 may be disposed adjacent to two opposite sides of stop layer 82, respectively, and thus the combination of stop layer 82 and barrier layers 83 and 85 may be substantially U-shaped. At least two electronic components 881, 882 are disposed on an upper surface 811 of the carrier 81. Furthermore, the portion of the upper surface 811 of the carrier 81 positioned between the recesses 810 may further comprise a wetting layer 89.

Further, referring to fig. 8B, glue is dispensed on the portion of the upper surface 811 of the carrier 81 located between the recesses 810. The glue will flow into the recess 810 but will not flow across the barrier layer 83. That is, a removable/sacrificial layer 87 will be formed between barrier layers 83. In addition, since the portion of the upper surface 811 of the carrier 81 between the recesses 810 may further comprise the wetting layer 89, the glue will be distributed smoothly and eventually the removable/sacrificial layer 87 will be formed evenly between the barriers 83.

Referring to fig. 8C, an encapsulation material 80 is disposed on carrier 81 and encapsulates upper surface 811 of carrier 81, stop layer 82, barrier layers 83, 85, removable/sacrificial layer 87, and components 881, 882. That is, encapsulation material 80 covers upper surface 811 of carrier 81, stop layer 82, barrier layer 83, removable/sacrificial layer 87, and components 881, 882.

Referring to fig. 8D, a portion of the encapsulation material 80 is removed by a laser process and thus a portion of the barrier layer 83 is exposed. Thus, the encapsulating material 80 is divided into three portions 84 and 85, wherein the encapsulating material portion 84 is attached to the upper surface 811 of the carrier 81 and the barrier layer 83, and the encapsulating material portion 85 is attached to the removable/sacrificial layer 87. In particular, when the portion of the encapsulating material 80 is removed by the laser process, the laser will impinge on the barrier layer 83 or on the barrier layer 83 and the stop layer 82 and will not damage the carrier 81.

Referring to fig. 8E, the removable/sacrificial layer 87 is removed by a physical method or a chemical method (e.g., a water washing process). In addition, the portion of encapsulation material 85 attached to the removable/sacrificial layer 87 is removed (e.g., while the removable/sacrificial layer 87 is removed). After removing removable/sacrificial layer 87 and encapsulation material portion 85, encapsulation material portion 84 remains on carrier 81 and the portions of upper surface 811 between recesses 810 and wetting layer 89 are exposed. In addition, portions of the barrier layers 83, 85 will also be exposed. Further, an encapsulating material portion 84 is disposed on the upper surface 811 of the carrier 81.

As shown in fig. 8E, the encapsulant portion 84 may have a side surface 841 located on the barrier layer 83. Further, the encapsulating material portion 84 may cover the side surface 813 of the recess 810. Barrier layer 83 has side surfaces 831, and barrier layer 85 has side surfaces 851 opposite side surfaces 831. Both side surfaces 831, 851 are exposed.

Referring to fig. 8F, at least one electronic component 883 is disposed on a portion of the upper surface 81 between the recesses 810.

Fig. 9A, 9B, 9C, 9D, 9E, and 9F illustrate a method of manufacturing a semiconductor device package 9 (as shown in fig. 9F) according to an embodiment of the present disclosure. As shown in fig. 9A, the carrier 91 has an upper surface 911 and two recesses 910 formed in the upper surface 911. The carrier 91 may have a recessed surface 912 that is recessed relative to the upper surface 911 (e.g., which defines the bottom of the recess 910). The stop layers 92 may be respectively received within the recesses 910 and may thus be respectively disposed on the recessed surfaces 912. In other words, the stop layer 92 is embedded in the carrier 91. The recess 910 has two opposite side surfaces 913, 914 connected to the upper surface 911 of the carrier 91. The side surfaces 913, 914 of the recess 910 are located on the stop layer 92. That is, the top surface 923 of the stop layer 92 is recessed relative to the upper surface 911 of the carrier 91. The stop layer 92 may have two opposite side surfaces 921 and 922. A distance between the side surface 921 of the stop layer 92 and the side surface 913 of the recess portion 910 may be the same as a distance between the side surface 922 of the stop layer 92 and the side surface 914 of the recess portion 910. At least two electronic components 981, 982 are arranged on an upper surface 911 of the carrier 91. Furthermore, the portion of the upper surface 911 of the carrier 91 positioned between the recesses 910 may further comprise a wetting layer 99.

Further, referring to fig. 9B, glue is dispensed on the portion of the upper surface 911 of the carrier 91 located between the recesses 910. The glue will flow into the recess 910 but will not flow across the recess 910. That is, the removable/sacrificial layer 97 will be formed between the side surfaces 913 of the recess 910. In addition, since the portion of the upper surface 911 of the carrier 91 between the recesses 910 may further comprise the wetting layer 99, the glue will be distributed smoothly and eventually the removable/sacrificial layer 97 will be formed uniformly between the recesses 910.

Referring to fig. 9C, an encapsulant material 90 is disposed on the carrier 91 and encapsulates the upper surface 911 of the carrier 91, the stop layer 92, the removable/sacrificial layer 97, and the components 981, 982. That is, the encapsulation material 90 covers the upper surface 911 of the carrier 91, the stop layer 92, the removable/sacrificial layer 97, and the components 981, 982.

Referring to fig. 9D, a portion of the encapsulation material 90 is removed by a laser process and thus a portion of the stop layer 92 is exposed. In particular, when removing portions of encapsulation material 90, the laser may contact a portion of carrier 91, and thus side surface 913' of carrier 91 will be damaged. Thereby, the encapsulation material 90 is divided into three portions 94 and 95, wherein the encapsulation material portion 94 is attached to the upper surface 911 of the carrier 91 and the encapsulation material portion 95 is attached to the removable/sacrificial layer 97.

Referring to fig. 9E, the removable/sacrificial layer 97 is removed by a physical method or a chemical method (e.g., a water washing process). In addition, the portion of encapsulation material 95 attached to the removable/sacrificial layer 97 is removed (e.g., while the removable/sacrificial layer 97 is removed). After removal of the removable/sacrificial layer 97 and the encapsulation material portions 95, the encapsulation material portions 94 remain on the carrier 91 and the portions of the upper surface 911 between the recesses 910 and the wetting layer 99 are exposed. In addition, portions of barrier layer 92 will also be exposed. Furthermore, an encapsulating material portion 94 is arranged on the upper surface 911 of the carrier 91.

As described above, the laser may contact a portion of the carrier 91 and the side surface 913 'of the concave portion 910 will be damaged, and thus, the encapsulation material portion 94 may have a side surface 941, which may be coplanar with the damaged side surface 913' of the concave portion 910. Further, since the side surface 913 'of the concave portion 910 is damaged by the laser, the roughness of the damaged side surface 913' of the concave portion may be greater than that of the side surface 914 of the concave portion 910. In addition, a distance between the side surface 921 of the stop layer 92 and the damaged side surface 913' of the recess portion 910 may be smaller than a distance between the side surface 922 of the stop layer 92 and the side surface 914 of the recess portion 910. The angle θ 1 between the upper surface 911 of the carrier 91 and the damaged side surface 913' of the recess 910 may be larger than 90 degrees and also larger than the angle θ 2 between the upper surface 911 of the carrier 91 and the side surface 914 of the recess 910.

Referring to fig. 9F, at least one electronic component 983 is disposed on a portion of the upper surface 911 between the recesses 910.

As used herein, the terms "about," "substantially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms may refer to the exact instance in which the event or circumstance occurs, as well as the instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the terms can refer to a range of variation of less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%.

For example, substantially parallel may refer to a range of angular variation of less than or equal to ± 10 ° relative to 0 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, substantially perpendicular may refer to a range of angular variation of less than or equal to ± 10 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 ° relative to 90 °.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface may be considered substantially flat if the displacement between the highest and lowest points of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular forms "a" and "the" may include plural referents unless the context clearly dictates otherwise.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such a range format is used for convenience and brevity, and should be interpreted flexibly to include numerical values explicitly recited as the limits of the range, as well as to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and drawings are not to be considered in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the disclosure as defined by the claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic renditions in this disclosure and actual devices. There may be other embodiments of the disclosure that are not specifically shown. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or rearranged to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless expressly stated herein, the order and grouping of the operations is not a limitation of the present disclosure.