阅读说明：本技术 一种芯片封装体及其制程方法和电子装置 (Chip package, manufacturing method thereof and electronic device ) 是由 霍佳仁 宋关强 江京 刘建辉 于 2020-09-25 设计创作，主要内容包括：本申请公开了一种芯片封装体及其制程方法和电子装置,其中,该芯片封装体包括：图案化的金属基材板,其中,金属基材板中设置有第一通孔；芯片,设置在第一通孔中；第一绝缘层,覆盖在芯片和金属基材板上,并填充所述第一通孔,其中,第一绝缘层中设置有第二通孔以裸露出部分的金属基材板和芯片；图案化的第一导电层,设置在第一绝缘层上和通孔内,以使芯片藉由第一导电层而连接至金属基材板。通过上述方式,本申请中的芯片封装体能够实现芯片的双面散热,且结构较为简单,电气路径和散热路径短,具有优异的低阻特性和散热效果,能够实现芯片封装体的小型化和轻薄化。(The application discloses a chip packaging body, a manufacturing method thereof and an electronic device, wherein the chip packaging body comprises: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.)

1. A chip package, comprising:

a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate;

a chip disposed in the first through hole;

a first insulating layer covering the chip and the metal base plate and filling the first through hole, wherein a second through hole is provided in the first insulating layer to expose a portion of the metal base plate and the chip;

a patterned first conductive layer disposed on the first insulating layer and within the via such that the chip is connected to the metal substrate board by the first conductive layer.

2. The chip package of claim 1,

a patterned second conductive layer is further arranged between the first insulating layer and the overlapped part of the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.

3. The chip package of claim 1,

the chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface of one side, far away from the first conductive layer, of the metal substrate plate and the surface of one side, with the horizontal plane, of the chip and the first insulating layer.

4. The chip package of claim 1,

the chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.

5. The chip package of claim 1,

the bottom area of the chip is smaller than that of the first through hole and is not in direct contact with the metal substrate plate.

6. A manufacturing method of a chip package is characterized by comprising the following steps:

forming a first through hole in a metal base material plate, and attaching a support substrate to the bottom of the metal base material plate;

disposing a chip on the support substrate in the first through hole;

forming a first insulating layer on the metal base material plate and the chip to cover the chip and the metal base material plate and fill the first through hole;

removing the support substrate;

patterning the first insulating layer to form a patterned first insulating layer, wherein a second through hole is provided in the patterned first insulating layer to expose a portion of the metal base plate and the chip;

forming a first conductive layer on the patterned first insulating layer, and filling the first conductive layer in the second through hole;

patterning the first conductive layer to form a patterned first conductive layer;

patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer.

7. The process of claim 6, wherein after the step of removing the supporting substrate, the step of patterning the first insulating layer to form a patterned first insulating layer, wherein the step of providing the patterned first insulating layer with the second via to expose a portion of the metal substrate plate and the chip further comprises:

forming a second conductive layer on the first insulating layer;

the patterning the first insulating layer to form a patterned first insulating layer, wherein the patterning the first insulating layer has a second through hole provided therein to expose portions of the metal substrate board and the chip, and the patterning includes:

patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein second through holes are provided in the patterned first insulating layer and the patterned second conductive layer to expose portions of the metal substrate board and the chip;

the step of forming a first conductive layer on the patterned first insulating layer and filling the second through holes with the first conductive layer comprises:

forming a first conductive layer on the patterned first insulating layer and the patterned second conductive layer, and filling the first conductive layer in the second through hole;

the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer comprises:

patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned second conductive layer and the patterned metal substrate plate by the patterned first conductive layer.

8. The process of claim 6, wherein the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises:

and forming a conductive metal layer on the surface of the patterned metal substrate plate on the side far away from the first insulating layer and the surface of the chip and the first insulating layer on the same horizontal plane side.

9. The process of claim 6, wherein the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises:

and forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

10. An electronic device comprising the chip package according to any one of claims 1-5.

Technical Field

The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip package, a method for manufacturing the chip package, and an electronic device.

Background

In recent years, with the application of Mosfet (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as Mosfet) and IGBT (Insulated Gate Bipolar Transistor) power modules to almost all power industry products, corresponding power devices are steadily developing in the direction of high performance, high speed, small volume and multi-chip connection packaging.

However, conventional wire bonding and double-sided copper interconnect processes and process methods have been increasingly difficult to meet the requirements of high performance, fast speed, small volume, multi-chip connection packaging and modularization of power devices. The power semiconductor packaging process needs to be developed towards a more excellent packaging mode of a PLFO (sheet level Fan out) process.

Disclosure of Invention

The application provides a chip package, a manufacturing method thereof and an electronic device, which are used for solving the problem that the chip package in the prior art cannot achieve the technical effects of miniaturization, lightness and thinness and excellent electrical and heat dissipation characteristics.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a chip package, wherein the chip package includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal base material plate and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal base material plate and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer.

And a patterned second conductive layer is arranged between the overlapped parts of the first insulating layer and the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.

The chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface of one side, far away from the first conductive layer, of the metal substrate board and the surface of one side, with the same horizontal plane, of the chip and the first insulating layer.

The chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.

The bottom area of the chip is smaller than that of the first through hole and is not in direct contact with the metal substrate plate.

In order to solve the above technical problem, the present application adopts another technical solution: a method for manufacturing a chip package is provided, wherein the method comprises: forming a first through hole in the metal base material plate, and attaching a support substrate to the bottom of the metal base material plate; disposing a chip on the support substrate in the first through hole; forming a first insulating layer on the metal base material plate and the chip to cover the chip and the metal base material plate and fill the first through hole; removing the support substrate; patterning the first insulating layer to form a patterned first insulating layer, wherein a second through hole is provided in the patterned first insulating layer to expose a portion of the metal base plate and the chip; forming a first conductive layer on the patterned first insulating layer, wherein the first conductive layer is filled in the second through hole; patterning the first conductive layer to form a patterned first conductive layer; the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer.

Wherein, after the step of removing the supporting substrate, the first insulating layer is patterned to form a patterned first insulating layer, wherein the step of providing the second through hole in the patterned first insulating layer to expose part of the metal substrate plate and the chip further comprises: forming a second conductive layer on the first insulating layer; patterning the first insulating layer to form a patterned first insulating layer, wherein the patterned first insulating layer is provided with a second through hole to expose a portion of the metal substrate board and the chip, and the step of patterning the first insulating layer includes: patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein second through holes are formed in the patterned first insulating layer and the patterned second conductive layer to expose parts of the metal substrate board and the chip; the step of forming a first conductive layer on the patterned first insulating layer and filling the second through hole with the first conductive layer includes: forming a first conductive layer on the patterned first insulating layer and the patterned second conductive layer, wherein the first conductive layer is filled in the second through hole; the step of patterning the metal substrate plate to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer comprises: the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned second conductive layer and the patterned metal substrate plate by the patterned first conductive layer.

Wherein the step of patterning the metal substrate plate to form the patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises: and forming a conductive metal layer on the surface of the patterned metal substrate plate at the side far away from the first insulating layer and at the side of the chip and the first insulating layer at the same level with the chip.

Wherein the step of patterning the metal substrate plate to form the patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer further comprises: and forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

In order to solve the above technical problem, the present application adopts another technical solution: there is provided an electronic device, wherein the electronic device comprises a chip package as defined in any one of the above.

The beneficial effect of this application is: unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application;

FIG. 2 is a schematic structural diagram of a second embodiment of a chip package according to the present application;

FIG. 3 is a schematic structural diagram of a third embodiment of a chip package according to the present application;

FIG. 4 is a schematic structural diagram of a fourth embodiment of a chip package according to the present application;

fig. 5 is a schematic structural diagram of a fifth embodiment of the chip package of the present application;

FIG. 6a is a schematic flow chart illustrating a method of fabricating a chip package according to a first embodiment of the present invention;

FIGS. 6 b-6 i are schematic structural diagrams of an embodiment corresponding to S610-S680 in FIG. 6 a;

FIG. 7a is a flow chart illustrating a method of fabricating a chip package according to a second embodiment of the present invention;

FIGS. 7 b-7 f are schematic structural diagrams of an embodiment corresponding to S750-S790 in FIG. 7 a;

FIG. 8a is a flow chart illustrating a third embodiment of a method for fabricating a chip package according to the present invention;

FIG. 8b is a schematic structural diagram of an embodiment corresponding to S890 in FIG. 8 a;

FIG. 9a is a schematic flow chart illustrating a fourth exemplary method of fabricating a chip package according to the present invention;

FIG. 9b is a schematic structural diagram of an embodiment corresponding to S990 in FIG. 9 a;

fig. 10 is a schematic structural diagram of an embodiment of an electronic device according to the present application.

Detailed Description

In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application.

In the present embodiment, the chip package includes the patterned metal base material plate 12, the chip 22, the first insulating layer 32, and the patterned first conductive layer 42. The chip package comprises a metal substrate 12, a chip 22, a first insulating layer 32, a first conductive layer 42, a second conductive layer 42, a first through hole, a chip 22, a second through hole, a first insulating layer 32, a second conductive layer 42 and a second conductive layer 42, wherein the metal substrate 12 is provided with the first through hole, the chip 22 is provided with the first through hole, the first insulating layer 32 is provided with the second through hole to expose a portion of the metal substrate 12 and the chip 22, the first conductive layer 42 is provided with the first conductive layer and the second through hole, the chip 22 is electrically connected with the metal substrate 12 through the first conductive layer 42, and the first through hole and the second through hole are finally formed as a pin of the chip package.

The number of the through holes in the first insulating layer 32 includes at least two, at least one through hole is disposed above the chip 22, at least another through hole is correspondingly disposed on the metal substrate 12, and the at least two through holes are electrically connected to each other through the first conductive layer 42 covering the inside of each through hole. And the part of the structure corresponding to the metal substrate board 12 under the at least two through holes can be used as a package pin of the chip package to electrically connect with an external device or other chips.

The patterning of the metal substrate 12 and the first conductive layer 42 is set to correspond to the logic circuit to be implemented by the chip 22, and the different chip pins correspond to different patterned electrical paths, and the patterning can be performed by chemical etching or ion etching.

Alternatively, the material of the metal substrate 12 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 32 may be one of silicon oxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 42 is selected from one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 22 in the chip package can realize double-sided heat dissipation through the metal substrate 12 and the first conductive layer 42 in the through hole, thereby having more excellent heat dissipation characteristics.

Alternatively, the bottom area of the chip 22 is smaller than the bottom area of the first through hole and is not in direct contact with the metal substrate 12, and the first insulating layer 32 is filled in the remaining portion of the first through hole after the chip 22 is removed, while in other embodiments, the bottom area of the chip 22 may be equal to the bottom area of the first through hole, and the first through hole is completely filled by the chip 22, and the first insulating layer 32 covers the chip 22 and the metal substrate 12, which is not limited in this application.

Alternatively, the surface area of the through hole provided in the first insulating layer 32 on the side facing the metal base plate 12 may be set smaller than the surface area on the side away from the metal base plate 12, that is, the bottom areas of the two sides of the through hole may be set to be different, while in other embodiments, the bottom areas of the two sides of the through hole may also be set to be the same, which is not limited in this application.

Alternatively, the edge portions of the first insulating layer 32 corresponding to the respective through holes may be inclined edges having at least two different inclination angles, or may be disposed in any reasonable structural style such as an arc-shaped curved surface, a wavy curved surface, and the like.

Unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip in the chip package of this application can dispel the heat through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole, thereby make this chip can realize two-sided heat dissipation, and make corresponding chip package's structure simpler, electric route and heat dissipation path are shorter, thereby have excellent low resistance characteristic and radiating effect, and can realize chip package's miniaturization and frivolousization.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package according to a second embodiment of the present application. The present embodiment is different from the first embodiment of the chip package provided in the present application in fig. 1 in that the chip package further includes a patterned second conductive layer 52, wherein the second conductive layer 52 is disposed between the overlapping portions of the first insulating layer 32 and the first conductive layer 42.

In the present embodiment, the second conductive layer 52 is disposed on the portion of the first insulating layer 32 not opened with the through hole, and the chip 22 is connected to the second conductive layer 52 by the first conductive layer and finally connected to the metal substrate 12.

The material used for the second conductive layer 52 is also selected from one of copper, aluminum, gold, silver, tin, lead, and their alloys or metal-filled organics, which is not limited in this application.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a chip package according to a third embodiment of the present application. This embodiment differs from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further comprises a conductive metal layer 62, wherein the conductive metal layer 62 is disposed on the surface of the metal base plate 12 away from the first insulating layer 32, i.e. the conductive metal layer 72 is disposed on the surface of the metal base plate 12 on the other side where the chip 22 is disposed.

In the present embodiment, the conductive metal layer 62 is made of the same material as the metal substrate 12, and is selected from one of copper, aluminum, gold, silver, and their alloys or metal-filled organic substances, and is disposed by thickening and laminating the metal substrate 12 to ensure that the finally formed patterned metal substrate 12, i.e. the corresponding leads of the chip package, have more reliable strength and are not easily bent or broken.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a chip package according to a fourth embodiment of the present application. This embodiment is different from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further includes a second insulating layer 72, wherein the second insulating layer 72 covers the first conductive layer 42 and the partially exposed first insulating layer 32.

In the present embodiment, the patterned first insulating layer 32 is partially exposed and is not completely covered by the first conductive layer 42, wherein the second insulating layer 72 is further disposed in the chip package to cover the first conductive layer 42 and the partially exposed first insulating layer 32, so as to effectively protect the first conductive layer 42 from being damaged by an external force, thereby preventing the logic circuit of the corresponding pin of the chip package from being unable to be effectively implemented due to the external force.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a chip package according to a fifth embodiment of the present application.

Optionally, in an embodiment, the chip package specifically includes: a patterned metal substrate board 12, a chip 22, a first insulating layer 32, a patterned first conductive layer 42, a patterned second conductive layer 52, a conductive metal layer 62, and a second insulating layer 72.

Wherein a first through-hole is provided in the patterned metal base plate 12, and the chip 22 is provided in the first through-hole, and the first insulating layer 32 covers the chip 22 and the metal base material plate 12, the patterned second conductive layer 52 is further disposed on the first insulating layer 32, wherein the first insulating layer 32 and the second conductive layer 52 are provided therein with second through holes to expose portions of the metal base plate 12 and the chip 22, and patterned first conductive layer 42 is disposed on second conductive layer 52 and within the second via, so that the chip 22 can be connected to the patterned second conductive layer 52 and the patterned metal substrate board 12 by the patterned first conductive layer 42 to finally constitute the leads of the chip package, therefore, the chip package has a short electric path and a short heat dissipation path, and has excellent low resistance and heat dissipation effects.

The conductive metal layer 62 is disposed on a surface of the metal substrate 12 away from the first insulating layer 32 and a surface of the chip 22 and the first insulating layer 32 on a same horizontal plane, and the conductive metal layer 62 is a thickened and stacked layer on the metal substrate 12 to ensure that the patterned metal substrate 12 is finally formed, i.e., the corresponding pins of the chip package have more reliable strength, and are not easily bent or broken. The second insulating layer 72 covers the first conductive layer 42 and the partially exposed second conductive layer 52 to effectively protect the first conductive layer 42 and the second conductive layer 52 from being damaged by external force, so as to prevent the logic circuit of the corresponding pin of the chip package from being unable to be effectively implemented due to the external force.

Alternatively, the material of the metal substrate 12 and the conductive metal layer 62 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 32 and the second insulating layer 72 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 42 and the second conductive layer 52 may be one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 22 in the chip package can realize double-sided heat dissipation through the metal substrate 12 and the first conductive layer 42 in the second through hole, thereby having more excellent heat dissipation characteristics.

Alternatively, the bottom area of the chip 22 is smaller than the bottom area of the first through hole and is not in direct contact with the metal substrate 12, and the first insulating layer 32 is filled in the remaining portion of the first through hole after the chip 22 is removed, while in other embodiments, the bottom area of the chip 22 may be equal to the bottom area of the first through hole, and the first through hole is completely filled by the chip 22, and the first insulating layer 32 covers the chip 22 and the metal substrate 12, which is not limited in this application.

Optionally, the insulating material used for the second insulating layer 72 is different from the insulating material used for the first insulating layer 32, and the thermal conductivity of the insulating material used for the second insulating layer 72 is better than that of the insulating material used for the first insulating layer 32, that is, the thermal conductivity of the second insulating layer 72 is higher than that of the first insulating layer 32, so that after the first conductive layer 42 and the second conductive layer 52 are coated, the chip 22 can achieve a better heat dissipation effect through the second insulating layer 72.

Optionally, a solder resist insulating layer is further provided on a side of the chip 22 remote from the metal base material plate 12 to allow only the first conductive layer 42 to be connected to the position corresponding to the pad on the side of the chip 22. The bonding pad is a copper layer portion exposed by a side of the chip 22 that needs to be soldered to electrically connect with an external device, and a non-bonding pad portion on the side of the chip 22 is provided as a solder resist insulating layer.

Optionally, the outermost layer of the chip package, that is, the outer side of the conductive metal layer 62 and the second insulating layer 72, is further provided with an insulating envelope material of any reasonable color, such as black, green or yellow, so as to make the appearance of the chip package more ornamental.

Alternatively, the edge portions of the metal substrate 12 corresponding to the corresponding grooves and the remaining structure after etching may be beveled edges having at least two different angles of inclination, or may be arranged in any reasonable structural pattern such as an arc-shaped curved surface, a wavy curved surface, and the like.

Alternatively, there may be a void at a position where the metal base material plate 12 is connected to the first conductive layer 42, or inside the first conductive layer 42, and the void is further filled with an insulating resin to prevent the entry of air and/or water molecules.

Optionally, the metal substrate 12 is filled with an insulating envelope material of one of any reasonable colors, such as black, green or yellow, at patterned gaps on a side thereof remote from the chip 22, to serve to make the appearance of the chip package more ornamental.

Alternatively, the chip package has a plurality of metal base plates 12 and insulating layers disposed in respective stacks, and interconnection of the plurality of metal base plates 12 is achieved by a plurality of conductive layers in respective through holes.

Optionally, solder balls are further disposed on the side of the metal substrate 12 or the conductive metal layer 62 away from the chip 22 to electrically connect with external devices.

Optionally, a side of the chip package away from the metal substrate 12 is further connected to a power module device, such as one or more of any reasonable power devices, such as a resistor, a capacitor, a transistor, etc., through the first conductive layer 42.

Optionally, at least two chips 22 are disposed on a side of the metal substrate 12 close to the chip 22, and the at least two chips 22 may be electrically connected to each other through the metal substrate 12 and the first conductive layer 42, or the at least two chips 22 are independent of each other and are not electrically connected, which is specifically set by a user according to a circuit logic that the user needs to achieve.

Based on the general inventive concept, the present application further provides a method for manufacturing a chip package, please refer to fig. 6a to 6i, wherein fig. 6a is a schematic flow diagram of a first embodiment of the method for manufacturing a chip package according to the present application, and fig. 6b to 6i are schematic structural diagrams of an embodiment corresponding to S610 to S680 in fig. 6 a. The embodiment comprises the following steps:

s610: a first through hole is formed in the metal base plate, and a support substrate is attached to the bottom of the metal base plate.

Specifically, as shown in fig. 6b, in one embodiment, a first through hole 1210 is first etched in the metal substrate 12 by pattern transfer or chemical etching, and a supporting substrate 82 is attached to the bottom of the metal substrate 12 with the first through hole 1210.

S620: a chip is disposed on the support substrate in the first through hole.

Specifically, as shown in fig. 6c, in an embodiment, when the first through hole 1210 is opened on the metal substrate 12, and the supporting substrate 82 is attached to the bottom of the metal substrate 12, the chip 22 is further attached to a partial area corresponding to the first through hole 1210 on the supporting substrate 82, wherein the bottom area of the chip 22 may be smaller than the bottom area of the first through hole 1210 and is not in direct contact with the metal substrate 12, and in other embodiments, the bottom area of the chip 22 may also be equal to the bottom area of the first through hole 1210, that is, the first through hole 1210 is completely filled with the chip 22, which is not limited in this application.

S630: a first insulating layer is formed on the metal base plate and the chip to cover the chip and the metal base plate and fill the first through hole.

Specifically, as shown in fig. 6d, in one embodiment, after the chip 22 is disposed on the supporting substrate 82 in the first through hole 1210, the first insulating layer 32 is further fabricated and formed on the metal substrate 12 and the chip 22 to completely cover the chip 22 and the metal substrate 12, wherein when the bottom area of the chip 22 is smaller than that of the first through hole 1210 and is not in direct contact with the metal substrate 12, the first insulating layer 32 is further filled into the remaining portion of the first through hole 1210 after the chip 22 is removed.

S640: the support substrate is removed.

Specifically, as shown in fig. 6e, in one embodiment, after the first insulating layer 32 is covered on the metal base plate 12 and the chip 22 and filled in the first through hole 1210, the supporting substrate 82 attached to the bottom of the metal base plate 12 may be removed.

S650: and patterning the first insulating layer to form a patterned first insulating layer, wherein a second through hole is arranged in the patterned first insulating layer to expose part of the metal substrate plate and the chip.

Specifically, as shown in fig. 6f, in an embodiment, the first insulating layer 32 is formed by printing, pressing, spraying, and further, a plurality of second through holes are formed in the first insulating layer 32 by laser drilling or chemical etching, and penetrate through the surfaces of the metal substrate 12 and the chip 22 to expose portions of the metal substrate 12 and the chip 22.

S660: a first conductive layer is formed on the patterned first insulating layer, and the second through holes are filled with the first conductive layer.

Specifically, as shown in fig. 6g, in one embodiment, a second through hole is formed in the patterned first insulating layer 32, and a portion of the metal substrate 12 and the chip 22 are exposed, and further, a first conductive layer 42 is formed on the first insulating layer 32 by printing, pressing, spraying, chemical plating, chemical deposition, or other processing methods, and the first conductive layer 42 is filled on the surface inside the second through hole, so as to achieve corresponding connection between the chip 22 and the metal substrate 12.

S670: the first conductive layer is patterned to form a patterned first conductive layer.

Specifically, as shown in fig. 6h, in one embodiment, the first conductive layer 42 is patterned by chemical etching or ion etching to form a patterned first conductive layer 42.

S680: the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer.

Specifically, as shown in fig. 6i, in one embodiment, a first conductive layer 42 is formed on the first insulating layer 32 and in the second through hole, which are patterned and cover the chip 22 and the metal substrate 12, the first conductive layer 42 is patterned, and the metal substrate 12 is further patterned by chemical etching or ion etching to form the patterned first conductive layer 42 and the metal substrate 12. It will be appreciated that the chip 22 can be connected to the patterned metal substrate board 12 by the patterned first conductive layer 42 in the through hole and on the first insulating layer 32, wherein the patterning process performed on the first insulating layer 32, the first conductive layer 42 and the metal substrate board 12 is adaptively set for achieving the electrical connection of the chip 22 and the metal substrate board 12 and the logic circuit to be achieved, so as to finally constitute the leads of the chip package.

Alternatively, the material of the metal substrate 12 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material of the first insulating layer 32 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 42 is one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 22 in the chip package can realize double-sided heat dissipation through the metal substrate 12 and the first conductive layer 42 in the through hole, thereby having more excellent heat dissipation characteristics.

Different from the prior art, the method for manufacturing the chip package in the present application includes: forming a first through hole in the metal base material plate, and attaching a support substrate to the bottom of the metal base material plate; disposing a chip on the support substrate in the first through hole; forming a first insulating layer on the metal base material plate and the chip to cover the chip and the metal base material plate and fill the first through hole; removing the support substrate; patterning the first insulating layer to form a patterned first insulating layer, wherein a second through hole is provided in the patterned first insulating layer to expose a portion of the metal base plate and the chip; forming a first conductive layer on the patterned first insulating layer, wherein the first conductive layer is filled in the second through hole; patterning the first conductive layer to form a patterned first conductive layer; the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned metal substrate plate by the patterned first conductive layer. In this way, the chip package who obtains in this application can be through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole and dispel the heat, thereby make this chip can realize two-sided heat dissipation, and the structure is comparatively simple, electric route and heat dissipation path are short, have more excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package, and the mode of adopting two-way preparation also makes the process of its whole processing procedure technology can be compatible with the technology of PCB equipment completely, thereby have efficient and the characteristics of high batchization degree, with low costs.

Referring to fig. 7a to 7f, fig. 7a is a flowchart illustrating a method for manufacturing a chip package according to a second embodiment of the present invention, and fig. 7b to 7f are structural diagrams illustrating an embodiment corresponding to S750 to S790 in fig. 7 a. It can be understood that the method for manufacturing the chip package in this embodiment is a flowchart illustrating a detailed implementation of the method for manufacturing the chip package in fig. 6a, and includes the following steps:

s710, S720, S730, and S740 in fig. 7a are the same as S610, S620, S630, and S640 in fig. 6a, respectively, and refer to fig. 6a and the related description thereof, which are not repeated herein, and at S740, after the step of removing the supporting substrate, the method further includes the following steps:

s750: a second conductive layer is formed on the first insulating layer.

Specifically, as shown in fig. 7b, in one embodiment, after disposing the chip 22 in the groove opened on the metal substrate 12 and forming the first insulating layer 32 on the metal substrate 12 on which the chip 22 is disposed to cover the chip 22 and the metal substrate 12, there is further included fabricating a second conductive layer 52 on the first insulating layer 32.

S760: and patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein second through holes are arranged in the patterned first insulating layer and the patterned second conductive layer to expose parts of the metal substrate plate and the chip.

Specifically, as shown in fig. 7c, in one embodiment, the first insulating layer 32 and the second conductive layer 52 formed on the first insulating layer 32 are patterned to obtain the patterned first insulating layer 32 and the patterned second conductive layer 52, and the first insulating layer 32 and the patterned second conductive layer 52 are formed and covered on the chip 22 and the metal substrate 12 provided with the chip 22, and a plurality of second through holes are further formed in the first insulating layer 32 and the second conductive layer 52 by laser drilling or chemical etching and penetrate the surfaces of the metal substrate 12 and the chip 22 to expose the bare portions of the metal substrate 12 and the chip 22.

S770: and forming a first conductive layer on the patterned first insulating layer and the patterned second conductive layer, wherein the first conductive layer is filled in the second through hole.

Specifically, as shown in fig. 7d, in one embodiment, after the patterned first insulating layer 32 and the second conductive layer 52 are provided with through holes and part of the metal substrate 12 and the chip 22 are exposed, the first conductive layer 42 is further fabricated on the first insulating layer 32 and the second conductive layer 52, and the first conductive layer 42 is filled in the second through hole formed in the first insulating layer 32, so as to realize the corresponding connection between the chip 22 and the metal substrate 12.

S780: the first conductive layer is patterned to form a patterned first conductive layer.

Specifically, as shown in fig. 7e, in one embodiment, the first conductive layer 42 is patterned by chemical etching or ion etching to form a patterned first conductive layer 42, and in other embodiments, the second conductive layer 52 may be further patterned to form a vertically uniform patterned first conductive layer 42 and a vertically uniform patterned second conductive layer 52.

S790: the metal substrate plate is patterned to form a patterned metal substrate plate such that the chip is connected to the patterned second conductive layer and the patterned metal substrate plate by the patterned first conductive layer.

Specifically, as shown in fig. 7f, in one embodiment, a first conductive layer 42 is formed on the first insulating layer 32 and the patterned second conductive layer 52 which are patterned and cover the chip 22 and the metal substrate 12, and the first conductive layer 42 is also filled in the second through hole in the first insulating layer 32, the first conductive layer 42 is subjected to patterning, and the metal substrate 12 is further subjected to patterning by chemical etching or ion etching to form the patterned first conductive layer 42 and the metal substrate 12. It will be appreciated that the chip 22 can be connected to the patterned metal substrate 12 by the patterned first conductive layer 42 in the through hole and on the first insulating layer 32 and the second conductive layer 52, wherein the patterning process performed on the first insulating layer 32, the second conductive layer 52, the first conductive layer 42 and the metal substrate 12 is adaptively set for achieving the electrical connection between the chip 22 and the metal substrate 12 and the logic circuit to be achieved, so as to finally constitute the leads of the chip package.

Referring to fig. 8 a-8 b, fig. 8a is a flowchart illustrating a third embodiment of a method for manufacturing a chip package according to the present application, and fig. 8b is a schematic structural diagram of an embodiment corresponding to S890 in fig. 8 a. The process flow of the chip package in this embodiment and fig. 6a is a schematic flow chart of another detailed implementation of the method for manufacturing a chip package, which includes the following steps:

s810, S820, S830, S840, S850, S860, S870, and S880 in fig. 8a are the same as S610, S620, S630, S640, S650, S660, S670, and S680 in fig. 6a, respectively, and refer to fig. 6a and the related description thereof for details, and no further description is given here, but at S880, the metal substrate board is patterned to form a patterned metal substrate board, so that after the step of connecting the chip to the patterned metal substrate board through the patterned first conductive layer, the method further includes the following steps:

s890: and forming a conductive metal layer on the surface of the patterned metal substrate plate at the side far away from the first insulating layer and at the side of the chip and the first insulating layer at the same level with the chip.

Specifically, as shown in fig. 8b, in one embodiment, when the first conductive layer 42 is formed on the first insulating layer 32 and in the second through hole, which are patterned and cover the chip 22 and the metal substrate 12, the first conductive layer 42 is patterned, and the metal substrate 12 is further patterned by chemical etching or ion etching to form the patterned first conductive layer 42 and the metal substrate 12, and after the chip 22 is connected to the patterned metal substrate 12 by the patterned first conductive layer 42, a conductive metal layer 62 is further formed on the surface of the patterned metal substrate 12 on the side away from the first insulating layer 32 and on the surface of the chip 22 and the first insulating layer 32 on the same horizontal plane. In other embodiments, the first conductive layer 42 may be formed on the first insulating layer 32 and the corresponding through hole, which are patterned and covered on the chip 22 and the metal substrate 12, and the first conductive layer 42 is patterned, then a conductive metal layer 62 is formed on the surface of the metal substrate 12 away from the first insulating layer 32, and then the metal substrate 12 and the conductive metal layer 62 are patterned to form the patterned first conductive layer 42, the metal substrate 12 and the conductive metal layer 62, so that the chip 22 is connected to the patterned metal substrate 12 through the patterned first conductive layer 42.

The conductive metal layer 62 is made of the same material as the metal substrate 12, and is selected from one of copper, aluminum, gold, silver, and alloys thereof or metal-filled organic substances, and is formed by thickening and laminating the metal substrate 12 to ensure that the finally formed patterned metal substrate 12, i.e., the corresponding leads of the chip package, have more reliable strength and are not easily bent or broken.

Referring to fig. 9 a-9 b, fig. 9a is a flowchart illustrating a fourth embodiment of a method for manufacturing a chip package according to the present application, and fig. 9b is a structural diagram illustrating an embodiment corresponding to S990 in fig. 9 a. The process flow of the chip package in this embodiment and fig. 6a is a schematic flow chart of another detailed implementation of the method for manufacturing a chip package, which includes the following steps:

s910, S920, S930, S940, S950, S960, S970, and S980 in fig. 9a are the same as S610, S620, S630, S640, S650, S660, S670, and S680 in fig. 6a, respectively, and refer to fig. 6a and the related description thereof for details, and no further description is given here, and at S980, the metal substrate board is patterned to form a patterned metal substrate board, so that after the step of connecting the chip to the patterned metal substrate board through the patterned first conductive layer, the method further includes the following steps:

s990: and forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

Specifically, as shown in fig. 9b, in one embodiment, when the first conductive layer 42 is formed and patterned on the first insulating layer 32 and in the corresponding through hole, which are patterned and covered on the chip 22 and the metal substrate 12, the first conductive layer 42 is patterned, and the metal substrate 12 is further patterned by chemical etching or ion etching to form the patterned first conductive layer 42 and the metal substrate 12, and after the chip 22 is connected to the patterned metal substrate 12 by the patterned first conductive layer 42, the second insulating layer 72 is further formed and covered on the first conductive layer 42 and the partially exposed first insulating layer 32 to effectively protect the first conductive layer 42 from being damaged by external force, so as to effectively prevent the logic circuit of the corresponding pin of the chip package from being effectively disabled by external force And (5) realizing.

Based on the general inventive concept, the present application further provides an electronic device, please refer to fig. 10, where fig. 10 is a schematic structural diagram of an embodiment of the electronic device according to the present application. The electronic device 100 includes any of the chip packages 1010 described above.

Unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.