阅读说明：本技术 半导体结构及其制造方法 (Semiconductor structure and manufacturing method thereof ) 是由 丘世仰 于 2019-11-26 设计创作，主要内容包括：本发明公开了一种半导体结构及其制造方法,半导体结构包括基板、介电层、导电通孔及着陆焊盘。介电层位于基板上。导电通孔从基板的下表面贯穿到介电层的上表面。着陆焊盘嵌入导电通孔中。此半导体结构可以在着陆焊盘和导电通孔之间提供足够的接触面积。(The invention discloses a semiconductor structure and a manufacturing method thereof. The dielectric layer is located on the substrate. The conductive via penetrates from the lower surface of the substrate to the upper surface of the dielectric layer. The landing pads are embedded in the conductive vias. The semiconductor structure can provide sufficient contact area between the landing pad and the conductive via.)

1. A semiconductor structure, comprising:

a substrate;

a dielectric layer on the substrate;

a conductive via penetrating from a lower surface of the substrate to an upper surface of the dielectric layer; and

a landing pad embedded in the conductive via.

2. The semiconductor structure of claim 1, wherein the landing pad has a first top surface that is substantially coplanar with a second top surface of the conductive via.

3. The semiconductor structure of claim 1, wherein the landing pad has a top surface that is substantially coplanar with the upper surface of the dielectric layer.

4. The semiconductor structure of claim 1, wherein the conductive via has a top surface that is substantially coplanar with the upper surface of the dielectric layer.

5. The semiconductor structure of claim 1, wherein the landing pad has a first top width that is less than a second top width of the conductive via.

6. The semiconductor structure of claim 1, wherein the conductive via and the landing pad have a trapezoidal cross-section.

7. The semiconductor structure of claim 1, in which a material of the conductive via is different from a material of the landing pad.

8. A method of fabricating a semiconductor structure, the method comprising:

receiving a dielectric layer and a substrate, wherein the dielectric layer is disposed on the substrate;

forming an etch stop structure on the dielectric layer, wherein the etch stop structure has an etch stop layer and a protrusion extending out from the etch stop layer and into the dielectric layer;

forming a first hole from the substrate to expose a sidewall of the protrusion;

forming a conductive via in the first hole;

removing the etch stop structure to form a second hole in the conductive via; and

forming a landing pad in the second hole.

9. The method of claim 8, further comprising forming the first hole to expose the etch stop layer.

10. The method of claim 8, wherein forming the landing pad in the second hole comprises:

forming a conductive layer to cover the dielectric layer and the conductive via; and

removing a portion of the conductive layer to expose the dielectric layer.

Technical Field

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly, to a semiconductor structure including a landing pad embedded in a conductive via and a method of fabricating the same.

Background

Generally, through-silicon vias (TSVs) have been used to form electrical connections within a System-in-Package (System-in-Package) architecture, connecting a plurality of semiconductor wafers through a semiconductor wafer substrate. One method of fabricating these TSVs is known as the via-first (via-first) method, in which the TSVs are formed through a substrate prior to forming a metal layer of a semiconductor wafer. Another method of fabricating these TSVs is known as the via-last (via-last) method, in which a metal layer is first formed on a substrate, and the TSVs are formed so as to extend through the substrate and the metal layer. The landing pads (bonding pads) in the metal layer must be large enough to connect with the TSVs, and therefore occupy a large space. Furthermore, when TSVs are formed to connect with landing pads, the TSVs sometimes cannot be precisely aligned with the landing pads.

In view of the foregoing, there is a need to develop a new method of fabricating TSVs.

Disclosure of Invention

It is an object of the present invention to provide a semiconductor structure that can provide a sufficient contact area between a landing pad and a conductive via.

The invention provides a semiconductor structure, which comprises a substrate, a dielectric layer, a conductive through hole and a landing pad. The dielectric layer is located on the substrate. The conductive via penetrates from the lower surface of the substrate to the upper surface of the dielectric layer. The landing pads are embedded in the conductive vias.

In some embodiments, the landing pad has a first top surface that is substantially coplanar with a second top surface of the conductive via.

In some embodiments, the landing pad has a top surface that is substantially coplanar with an upper surface of the dielectric layer.

In some embodiments, the conductive via has a top surface that is substantially coplanar with an upper surface of the dielectric layer.

In some embodiments, the landing pad has a first top width that is less than a second top width of the conductive via.

In some embodiments, the conductive vias and landing pads have a trapezoidal cross-section.

In some embodiments, the material of the conductive via is different from the material of the landing pad.

The present invention provides a method of fabricating a semiconductor structure, the method comprising the following steps. The dielectric layer is disposed on the substrate. An etch stop structure is formed on the dielectric layer, wherein the etch stop structure has an etch stop layer and a protrusion extending from the etch stop layer and into the dielectric layer. A first hole is formed from the substrate to expose a sidewall of the protrusion. A conductive via is formed in the first hole. The etch stop structure is removed to form a second hole in the conductive via. A landing pad is formed in the second hole.

In some embodiments, the method further comprises forming a first hole to expose the etch stop layer

In some embodiments, forming the landing pad in the second hole comprises: forming a conductive layer to cover the dielectric layer and the conductive via; and removing a portion of the conductive layer to expose the dielectric layer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed.

Drawings

The above and other embodiments, features and other advantages of the present invention will be more clearly understood by reference to the following description taken in conjunction with the accompanying drawings, in which:

fig. 1-6 are cross-sectional views that schematically illustrate intermediate stages in the fabrication of a semiconductor structure, in accordance with some embodiments of the present invention.

7A-7C are top views that schematically illustrate landing pads and conductive vias, in accordance with some embodiments of the present invention.

Description of the main reference numerals:

100-substrate, 110-dielectric layer, 120-etch stop structure, 122-etch stop layer, 124-protrusion, 300-conductive via, 510-conductive layer, 512-first part, 514-second part, 600-semiconductor structure, 610-landing pad, H1-first hole, H2-second hole, S1-lower surface, S2-upper surface, S3-lower surface, S4-lower surface, SW-sidewall, TS1, TS 2-top surface, W1, W2-top width.

Detailed Description

In order to make the description of the present invention more complete and complete, reference is made to the accompanying drawings, in which like numerals designate the same or similar elements, and the various embodiments described below.

In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.

The invention provides a method of fabricating a semiconductor structure. Fig. 1-6 are cross-sectional views that schematically illustrate intermediate stages in the fabrication of a semiconductor structure. Although the methods disclosed herein are illustrated below as a series of acts or steps, the order in which the acts or steps are presented should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Moreover, not all illustrated operations, steps and/or features may be required to implement an embodiment of the present invention. Further, each operation or step described herein may comprise multiple sub-steps or actions.

Please refer to fig. 1. A substrate 100 and a dielectric layer 110 are received, wherein the dielectric layer 110 is disposed on the substrate 100. And, forming an etch stop structure 120 on the dielectric layer 110, wherein the etch stop structure 120 has an etch stop layer 122 and a protrusion 124, the protrusion 124 extending from the etch stop layer 122 into the dielectric layer 110. In some embodiments, the material of the etch stop structure 120 comprises a nitride, an oxide, or a combination thereof. For example, the nitride is silicon nitride (SiN). In some embodiments, dielectric layer 110 comprises silicon dioxide (SiO)₂)。

As shown in fig. 2, a first hole H1 is formed from the substrate 100 to expose the sidewall SW of the protrusion 124 and the lower surface S1 of the etch stop layer 122. In some embodiments, only the sidewalls SW of the protrusion 124 are exposed from the first hole H1, and the lower surface S1 of the etch stop layer 122 is not exposed. In some embodiments, the first hole H1 is formed by etching.

As shown in fig. 3, a conductive via 300 is formed in the first hole H1. Thus, the protrusion 124 of the etch stop structure 120 is embedded in the conductive via 300. In some embodiments, the conductive vias 300 comprise copper, gold, tungsten, or alloys thereof.

As shown in fig. 4, the etch stop structure 120 is removed to form a second hole H2 in the conductive via 300. More specifically, since the protrusion 124 of the etch stop structure 120 has been previously embedded in the conductive via 300, the second hole H2 is formed in the conductive via 300 after the etch stop structure 120 is removed.

As shown in fig. 5, a conductive layer 510 is formed to cover the dielectric layer 110 and the conductive via 300. Conductive layer 510 includes a first portion 512 and a second portion 514. The second portion 514 extends from the first portion 512 and fills the second hole H2 of the conductive via 300. The upper surface S2 of dielectric layer 110 is covered by first portion 512 of conductive layer 510. In some embodiments, conductive layer 510 comprises copper, gold, tungsten, or alloys thereof. In some embodiments, the material of conductive via 300 is different from the material of conductive layer 510.

As shown in fig. 6, a portion of the conductive layer 510 is removed to expose the dielectric layer 110, and thus, a landing pad 610 is formed in the second hole H2. In some embodiments, a portion of conductive layer 510 is removed by chemical-mechanical polishing (CMP).

Please still refer to fig. 6. Semiconductor structure 600 includes substrate 100, dielectric layer 110, conductive via 300, and landing pad 610. The dielectric layer 110 is located on the substrate 100. The conductive via 300 penetrates from the lower surface S3 of the substrate 100 to the upper surface S2 of the dielectric layer 110. The landing pad 610 is embedded in the conductive via 300. Notably, the contact area between the landing pad 610 and the conductive via 300 includes the lower surface S4 of the landing pad 610 and the surface of the sidewall SW. In contrast to conventional structures in which the landing pad contacts the conductive via only through its lower surface, the semiconductor structure 600 of the present invention can provide a sufficient contact area between the landing pad 610 and the conductive via 300.

In some embodiments, the landing pad 610 has a top surface TS1, the top surface TS1 being substantially coplanar with the top surface TS2 of the conductive via 300, as shown in fig. 6. In some embodiments, the landing pad 610 has a top surface TS1, the top surface TS1 being substantially coplanar with the upper surface S2 of the dielectric layer 110, as shown in fig. 6. In some embodiments, the conductive via 300 has a top surface TS2, the top surface TS2 being substantially coplanar with the top surface S2 of the dielectric layer 110, as shown in fig. 6.

In some embodiments, the top width W1 of the landing pad 610 is less than the top width W2 of the conductive via 300, as shown in fig. 6. Unlike conventional structures having a lower surface of the landing pad that is larger than an upper surface of the conductive via, the landing pad 610 of the present invention is smaller than that of conventional structures. Thus, the semiconductor structure 600 of the present invention is advantageously scaled down.

In some embodiments, conductive via 300 and landing pad 610 have a trapezoidal cross-section as shown in fig. 6. In some embodiments, conductive vias 300 include a dielectric layer and a conductive pillar. The conductive posts are surrounded by a dielectric layer. The conductive posts are separated from the substrate 100 and the dielectric layer 110 by the dielectric layer. In some embodiments, the material of conductive via 300 is different from the material of landing pad 610.

7A-7C are top views that schematically illustrate landing pads and conductive vias, in accordance with some embodiments of the present invention. As shown in fig. 7A, the landing pad 720a is accurately aligned with the conductive via 710. The contact surface between the landing pad 720a and the conductive via 710 includes the lower surface and sidewall surface of the landing pad 720a in contact with the conductive via 710. As shown in fig. 7B, the landing pad 720B is not accurately aligned with the conductive via 710, and the contact surface between the landing pad 720B and the conductive via 710 includes the lower surface and the sidewall surface of the landing pad 720B that is in contact with the conductive via 710, and thus, the contact surface is large enough to complete the electrical connection between the landing pad 720B and the conductive via 710. The contact surface between the landing pad 720c and the conductive via 710 includes the lower surface and sidewall surface of the landing pad 720c that contacts the conductive via 710, and therefore, this contact surface is large enough to complete the electrical connection between the landing pad 720c and the conductive via 710.

Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims.