阅读说明：本技术 包括堆叠的半导体芯片的半导体封装 (Semiconductor package including stacked semiconductor chips ) 是由 金载敏 于 2020-06-04 设计创作，主要内容包括：包括堆叠的半导体芯片的半导体封装。半导体封装可以包括：芯片堆叠,其包括第一至第N半导体芯片,该第一至第N半导体芯片以向一侧偏移的方式堆叠以使得该第一至第N半导体芯片的在另一侧的边缘被暴露,并且具有分别设置在另一侧边缘的第一至第N芯片焊盘；桥接单元,其相邻于芯片堆叠的另一侧并与芯片堆叠间隔开；第k至第N导线,该第k至第N导线在其一端与第一至第N芯片焊盘中的第k至第N芯片焊盘连接的状态下在垂直方向上延伸；第一至第k-1导线,该第一至第k-1导线的一端连接至第一至第N芯片焊盘中的第一至第k-1芯片焊盘；以及附加导线,其电连接到第一至第k-1导线并在其一端连接至桥接单元的状态下在垂直方向上延伸。(A semiconductor package includes stacked semiconductor chips. The semiconductor package may include: a chip stack including first to N-th semiconductor chips stacked in an offset manner to one side such that edges of the first to N-th semiconductor chips at the other side are exposed, and having first to N-th chip pads respectively disposed at the other side edges; a bridge unit adjacent to the other side of the chip stack and spaced apart from the chip stack; k to N-th conductive lines extending in a vertical direction in a state where one ends thereof are connected to k to N-th chip pads among the first to N-th chip pads; first to k-1-th conductive lines having one ends connected to first to k-1-th chip pads among the first to N-th chip pads; and additional conductive lines electrically connected to the first to k-1 th conductive lines and extending in a vertical direction in a state where one ends thereof are connected to the bridge unit.)

1. A semiconductor package, comprising:

a chip stack including first to N-th semiconductor chips stacked in order in a manner offset to one side such that edges of the first to N-th semiconductor chips at the other side are exposed, and having first to N-th chip pads disposed at the edges of the other side, respectively, wherein N is a natural number equal to or greater than 2;

a bridge unit disposed adjacent to the other side of the chip stack and spaced apart from the chip stack;

a k wire to an N wire extending in a vertical direction with one ends thereof connected to k chip pads to N chip pads of the first to N chip pads, wherein k is a natural number equal to or greater than 2 and equal to or less than N;

first to k-1-th wires having one ends connected to the first to k-1-th chip pads among the first to N-th chip pads, wherein the other ends of the first wires are connected to the bridge unit, and the other ends of the second to k-1-th wires are connected to the bridge unit or the first to k-2-th chip pads, respectively; and

an additional conductive line electrically coupled to the first to k-1 th conductive lines and extending in the vertical direction with one end thereof connected to the bridging unit.

2. The semiconductor package according to claim 1, wherein a thickness of the bridging unit is greater than a total thickness of the first to k-1 th semiconductor chips among the first to N-th semiconductor chips, and equal to or less than a thickness of the chip stack.

3. The semiconductor package of claim 1, wherein the bridging unit comprises:

a body portion; and

a redistribution layer on the body portion and connected to the additional conductive line and a conductive line of which the other end is connected to the bridge unit among the first to k-1 th conductive lines.

4. The semiconductor package of claim 3, wherein the body portion is electrically insulated from the redistribution layer and the chip stack.

5. The semiconductor package of claim 3, wherein the redistribution layer comprises:

a first redistribution dielectric layer covering the body portion;

a redistribution conductive layer on the first redistribution dielectric layer; and

a second redistribution dielectric layer covering the first redistribution dielectric layer and the redistribution conductive layer and having an opening to expose a portion of the redistribution conductive layer.

6. The semiconductor package according to claim 5, wherein the first to k-1 chip pads are signal pads to which signals are applied,

the redistribution conductive layer includes first to k-1 th conductive layers separated from each other,

the first to k-1 th conductive lines are connected to the first to k-1 th conductive layers, respectively, and

the additional conductive lines include first to k-1 th additional conductive lines connected with the first to k-1 th conductive layers, respectively, with being spaced apart from the first to k-1 th conductive lines.

7. The semiconductor package according to claim 6, wherein a tth conductive layer among the first to k-1 conductive layers includes a tth connection part having a relatively small width and two tth end parts having a relatively large width and located at both sides of the tth connection part, wherein t is a natural number equal to or greater than 1 and equal to or less than k-1,

the t +1 th conductive layer includes a t +1 th connection part having a relatively small width and two t +1 th end parts having a relatively large width and located at both sides of the t +1 th connection part, and

the t-th conductive layer and the t + 1-th conductive layer are disposed such that the two t-th end portions and the two t + 1-th end portions are alternately arranged.

8. The semiconductor package according to claim 7, wherein a tth wire of the first to k-1 st wires and a tth additional wire of the first to k-1 st additional wires are connected to the two tth ends, respectively, and

the t +1 th wire and the t +1 th additional wire are connected to the two t +1 th ends, respectively.

9. The semiconductor package of claim 8, wherein the tth wire is connected to a closer one of the two tth ends, and

the t +1 th wire is connected to a closer one of the two t +1 th end portions.

10. The semiconductor package of claim 7, wherein the opening of the second redistribution dielectric layer overlaps the two t-th end portions and the two t + 1-th end portions, respectively.

11. The semiconductor package according to claim 5, wherein the first to k-1 chip pads are power supply pads to which a ground voltage or a power supply voltage is applied,

the second to k-1 th wires are connected to the first to k-2 nd chip pads, and

the first wire and the additional wire are commonly connected to the redistribution conductive layer.

12. The semiconductor package of claim 11, wherein the redistribution conductive layer extends in one direction such that the other end of the first wire and the one end of the additional wire are arranged spaced apart from each other in the one direction.

13. The semiconductor package of claim 12, wherein the openings of the second redistribution dielectric layer overlap the other end of the first conductive line and one end of the additional conductive line, respectively.

14. The semiconductor package of claim 1, wherein the first through nth semiconductor chips comprise the same memory chip.

15. The semiconductor package according to claim 1, further comprising a molding layer covering the chip stack, the bridge unit, the first to nth wires, and the additional wire, and having one surface exposing the other ends of the k to nth wires and the additional wire.

16. The semiconductor package of claim 15, further comprising a package redistribution layer formed on the one surface of the molding layer and electrically coupled to the other end of the k-th wire to the N-th wire and the other end of the additional wire.

17. The semiconductor package of claim 16, wherein the package redistribution layer comprises:

a first package redistribution dielectric layer covering the one surface of the molding layer and having an opening to expose the k-th wire to the other end of the N-th wire and the other end of the additional wire;

a package redistribution conductive layer formed on the first package redistribution dielectric layer and connected to the k-th wire to the other end of the N-th wire and the other end of the additional wire through the opening; and

a second package redistribution dielectric layer covering the first package redistribution dielectric layer and the package redistribution conductive layer and having an opening to expose a portion of the package redistribution conductive layer.

18. The semiconductor package of claim 16, further comprising external connection terminals electrically coupled to the package redistribution layer.

19. The semiconductor package of claim 1, further comprising an additional chip stack sharing the bridging unit with the chip stack.

20. The semiconductor package of claim 19, wherein the additional chip stack is disposed opposite a side of the bridge unit adjacent to another side of the chip stack such that the bridge unit is interposed between the chip stack and the additional chip stack.

21. The semiconductor package according to claim 19, wherein the wires connected to the additional chip stack have a symmetrical structure with the first to nth wires and the additional wire connected to the chip stack.

Technical Field

Various embodiments relate generally to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips stacked over a substrate.

Background

Electronic products need to process larger amounts of data while having a smaller volume. Therefore, it is necessary to increase the integration degree of the semiconductor device used in such electronic products.

However, due to the limitation of semiconductor integration technology, only a single semiconductor chip cannot satisfy the required functions. Thus, a semiconductor package having a plurality of semiconductor chips embedded therein is manufactured.

Although a semiconductor package includes a plurality of semiconductor chips, the semiconductor package is required to have a specified size or a size smaller than the specified size according to the requirements of an application in which the semiconductor package is to be mounted.

Disclosure of Invention

In one embodiment, a semiconductor package may include: a chip stack including first to N-th semiconductor chips stacked in a manner offset to one side such that edges of the first to N-th semiconductor chips at the other side are exposed, and having first to N-th chip pads respectively disposed at the other side edges, wherein N is a natural number equal to or greater than 2; a bridge unit adjacent to the other side of the chip stack and spaced apart from the chip stack; k to N-th conductive lines extending in a vertical direction in a state where one ends thereof are connected to k to N-th chip pads among the first to N-th chip pads, wherein k is a natural number equal to or greater than 2 and equal to or less than N; first to k-1-th wires having one ends connected to first to k-1-th chip pads among the first to N-th chip pads, wherein the other ends of the first wires are connected to a bridge unit, and the other ends of the second to k-1-th wires are connected to the bridge unit or the first to k-2-th chip pads, respectively; and additional conductive lines electrically connected to the first to k-1 th conductive lines and extending in a vertical direction in a state where one ends thereof are connected to the bridge unit.

Drawings

Fig. 1A, 1B, 1C, 1D, 1E, 1F, 2A, 2B, 2C, 2D, 2E, 2F, 2G, 3, 4, and 5 are diagrams for describing a semiconductor package and a method of manufacturing the same according to an embodiment.

Fig. 6 is a diagram showing sweeping (sweeping) of vertical wires.

Fig. 7A and 7B are a sectional view and a plan view illustrating a semiconductor package according to an embodiment.

FIG. 8 shows a block diagram of an electronic system employing a memory card including a semiconductor package according to one embodiment.

Fig. 9 shows a block diagram of another electronic system including a semiconductor package according to an embodiment.

Detailed Description

Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings.

Various embodiments may be directed to a semiconductor package and a method of manufacturing the same capable of avoiding defects and facilitating a manufacturing process.

The drawings may not necessarily be to scale and in some instances, the proportions of at least some of the structures in the drawings may be exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example having two or more layers is presented in a multilayer structure in the drawings or the specification, the relative positional relationship of the layers or the order in which the layers are arranged as shown reflects the specific embodiment of the example described or illustrated, and different relative positional relationship or order in which the layers are arranged is also possible. Additionally, the examples of multilayer structures described or illustrated may not reflect all of the layers present in that particular multilayer structure (e.g., there may be one or more additional layers between the two illustrated layers). As a specific example, when a first layer in a multilayer structure described or illustrated is referred to as being "on" or "over" a second layer or as being "on" or "over" a substrate, the first layer may be formed directly on the second layer or the substrate, but may also represent a structure in which one or more other intermediate layers may be present between the first layer and the second layer or the substrate.

Fig. 1A to 1F, fig. 2A to 2G, and fig. 3 to 5 are diagrams for describing a semiconductor package and a method of manufacturing the same according to an embodiment. Fig. 1A, fig. 2B, fig. 3, fig. 4, and fig. 5 are sectional views, and fig. 1B and fig. 2C are plan views corresponding to fig. 1A and fig. 2A/fig. 2B, respectively. Fig. 1C to 1F are diagrams illustrating a redistribution layer (redistribution layer) of fig. 1A and 1B, and fig. 2D to 2G are diagrams illustrating the redistribution layer of fig. 1C to 1F and a wire (wire) connected thereto.

First, the manufacturing method will be described.

Referring to fig. 1A and 1B, a carrier substrate 100 may be provided. The carrier substrate 100 may be a glass carrier substrate or a ceramic carrier substrate, etc. Alternatively, the carrier substrate 100 may be a wafer (wafer), and a plurality of packages may be simultaneously formed on the carrier substrate 100.

Then, the chip stack 200 and the bridge unit 300 may be formed on the first surface 101 of the carrier substrate 100.

The chip stack 200 may include a plurality of semiconductor chips 210, 220, 230, and 240 stacked in a direction perpendicular to the first surface 101 of the carrier substrate 100. Fig. 1A and 1B show that one chip stack 200 includes four semiconductor chips 210, 220, 230, and 240. However, the present embodiment is not limited thereto, but the number of semiconductor chips included in one chip stack 200 may be set to various values. Hereinafter, for convenience of description, the four semiconductor chips 210, 220, 230, and 240 are referred to as a first semiconductor chip 210, a second semiconductor chip 220, a third semiconductor chip 230, and a fourth semiconductor chip 240, respectively, according to distances from the carrier substrate 100. Further, for convenience of description, a position relatively close to the carrier substrate 100 in the vertical direction will be referred to as a bottom/lower position, and a position relatively far from the carrier substrate 100 will be referred to as a top/upper position. For example, the first semiconductor chip 210 may be referred to as being located at the lowermost portion of the chip stack 200, and the fourth semiconductor chip 240 may be referred to as being located at the uppermost portion of the chip stack 200.

The first to fourth semiconductor chips 210, 220, 230 and 240 may include first to fourth active (active) surfaces 216, 226, 236 and 246 and first to fourth inactive surfaces 217, 227, 237 and 247, respectively. The first to fourth active surfaces 216, 226, 236 and 246 do not face the first surface 101 of the carrier substrate 100, and the first to fourth inactive surfaces 217, 227, 237 and 247 are located at opposite sides of the first to fourth active surfaces 216, 226, 236 and 246 to face the first surface 101 of the carrier substrate 100. The first to fourth semiconductor chips 210, 220, 230 and 240 may include first to fourth chip pads 212, 222, 232 and 242 disposed at the first to fourth active surfaces 216, 226, 236 and 246, respectively. The first to fourth chip pads 212, 222, 232, and 232 may be bonding pads for wire bonding.

The first to fourth semiconductor chips 210, 220, 230 and 240 may be sequentially stacked in a state of being shifted to one side (e.g., the right side) in the first direction by a predetermined offset. When the first to fourth semiconductor chips 210, 220, 230 and 240 are sequentially stacked in such a manner as to be offset to the one side, the other side edges of the first to third active surfaces 216, 226 and 236 of the first to third semiconductor chips 210, 220 and 230 may be exposed. The other side edges of the first to third active surfaces 216, 226 and 236 may be edges (e.g., left edges) located on the opposite side of one side in the offset direction. Hereinafter, the exposed edges of the first to third active surfaces 216, 226 and 236 will be referred to as exposed portions of the first to third active surfaces 216, 226 and 236 and will be denoted by reference numerals 216A, 226A and 236A, respectively. The first to third chip pads 212, 222 and 232 may be disposed in the exposed portions 216A, 226A and 236A of the first to third active surfaces 216, 226 and 236, respectively. That is, the first to third semiconductor chips 210, 220 and 230 may be edge pad-type (edge pad-type) semiconductor chips. Since the fourth semiconductor chip 240 is located at the uppermost portion of the chip stack 200, the entire fourth active surface 246 may be exposed. Therefore, the fourth chip pad 242 may be located at any position of the fourth active surface 246. In an embodiment, the fourth chip pad 242 may be located at substantially the same position as the first to third chip pads 212, 222 and 232, that is, a left edge of the fourth active surface 246 of the fourth semiconductor chip 240. That is, the fourth semiconductor chip 240 may be an edge pad type semiconductor chip.

The cross-sectional view of fig. 1A shows that each of the first to fourth chip pads 212, 222, 232, and 242 appears to be formed as one pad in a corresponding one of the first to fourth semiconductor chips 210, 220, 230, and 240. However, referring to the plan view of fig. 1B, a plurality of first chip pads 212 may be disposed in the exposed portion 216A of the first active surface 216 of the first semiconductor chip 210. The first chip pads may be spaced apart from each other in a second direction substantially perpendicular to the first direction while being parallel to the first surface 101 of the carrier substrate 100. Fig. 1B shows that 12 first chip pads 212 are formed on one line, but the number and arrangement of the first chip pads 212 may be modified in various ways. Similarly, the plurality of second chip pads 222 may be disposed in the exposed portion 226A of the second active surface 226 while being spaced apart from each other in the second direction, and the plurality of third chip pads 232 may be disposed in the exposed portion 236A of the third active surface 236 while being spaced apart from each other in the second direction. A plurality of fourth chip pads 242 may be arranged at a left edge of the fourth active surface 246 while being spaced apart from each other in the second direction.

Among a plurality of chip pads included in each of the first to fourth semiconductor chips 210, 220, 230, and 240, a certain chip pad may be a signal pad to which an input/output signal is applied, and another chip pad may be a power supply pad to which a power supply voltage or a ground voltage is applied. In one embodiment, fig. 1B illustrates a case where, with respect to the second direction, the lowermost first chip pad 212 among the plurality of first chip pads 212 is a signal pad, and the first chip pad 212 above the signal pad is a power supply pad. For convenience of description, among the first chip pads 212, the signal pad will be referred to as a first signal pad 212A, and the power supply pad will be referred to as a first power supply pad 212B. In one embodiment, fig. 1B illustrates a case where, from the perspective of the second direction, the lowermost second chip pad 222 among the plurality of second chip pads 222 is a signal pad, and the second chip pad 222 above the signal pad is a power supply pad. For convenience of description, among the second chip pads 222, the signal pad will be referred to as a second signal pad 222A, and the power supply pad will be referred to as a second power supply pad 222B. In one embodiment, the first signal pad 212A of the first semiconductor chip 210 and the second signal pad 222A of the second semiconductor chip 220 may be formed at positions corresponding to each other, and the first power supply pad 212B of the first semiconductor chip 210 and the second power supply pad 222B of the second semiconductor chip 220 may be formed at positions corresponding to each other. However, the present embodiment is not limited thereto, and the number and position of the signal pads and the number and position of the power supply pads in each semiconductor chip may be modified in various ways.

The first to fourth semiconductor chips 210, 220, 230 and 240 may be the same chip. The first to fourth semiconductor chips 210, 220, 230 and 240 may be memory chips (memory chips). For example, the first to fourth semiconductor chips 210, 220, 230 and 240 may be NAND flash memory chips. However, the present embodiment is not limited thereto, and each of the first to fourth semiconductor chips 210, 220, 230 and 240 may include a non-volatile memory chip such as a phase change random access memory (PRAM) and a magnetoresistive RAM or a volatile memory chip such as a Dynamic RAM (DRAM), a mobile DRAM and a static RAM (sram).

On each of the first to fourth inactive surfaces 217, 227, 237 and 247 of the first to fourth semiconductor chips 210, 220, 230 and 240, an adhesive layer 205 may be formed. The first to fourth semiconductor chips 210, 220, 230 and 240 may be attached to the first surface 101 of the carrier substrate 100 and the first to third active surfaces 216, 226 and 236 of the first to third semiconductor chips 210, 220 and 230, respectively, by the adhesive layer 205. The adhesive layer 205 may include a dielectric adhesive material such as Die Attach Film (DAF).

The bridge unit 300 may be formed on the first surface 101 of the carrier substrate 100 to be spaced apart from the chip stack 200. Specifically, the bridge unit 300 may be disposed at a side close to the first to fourth chip pads 212, 222, 232, and 242 among both sides of the chip stack 200 in the first direction. This is to electrically couple some of the wires connected to the first to fourth chip pads 212, 222, 232, and 242 to the bridge unit 300. In one embodiment, the first to fourth semiconductor chips 210, 220, 230 and 240 of the chip stack 200 may be stacked in a right-offset manner such that the first to fourth chip pads 212, 222, 232 and 242 are disposed at left edges of the first to fourth semiconductor chips 210, 220, 230 and 240. Accordingly, the bridge unit 300 may be disposed at the left side of the chip stack 200. However, in one embodiment, the first to fourth semiconductor chips 210, 220, 230 and 240 of the chip stack 200 may be stacked in a leftward offset manner such that the first to fourth chip pads 212, 222, 232 and 242 are disposed at right edges of the first to fourth semiconductor chips 210, 220, 230 and 240. In this case, the bridge unit 300 may be disposed at the right side of the chip stack 200.

The bridge unit 300 may include a body portion 310 and a redistribution layer 320 on the body portion 310.

The body portion 310 may include a second surface 313 facing the first surface 101 of the carrier substrate 100 and a first surface 311 on an opposite side of the second surface 313. The redistribution layer 320 may be formed on the first surface 311 of the body portion 310 and the adhesive layer 305 may be formed on the second surface 313 of the body portion 310 to attach the body portion 310 to the carrier substrate 100.

The body portion 310 may be a dummy body (dummy) that does not perform an electrical function and is electrically insulated from components within the package (e.g., the redistribution layer 320 and the chip stack 200, etc.). However, the body portion 310 may be used to provide a predetermined thickness to meet the thickness T2 required by the bridge unit 300 and may provide a predetermined area to provide an area where the redistribution layer 320 is to be formed. The body portion 310 may be a block formed of a material including, for example, but not limited to, silicon, glass, ceramic, or some combination thereof.

The redistribution layer 320 may include a plurality of redistribution pads 327 arranged in a matrix shape in a first direction and a second direction. When the redistribution pads 327 arranged in the first direction are referred to as a row of redistribution pads 327, a particular row of redistribution pads 327 may include a first redistribution pad 327A (see P1), while another row of redistribution pads 327 may include a second redistribution pad 327B (see P2). The first redistribution pad 327A may be connected to signal pads (e.g., the first signal pad 212A and the second signal pad 222A). The row of the first redistribution pad 327A may be formed at positions corresponding to the first and second signal pads 212A and 222A. Second redistribution pad 327B may be connected to power supply pads (e.g., first power supply pad 212B and second power supply pad 222B). The row of second redistribution pads 327B may be formed at positions corresponding to the first power supply pad 212B and the second power supply pad 222B. Such a redistribution layer 320 will be described with reference to fig. 1C through 1F.

Fig. 1C is a plan view of the redistribution layer 320 shown based on the row of the first redistribution pads 327A in fig. 1B, fig. 1D is a cross-sectional view taken along line X1-X1 'of fig. 1C, fig. 1E is a plan view of the redistribution layer 320 shown based on the row of the second redistribution pads 327B in fig. 1B, and fig. 1F is a cross-sectional view taken along line X2-X2' of fig. 1E.

First, referring to fig. 1C and 1D and fig. 1A and 1B, the redistribution layer 320 may include a first redistribution dielectric layer 321 formed on the first surface 311 of the body portion 310, a first redistribution conductive layer 326A formed on the first redistribution dielectric layer 321, and a second redistribution dielectric layer 323 formed on the first redistribution dielectric layer 321 and the first redistribution conductive layer 326A and having an opening to expose a portion of the first redistribution conductive layer 326A.

The first redistribution dielectric layer 321 may cover the entire first surface 311 of the body portion 310 to insulate the first redistribution conductive layer 326A and the body portion 310 from each other.

The first redistribution conductive layer 326A may include a first conductive layer 326A-1 and a second conductive layer 326A-2 spaced apart from each other in the second direction. The first conductive layer 326A-1 may be a portion to be connected to the first signal pad 212A, and the second conductive layer 326A-2 may be a portion to be connected to the second signal pad 222A. Since the different signal pads need to be electrically isolated from each other, first conductive layer 326A-1 and second conductive layer 326A-2 can be spaced apart from each other and electrically isolated from each other.

The first conductive layer 326A-1 may include a line-shaped connection portion L1 and plate-shaped first and second end portions E1 and E1'. The connection part L1 may have a relatively small width in a state of extending in the first direction, and the first and second end parts E1 and E1' may have a relatively large width in a state of being located at both ends of the connection part L1. The second conductive layer 326A-2 may include a line-shaped connection portion L2 and plate-shaped first and second end portions E2 and E2'. The line-shaped connection part L2 may have a relatively small width in a state of extending in the first direction, and the first and second end parts E2 and E2' may have a relatively large width in a state of being located at both ends of the connection part L2.

The first and second end portions E1 and E1 'of the first conductive layer 326A-1 and the first and second end portions E2 and E2' of the second conductive layer 326A-2 may have surfaces overlapping the opening of the second redistribution dielectric layer 323, respectively, to be exposed therethrough. The first and second ends E1 and E1 'of the first conductive layer 326A-1 and the exposed portions of the first and second ends E2 and E2' of the second conductive layer 326A-2 exposed through the openings of the second redistribution dielectric layer 323 may constitute the first redistribution pads 327A. For example, the exposed portion of the first end E1 of the first conductive layer 326A-1 to be connected to the first signal pad 212A by a wire will be referred to hereinafter as a first signal redistribution pad 327A-1. The exposed portion of first end E2 of second conductive layer 326A-2 to be connected to second signal pad 222A by a wire will be referred to hereinafter as second signal redistribution pad 327A-2. The exposed portion of the second end E1' of the first conductive layer 326A-1 that may be electrically coupled to the first signal pad 212A by a connection L1 will be referred to hereinafter as a first another signal redistribution pad 327A-3. The exposed portion of the second end portion E2' of the second conductive layer 326A-2 that may be electrically coupled to the second signal pad 222A by a connection L2 will be referred to hereinafter as a second another signal redistribution pad 327A-4.

The first conductive layer 326A-1 may be disposed closer to one side (e.g., a top side) in the second direction than the second conductive layer 326A-2. The first end E1 and the second end E1' of the first conductive layer 326A-1 may protrude further to the other side (e.g., the bottom side) in the second direction than the connection portion L1. The first end E2 and the second end E2' of the second conductive layer 326A-2 may protrude further to one side (e.g., top side) in the second direction than the connection portion L2. In addition, the first and second ends E1 and E1 'of the first conductive layer 326A-1 and the first and second ends E2 and E2' of the second conductive layer 326A-2 may be alternately arranged from the right side toward the left side. In this case, the first end E2 of the second conductive layer 326A-2 may be disposed between the first end E1 and the second end E1 ' of the first conductive layer 326A-1, and the second end E1 ' of the first conductive layer 326A-1 may be disposed between the first end E2 and the second end E2 ' of the second conductive layer 326A-2. Thus, the first signal redistribution pad 327A-1, the second signal redistribution pad 327A-2, the first further signal redistribution pad 327A-3, and the second further signal redistribution pad 327A-4 may be located on a straight line (e.g., line X1-X1') in a state of being arranged in order in a right-to-left direction.

The second redistribution dielectric layer 323 may be formed to cover the first redistribution conductive layer 326A and the first redistribution dielectric layer 321, except for four openings exposing the first end E1 and the second end E1 'of the first conductive layer 326A-1 and the first end E2 and the second end E2' of the second conductive layer 326A-2, respectively.

Next, referring to fig. 1E and 1F and fig. 1A and 1B, the redistribution layer 320 may include a first redistribution dielectric layer 321, a second redistribution conductive layer 326B formed on the first redistribution dielectric layer 321, and a second redistribution dielectric layer 323 formed on the first redistribution dielectric layer 321 and the second redistribution conductive layer 326B and having an opening to expose a portion of the second redistribution conductive layer 326B.

Second redistribution conductive layer 326B may be a portion to be connected to first power supply pad 212B and second power supply pad 222B. The first and second power pads 212B and 222B may be ground pads. Alternatively, the first and second power supply pads 212B and 222B may be pads for supplying power. The ground pads may be electrically coupled to each other. Further, the power pads may be electrically coupled to each other. Accordingly, the second redistribution conductive layer 326B may be commonly connected to the first power supply pad 212B and the second power supply pad 222B through wires. For example, although described below, second redistribution conductive layer 326B may be directly connected to wires connected to first power supply pads 212B, and not directly connected to wires connected to second power supply pads 222B. Since the wire connected to the second power supply pad 222B is connected to the first power supply pad 212B, the second power supply pad 222B may be connected to the second redistribution conductive layer 326B via the first power supply pad 212B.

The second redistribution conductive layer 326B may have a stripe shape having a width in the first direction greater than a width in the second direction or a shape similar to the stripe shape. The second redistribution conductive layer 326B may have a surface that overlaps and is exposed through the opening of the second redistribution dielectric layer 323. The portion of the second redistribution conductive layer 326B exposed through the opening of the second redistribution dielectric layer 323 may constitute the second redistribution pad 327B described above. Second redistribution pad 327B may include a power redistribution pad 327B-1 and another power redistribution pad 327B-2, the power redistribution pad 327B-1 being to be connected by wire to first power supply pad 212B, and the another power redistribution pad 327B-2 being electrically coupled to first power supply pad 212B by second redistribution conductive layer 326B.

The power redistribution pad 327B-1 and another power redistribution pad 327B-2 may be arranged in sequence from the right side toward the left side and in a straight line (e.g., line X2-X2'). Power redistribution pad 327B-1 and another power redistribution pad 327B-2 may be disposed relatively close to chip stack 200 (i.e., to the right).

Referring back to fig. 1A and 1B, the sum of the number of rows of first redistribution pads 327A and the number of rows of second redistribution pads 327B may be substantially equal to the number of first chip pads 212 arranged in the second direction and/or the number of second chip pads 222 arranged in the second direction. In one embodiment, fig. 1B illustrates a case where the row of second redistribution pads 327B is set to one row at a second position from the bottom in the second direction, and the other row is the row of first redistribution pads 327A. However, the relative number and arrangement thereof may be modified in various ways.

The thickness of the chip stack 200, i.e., the distance from the first surface 101 of the carrier substrate 100 to the top surface of the fourth semiconductor chip 240, or the distance from the bottom surface of the lowermost adhesive layer 205 to the top surface of the fourth semiconductor chip 240, may be referred to as a first thickness T1. When the adhesive layer 205 is omitted, the thickness T1 of the chip stack 200 may correspond to a distance from the bottom surface of the first semiconductor chip 210 to the top surface of the fourth semiconductor chip 240. The thickness of the bridge unit 300, i.e., the distance from the first surface 101 of the carrier substrate 100 to the top surface of the redistribution layer 320, or the distance from the bottom surface of the adhesive layer 305 to the top surface of the redistribution layer 320, may be referred to as a second thickness T2. When the adhesive layer 305 is omitted, the thickness T2 of the bridging unit 300 may correspond to a distance from the bottom surface of the body portion 310 to the top surface of the redistribution layer 320. The second thickness T2 may be equal to or less than the first thickness T1. In addition, the second thickness T2 may be greater than the total thickness of the semiconductor chips (e.g., the first semiconductor chip 210 and the second semiconductor chip 220) to be connected to the bridge unit 300. In this case, the length of the vertical wires (see reference numerals 314 and 324 of fig. 2A) indirectly connected to the first and second semiconductor chips 210 and 220 through the bridging unit 300 may be shorter than the length of the vertical wires directly connected to the first and second semiconductor chips 210 and 220. Thus, sweeping (sweeping) of the vertical wires can be reduced.

Subsequently, referring to fig. 2A to 2C, first to fourth conductive lines 214, 224, 234 and 244 connected to the first to fourth chip pads 212, 222, 232 and 242, respectively, and first to third additional conductive lines 314, 324 and 334 connected to some of the redistribution pads 327 of the redistribution layer 320 may be formed.

Among the first to fourth conductive lines 214, 224, 234 and 244, the first conductive line 214 and the second conductive line 224 connected to the first chip pad 212 of the first semiconductor chip 210 and the second chip pad 222 of the second semiconductor chip 220 may be bent toward the redistribution layer 320 to be connected to the redistribution layer 320. On the other hand, the third and fourth wires 234 and 244 connected to the third and fourth chip pads 232 and 242 of the third and fourth semiconductor chips 230 and 240 may extend in the vertical direction. In addition, the first to third additional conductive lines 314, 324 and 334 may extend in a vertical direction.

First and second conductive lines 214 and 224 may be formed by a wire bonding process. The third and fourth conductive lines 234 and 244 and the first to third additional conductive lines 314, 324 and 334 may be formed through a vertical conductive line forming process. The vertical wire forming process will be described below. First, one end of the wire may be bonded to the chip pad by a wire bonding machine (not shown). The wires may include metals such as gold, silver, copper, and platinum or alloys thereof that can be soldered to the die pads by ultrasonic energy and/or heat. The other end of the wire may then be pulled in a vertical direction away from the chip pad (e.g., from bottom to top) by a wire bonding machine. When the other end of the wire is extended to a desired position, the other end of the wire may be cut.

One end of the third and fourth wires 234 and 244 may be connected to the third and fourth chip pads 232 and 242, respectively, and the other end is located at an opposite side of the one end and at a higher level than the top surface of the chip stack 200 (i.e., the fourth active surface 246 of the fourth semiconductor chip 240). In one embodiment, the other ends of the third and fourth conductive lines 234 and 244 may be located at the same distance (i.e., at the same height) from the first surface 101 of the carrier substrate 100. However, the present embodiment is not limited thereto, and the other ends of the third and fourth conductive lines 234 and 244 may be located at different heights on the premise that the other ends of the third and fourth conductive lines 234 and 244 are located at a higher level than the fourth active surface 246. Since the third and fourth conductive lines 234 and 244 are connected with the third and fourth semiconductor chips 230 and 240, respectively, which are formed at a relatively long distance from the carrier substrate 100, the third and fourth conductive lines 234 and 244 may have a relatively small length.

The first conductive lines 214 may have one end connected to the first chip pad 212 and the other end connected to the redistribution pad 327 of the redistribution layer 320. For example, the first conductive line 214 may include a first signal line 214A and a first power line 214B. The first signal line 214A may have one end connected to the first signal pad 212A of the first chip pad 212 and the other end connected to one of the first redistribution pads 327A. The first power line 214B may have one end connected to the first power supply pad 212B of the first chip pad 212 and the other end connected to one of the second redistribution pads 327B. The second conductive lines 224 may have one end connected to the second chip pad 222 and the other end connected to the redistribution pad 327 of the redistribution layer 320 or the first chip pad 212. For example, the second wire 224 may include a second signal line 224A and a second power line 224B. The second signal line 224A may have one end connected to the second signal pad 222A among the second chip pads 222 and the other end connected to one of the first redistribution pads 327A. The second power line 224B may have one end connected to the second power supply pad 222B among the second chip pads 222 and the other end connected to the first power supply pad 212B of the first chip pad 212.

The first through third additional wires 314, 324, and 334 may have one end connected to the redistribution pad 327 of the redistribution layer 320 and the other end located at an opposite side of the one end and at a higher level than the top surface of the chip stack 200. In one embodiment, the other ends of the first to third additional wires 314, 324 and 334 may be located at the same height as the other ends of the third wire 234 and the fourth wire 244 in a state of being located at the same height. However, the present embodiment is not limited thereto, but the other ends of the first to third additional wires 314, 324 and 334 may be located at different heights on the premise that the other ends of the first to third additional wires 314, 324 and 334 are located at a higher level than the fourth active surface 246. Since the first to third additional conductive lines 314, 324 and 334 are connected with the redistribution layer 320 formed at a relatively long distance from the carrier substrate 100, the first to third additional conductive lines 314, 324 and 334 may have a relatively small length.

The connection relationship between the first and second conductive lines 214 and 224 and the redistribution layer 320 and between the first to third additional conductive lines 314, 324 and 334 and the redistribution layer 320 will be described with reference to fig. 2D to 2G to be described later.

Fig. 2D is a plan view of the redistribution layer 320 and the wires connected to the redistribution layer 320 shown based on the row of the first redistribution pads 327A in fig. 2C, fig. 2E is a cross-sectional view taken along line X1-X1 'of fig. 2D, fig. 2F is a plan view of the redistribution layer 320 and the wires connected to the redistribution layer 320 shown based on the row of the second redistribution pads 327B in fig. 2C, and fig. 2G is a cross-sectional view taken along line X2-X2' of fig. 2F.

First, referring to fig. 2D and 2E and fig. 2A and 2C, as described above, the first redistribution pad 327A may include a first signal redistribution pad 327A-1, a second signal redistribution pad 327A-2, a first further signal redistribution pad 327A-3, and a second further signal redistribution pad 327A-4, which are sequentially arranged in a left-to-right direction.

The other end of the first signal line 214A connected to the first signal pad 212A may be connected to a first signal redistribution pad 327A-1. That is, first signal line 214A may connect first signal pad 212A and first signal redistribution pad 327A-1 that are closest to each other in the first direction.

The other end of second signal line 224A connected to second signal pad 222A may be connected to second signal redistribution pad 327A-2. That is, second signal line 224A may connect second signal pad 222A and second signal redistribution pad 327A-2 that are second proximate to each other in the first direction. To prevent a short circuit to the first signal line 214A, the second signal line 224A may be spaced apart from the first signal line 214A by a predetermined distance in the vertical direction and formed at a higher position than the first signal line 214A.

First additional conductor 314 may have one end connected to a first other signal redistribution pad 327A-3. First another signal redistribution pad 327A-3 may be connected to first signal redistribution pad 327A-1 by first conductive layer 326A-1. As a result, a signal path may be formed through the first signal pad 212A, the first signal line 214A, the first conductive layer 326A-1, and the first additional conductive line 314.

Second additional conductor 324 may have one end connected to a second other signal redistribution pad 327A-4. A second other signal redistribution pad 327A-4 may be connected to second signal redistribution pad 327A-2 by second conductive layer 326A-2. As a result, a signal path may be formed through the second signal pad 222A, the second signal line 224A, the second conductive layer 326A-2, and the second additional conductive line 324.

Next, referring to FIGS. 2F and 2G and FIGS. 2B and 2C, as described above, the second redistribution pad 327B may include a power redistribution pad 327B-1 and another power redistribution pad 327B-2 arranged in sequence in a direction from right to left.

The other end of first power line 214B connected to first power supply pad 212B may be connected to power redistribution pad 327B-1. That is, the first power line 214B may connect the first power supply pad 212B and the power redistribution pad 327B-1 closest to each other in the first direction.

On the other hand, the other end of the second power line 224B connected to the second power supply pad 222B may not be directly connected to the second redistribution conductive layer 326B, but may be connected to the first power supply pad 212B.

Third additional wire 334 may have one end connected to another power redistribution pad 327B-2. Another power redistribution pad 327B-2 may be connected to power redistribution pad 327B-1 by second redistribution conductive layer 326B. As a result, a power supply path passing through second power supply pad 222B, second power supply line 224B, first power supply pad 212B, first power supply line 214B, second redistribution conductive layer 326B, and third additional wire 334 may be formed.

Referring again to fig. 2A through 2C, the wires (e.g., the third and fourth wires 234 and 244) of the first through fourth wires 214, 224, 234, and 244 connected to the semiconductor chip located at a relatively high level may have a relatively small length even if extending in the vertical direction. Therefore, the occurrence of sweeping can be prevented, or the sweeping stroke can be small. However, wires (e.g., the first and second wires 214 and 224) connected to the semiconductor chip located at a relatively low level among the first to fourth wires 214, 224, 234, and 244 may have a relatively large length when extending in the vertical direction. The sweeping motion of the wire may be relatively large. Accordingly, in one embodiment, the first and second conductive lines 214 and 224 may be connected to the bridging unit 300 to prevent the sweeping of the first and second conductive lines 214 and 224. The sweeping will be described below with reference to fig. 6.

Fig. 6 is a diagram showing the sweeping of the vertical wire VW.

Referring to fig. 6, the vertical wire VW may have one end E1 attached to the chip pad and the other end E2 located at the opposite side of the one end E1.

The left side of the arrow shows a state immediately after the vertical wire VW is formed. Such a vertical wire VW can maintain the state in which the vertical wire VW is upright in the vertical direction as long as no external force is applied.

The right side of the arrow shows a state after an external force (e.g., pressure caused by the flow of the molding material) is applied to the vertical wires VW in the molding process. When such pressure is applied, since the end E1 of the vertical wire VW is attached and fixed to the chip pad, the end E1 does not move. However, since the other end E2 of the vertical wire VW is not fixed, the other end E2 thereof moves in the direction in which the pressure is applied. Therefore, a sweeping motion in which the vertical wires VW are bent may occur. Due to the sweeping, the other end E2 of the vertical wire VW may be displaced to a random position within the concentric circle shown in fig. 6. The displacement of the other end E2 of the vertical wire VW may be changed due to the vortex (vortex) of the molding material caused by the injection direction and pressure of the molding material and the surrounding structure. This sweeping may become severe as the length of the vertical wires VW increases. When the vertical wire VW is swept, the vertical wire VW may be shorted with an adjacent vertical wire, or the connection between the vertical wire VW and the chip pad may be removed. In addition, due to the change in the position of the other end E2 of the vertical wire VW, a component (for example, the redistribution layer 600 (see fig. 6)) to be connected to the other end E2 of the vertical wire VW may be misaligned with the other end E2 of the vertical wire VW. Therefore, a connection defect may occur between the vertical wires VW and the redistribution layer.

Referring again to fig. 2A through 2C, when the wires connected to the first and second chip pads 212 and 222 are implemented as vertical wires, the wires may be swept more than the wires connected to the third and fourth chip pads 232 and 242 because the lengths of the wires connected to the first and second chip pads 212 and 222 are greater than the lengths of the wires connected to the third and fourth chip pads 232 and 242. In one embodiment, the first and second conductive lines 214 and 224 may be connected to the bridge unit 300 on one side of the chip stack 200. Since one end and the other end of the first wire 214 and the second wire 224 are fixed, the sweeping may be prevented or reduced.

Since the first to third additional conductive lines 314, 324 and 334 extending in the vertical direction in a state of being connected to the first conductive line 214 and the second conductive line 224 are formed in the bridge unit 300, the first conductive line 214 and the second conductive line 224 may function as an interconnection for transmitting signals in the vertical direction, like the third conductive line 234 and the fourth conductive line 244.

Since the first to third additional conductive lines 314, 324 and 334 are formed on the bridge unit 300 and thus have a relatively small length like the third conductive line 234 and the fourth conductive line 244, the sweeping motion may be prevented or reduced.

Referring to fig. 3, a molding layer 500 may be formed on the carrier substrate 100 on which the chip stack 200, the bridge unit 300, the first to fourth wires 214, 224, 234 and 244, and the first to third additional wires 314, 324 and 334 are formed.

The molding layer 500 may be formed to have a thickness sufficient to cover the chip stack 200 and the bridge unit 300. In one embodiment, the molding layer 500 may be formed to have a thickness sufficient to cover the third and fourth wires 234 and 244 and the first to third additional wires 314, 324, and 334, which are vertical wires. However, in another embodiment, on the premise that the molding layer 500 covers the chip stack 200 and the bridge unit 300, the molding layer 500 may have a thickness exposing the other ends of the third and fourth wires 234 and 244 and the first to third additional wires 314, 324 and 334.

The molding layer 500 may be formed through a molding process of filling an empty space of a molding die (not shown) with a molding material and then curing the molding material. When the molding layer 500 is formed, pressure caused by the flow of the molding material may be applied to the first to fourth wires 214, 224, 234 and 244 and the first to third additional wires 314, 324 and 334. However, since the third and fourth conductive lines 234 and 244 and the first to third additional conductive lines 314, 324, and 334 have relatively small lengths, bending may be prevented and/or reduced. In addition, since both ends of the first and second conductive lines 214 and 224 are fixed, bending may be prevented or reduced.

Referring to fig. 4, a grinding process may be performed on the molding layer 500. The grinding process may include a mechanical or chemical polishing process.

Through the grinding process, the molding layer 500 may have a flat surface 501 located at a predetermined height from the first surface 101 of the carrier substrate 100. The height of the planar surface 501 may be greater than the height of the top surface of the chip stack 200. The other ends of the third and fourth wires 234 and 244 and the first to third additional wires 314, 324, and 334 may be exposed to the flat surface 501 in a state of being located at the same height as the flat surface 501 of the molding layer 500.

Referring to fig. 5, an encapsulation redistribution layer 600 may be formed on the planar surface 501 of the molding layer 500.

The process of forming the encapsulating redistribution layer 600 will be described below. First, a first package redistribution dielectric layer 626 may be formed on the planar surface 501 of the molding layer 500. The first package redistribution dielectric layer 626 may be patterned to have openings that expose the other ends of the third and fourth conductive lines 234 and 244 and the other ends of the first through third additional conductive lines 314, 324, and 334. A package redistribution conductive layer 622 may then be formed on the first package redistribution dielectric layer 626. The package redistribution conductive layer 622 may be buried (buried) in the opening of the first package redistribution dielectric layer 626, thereby being electrically coupled to the other ends of the third and fourth conductive lines 234 and 244 and the other ends of the first to third additional conductive lines 314, 324, and 334, and patterned in various shapes. A second package redistribution dielectric layer 624 may then be formed over the first package redistribution dielectric layer 626 and the package redistribution conductive layer 622. The second package redistribution dielectric layer 624 may be patterned with openings that expose portions of the package redistribution conductive layer 622.

Subsequently, external connection terminals 700 may be formed on the package redistribution layer 600 to electrically couple to the package redistribution conductive layer 622 through the openings of the second package redistribution dielectric layer 624. In one embodiment, solder balls may be used as the external connection terminals 700. However, the present embodiment is not limited thereto, and various types of electrical connectors may be used.

The carrier substrate 100 may then be removed. The carrier substrate 100 may be removed at any step after the molding layer 500 is formed.

Through the above processes, the semiconductor package according to the embodiment may be manufactured.

Referring again to fig. 5 and 2C, the semiconductor package according to an embodiment may include a chip stack 200, a bridge unit 300, third and fourth conductive lines 234 and 244, first and second conductive lines 214 and 224, and first to third additional conductive lines 314, 324, and 334. The chip stack 200 may include first to fourth semiconductor chips 210, 220, 230, and 240, the first to fourth semiconductor chips 210, 220, 230, and 240 having first to third chip pads 212, 222, and 232 and a fourth chip pad 242 formed at a fourth active surface 246, the first to third chip pads 212, 222, and 232 being formed at the other side edge (e.g., left edge) exposed when the semiconductor chips are stacked in a manner offset to one side (e.g., right side), that is, the exposed portions 216A, 226A, and 236A of the first to third active surfaces 216, 226, and 236, respectively. The bridge unit 300 may be formed at the other side (e.g., the left side) of the chip stack 200 while being spaced apart from the chip stack 200. The third and fourth conductive lines 234 and 244 may extend in a vertical direction in a state where one ends thereof are connected to the third and fourth chip pads 232 and 242. The first and second conductive lines 214 and 224 may have one ends connected to the first and second chip pads 212 and 222 and the other ends connected to the bridge unit 300 (or, specifically, the redistribution layer 320). The first through third additional conductive lines 314, 324, and 334 may extend in a vertical direction from the redistribution layer 320 in a state of being electrically coupled to the first conductive line 214 and the second conductive line 224 through the redistribution layer 320.

The semiconductor package according to an embodiment may further include an encapsulation redistribution layer 600 and an external connection terminal 700 formed on the flat surface 501 of the molding layer 500. Since the package redistribution layer 600 may be formed in an area defined by the molding layer 500, the semiconductor package according to an embodiment may be a fan-out (fan-out) semiconductor package.

Since components of the semiconductor package have already been described in describing the manufacturing method, a detailed description thereof is omitted herein.

The semiconductor package and the method of manufacturing the same, which have been described so far, can obtain the following effects.

First, in a semiconductor package including a plurality of stacked semiconductor chips that need to be connected to vertical wires having different lengths, the vertical wires having a relatively large length may be replaced with wires connected to and extending from a bridge unit. Accordingly, the length of the vertical wire in the semiconductor package can be set to a relatively small length. As a result, sweeping of the vertical wires can be prevented and/or reduced, so that various defects can be prevented.

In addition, the structure of the redistribution layer of the bridge unit and the layout of the conductive lines connected to the redistribution layer may be optimized to optimize the manufacturing process of the semiconductor package.

In one embodiment, forming one bridge unit corresponding to one chip stack has been described. However, two or more chip stacks may share one bridge unit. This structure will be described with reference to fig. 7A and 7B.

Fig. 7A and 7B are a sectional view and a plan view illustrating a semiconductor package according to an embodiment.

Referring to fig. 7A and 7B, a first chip stack 200, a bridge unit 300 ', and a second chip stack 200' may be disposed on the first surface 101 of the carrier substrate 100.

The first chip stack 200 is substantially identical to the chip stack 200 of the above-described embodiment and is therefore denoted by the same reference numeral. Accordingly, the first to fourth conductive lines 214, 224, 234 and 244 connected to the first chip stack 200 are substantially the same as the first to fourth conductive lines 214, 224, 234 and 244 of the above-described embodiment, and thus are denoted by the same reference numerals.

The second chip stack 200 ' may be located at an opposite side of the first chip stack 200 with the bridge unit 300 ' interposed between the first chip stack 200 and the second chip stack 200 '. That is, when the first chip stack 200 is located at the right side of the bridge unit 300 ', the second chip stack 200 ' may be located at the left side of the bridge unit 300 '.

The second chip stack 200 ' may have a symmetrical structure to the first chip stack 200 with the bridge unit 300 ' interposed between the first chip stack 200 and the second chip stack 200 '. Accordingly, the second chip stack 200 ' may include first to fourth semiconductor chips 210 ', 220 ', 230 ', and 240 ', which are stacked in a manner offset to an opposite side (e.g., left side) of the first chip stack 200. The first to fourth semiconductor chips 210 ', 220', 230 ', and 240' may include first to fourth chip pads 212 ', 222', 232 ', and 242' formed at right edges of the first to fourth semiconductor chips 210 ', 220', 230 ', and 240' and exposed to the outside. The first signal pad 212A 'and the first power supply pad 212B' of the first chip pad 212 'may be formed at positions corresponding to the first signal pad 212A and the first power supply pad 212B of the first chip pad 212, respectively, and the second signal pad 222A' and the second power supply pad 222B 'of the second chip pad 222' may be formed at positions corresponding to the second signal pad 222A and the second power supply pad 222B of the second chip pad 222, respectively. The first to fourth conductive lines 214 ', 224 ', 234 ' and 244 ' of the second chip stack 200 ' may also have a symmetrical structure with the first to fourth conductive lines 214, 224, 234 and 244 of the first chip stack 200.

The bridge unit 300 'may be further extended in the first direction than the above-described bridge unit 300, so that redistribution pads for connection with the second chip stack 200', that is, with the first and second conductive lines 214 'and 224', may be further arranged. Since the first chip stack 200 and the second chip stack 200 'are symmetrical to each other, the first to fourth conductive lines 214, 224, 234, and 244 of the second chip stack 200 and the right half of the redistribution layer 320' of the bridge unit 300 may have the same structure as that of the redistribution layer 320 of the above-described embodiment, and the left half thereof may have a structure symmetrical to the right half. In other words, the right half of the redistribution pads (see P1 'and P2') may have the same arrangement as the redistribution pads 327A and 327B of the above-described embodiments, and the left half thereof may be symmetrically arranged with the right half. Accordingly, the first to fourth wires 214, 224, 234 and 244 and the first to third additional wires 314, 324 and 334 connected to the right half of the redistribution pad may be formed in substantially the same manner as the first to fourth wires 214, 224, 234 and 244 and the first to third additional wires 314, 324 and 334 of the above-described embodiment, and the first to fourth wires 214 ', 224 ', 234 ' and 244 ' and the first to third additional wires 314 ', 324 ' and 334 ' connected to the left half of the redistribution pad may be formed symmetrically to the first to fourth wires 214, 224, 234 and 244 and the first to third additional wires 314, 324 and 334.

The package according to the present embodiment is substantially the same as the package according to the above-described embodiment except that the second chip stack 200 'and the wires 214' to 244 'and 314' to 334 'connected to the second chip stack 200' are symmetrical to the first chip stack 200 and the wires 214 to 244 and 314 to 334 connected to the first chip stack 200, and thus, the redistribution layer 320 'of the bridge unit 300' further includes pads for connection of the wires 214 'to 244' and 314 'to 334' that are symmetrically arranged to the pads to which the wires 214 to 244 and 314 to 334 are connected. Therefore, detailed descriptions of the respective components of the package according to the present embodiment are omitted herein.

According to the embodiment, defects of the semiconductor package may be avoided and a method for manufacturing the semiconductor package may be facilitated.

Fig. 8 shows a block diagram of an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of memory 7810 and memory controller 7820 may include at least one of a semiconductor package according to the described embodiments.

The memory 7810 may include a nonvolatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 to read out stored data or store data in response to a read/write request from the host 7830.

Fig. 9 shows a block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, input/output device 8712, and memory 8713 may be coupled to one another by a bus 8715, with the bus 8715 providing a path through which data moves.

In one embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 can store data and/or commands to be executed by the controller 8711, and the like.

The memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a Solid State Disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

Electronic system 8710 may further include an interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be of a wired or wireless type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If electronic system 8710 represents a device capable of performing wireless communication, electronic system 8710 may be used in a communication system using CDMA (code division multiple access), GSM (global system for mobile communication), NADC (north american digital cellular network), E-TDMA (enhanced time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband internet access) technology.

Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2019-0118014, filed on 25.9.2019, the entire contents of which are incorporated herein by reference.