阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 新居雅人 于 2020-02-21 设计创作，主要内容包括：实施方式提供一种能够确保各晶片间的接合强度及导通性的半导体装置。实施方式的半导体装置具有第1晶片、第1配线层、第1绝缘层、第1电极、第2晶片、第2配线层、第2绝缘层、第2电极和第1层。第1电极具有第1面、第2面、第3面及第4面。第2电极具有第5面、第6面、第7面、第2侧面及第8面。第1层设于第4面与第1绝缘层中的将第4面包围的部分之间,从第3面在第1方向上远离而设置。(The embodiment provides a semiconductor device capable of ensuring bonding strength and conductivity between wafers. The semiconductor device of the embodiment has a 1 st wafer, a 1 st wiring layer, a 1 st insulating layer, a 1 st electrode, a 2 nd wafer, a 2 nd wiring layer, a 2 nd insulating layer, a 2 nd electrode, and a 1 st layer. The 1 st electrode has a 1 st surface, a 2 nd surface, a 3 rd surface and a 4 th surface. The No. 2 electrode has a No. 5 surface, a No. 6 surface, a No. 7 surface, a No. 2 side surface and a No. 8 surface. The 1 st layer is provided between the 4 th surface and a portion of the 1 st insulating layer surrounding the 4 th surface, and is provided apart from the 3 rd surface in the 1 st direction.)

1. A kind of semiconductor device is provided, in which,

comprising:

1, a first wafer;

a 1 st wiring layer provided on the 1 st wafer;

a 1 st insulating layer provided on one side of the 1 st wiring layer in a 1 st direction;

a 1 st electrode provided in the 1 st insulating layer and having a 1 st surface connected to the 1 st wiring layer, a 2 nd surface located at a position distant from the first surface on one side in the 1 st direction, a 3 rd surface located at a position distant from the 1 st surface than the 2 nd surface on one side in the 1 st direction, a 1 st side surface facing the 2 nd surface from the 1 st surface, and a 4 th surface facing the 3 rd surface from the 2 nd surface;

a 2 nd wafer;

a 2 nd wiring layer provided on the 2 nd wafer;

a 2 nd insulating layer provided on the other side in the 1 st direction with respect to the 2 nd wiring layer;

a 2 nd electrode provided in the 2 nd insulating layer and having a 5 th surface connected to the 2 nd wiring layer, a 6 th surface located at a position distant from the 5 th surface on the other side in the 1 st direction, a 7 th surface located at a position distant from the 5 th surface than the 6 th surface on the other side in the 1 st direction and connected to the 3 rd surface, a 2 nd side surface facing the 6 th surface from the 5 th surface, and an 8 th surface facing the 7 th surface from the 6 th surface; and

and a 1 st layer provided between the 4 th surface and a portion of the 1 st insulating layer surrounding the 4 th surface, the 1 st layer being provided apart from the 3 rd surface in the 1 st direction.

2. The semiconductor device as set forth in claim 1,

the second insulating layer has a 2 nd layer provided between the 8 th surface and a portion of the 2 nd insulating layer surrounding the 8 th surface, and provided apart from the 7 th surface.

3. The semiconductor device as set forth in claim 1,

the 3 rd surface is longer in a 2 nd direction intersecting the 1 st direction than the 2 nd surface.

4. The semiconductor device as set forth in claim 1,

the 1 st layer further extends between the 2 nd surface and a portion of the 1 st insulating layer on the other side in the 1 st direction with respect to the 2 nd surface, between the 1 st surface and a portion of the 1 st insulating layer surrounding the 1 st surface, and between the 1 st surface and the 1 st wiring layer;

the 1 st surface is connected to the 1 st wiring layer via the 1 st layer.

5. The semiconductor device as set forth in claim 1,

the 1 st electrode is made of a conductor;

the 1 st layer is disposed on the 4 th surface of the 1 st electrode.

6. The semiconductor device as set forth in claim 1,

a portion of the 1 st electrode is disposed between the 1 st layer and the 3 rd face.

7. The semiconductor device as set forth in claim 2,

the 1 st layer and the 2 nd layer contain titanium.

8. The semiconductor device as set forth in claim 1,

the 1 st electrode and the 2 nd electrode contain copper.

9. The semiconductor device as set forth in claim 1,

a 3 rd layer is provided between the 1 st layer and the 1 st insulating layer surrounding the 4 th surface.

10. A kind of semiconductor device is provided, in which,

comprising:

1, a first wafer;

a 1 st wiring layer provided on the 1 st wafer;

a 1 st insulating layer provided above the 1 st wiring layer; and

and an electrode including a 1 st portion, a 2 nd portion, and a 3 rd portion, the 1 st portion being provided in the 1 st insulating layer, connected to the 1 st wiring layer, having a 1 st length in a 1 st direction parallel to a surface of the 1 st wafer, the 2 nd portion being provided in the 1 st insulating layer, being integral with the 1 st portion, having a 2 nd length greater than the 1 st length in the 1 st direction, and a 3 rd length greater than the 2 nd length in the 1 st direction, the 3 rd portion being provided on the 1 st insulating layer, connected to the 2 nd portion, in a 2 nd insulating layer provided below the 2 nd wafer provided with the 2 nd wiring layer, and having a 4 th length smaller than the 3 rd length in the 1 st direction.

11. The semiconductor device as set forth in claim 10,

the electrode further includes a 4 th portion, the 4 th portion being provided in the 2 nd insulating layer, connected to the 2 nd wiring layer, integrated with the 3 rd portion, and having a 5 th length smaller than the 4 th length in the 1 st direction.

12. The semiconductor device as set forth in claim 10,

a 1 st layer is arranged between the 1 st insulating layer and the 2 nd part of the electrode, and a 2 nd layer is also arranged between the 2 nd insulating layer and the 3 rd part of the electrode;

in a cross section cutting off the 1 st wiring layer, the 1 st insulating layer, the 2 nd wiring layer, the 1 st section, the 2 nd section, and the 3 rd section,

the 2 nd length is a length between 2 of the 1 st layers occurring at 2 borderlines of the 1 st insulating layer and the 2 nd portion,

the 4 th length is a length between the 2 nd layer occurring at 2 boundary lines of the 2 nd insulating layer and the 3 rd portion.

13. The semiconductor device as set forth in claim 12,

the 1 st layer and the 2 nd layer contain titanium.

14. The semiconductor device as set forth in claim 10,

the electrode contains copper.

15. A kind of semiconductor device is provided, in which,

comprising:

a 1 st wafer provided with a 1 st signal line;

an insulating layer provided on the 1 st signal line;

the 2 nd wafer is arranged on the insulating layer and is provided with a 2 nd signal line;

a 1 st electrode portion which is provided on the 1 st signal line so as to be surrounded by the insulating layer and is electrically connected to the 1 st signal line;

a 2 nd electrode portion which is provided on the 1 st electrode portion so as to be surrounded by the insulating layer, is connected to the 1 st electrode portion, and has a cross-sectional area larger than a cross-sectional area of the 1 st electrode portion in a direction intersecting a lamination direction of the 1 st wafer and the 2 nd wafer;

a 1 st conductive layer provided between the 2 nd electrode portion and a portion of the insulating layer surrounding the 2 nd electrode portion;

a 3 rd electrode portion which is provided on the 2 nd electrode portion and the 1 st conductive layer so as to be surrounded by the insulating layer, is connected to the 2 nd electrode portion, and has a cross-sectional area larger than a cross-sectional area of the 2 nd electrode portion in the intersecting direction;

a 4 th electrode portion which is provided on the 3 rd electrode portion so as to be surrounded by the insulating layer, is connected to the 3 rd electrode portion, and has a cross-sectional area larger than a cross-sectional area of the 2 nd electrode portion in the intersecting direction;

a 5 th electrode portion which is provided on the 4 th electrode portion so as to be surrounded by the insulating layer, is connected to the 4 th electrode portion, and has a cross-sectional area smaller than that of the 4 th electrode portion in the intersecting direction;

a 2 nd conductive layer provided between the 5 th electrode portion and a portion of the insulating layer surrounding the 5 th electrode portion, and provided on the 4 th electrode portion; and

and a 6 th electrode portion which is provided on the 5 th electrode portion so as to be surrounded by the insulating layer, is connected to the 5 th electrode portion, is electrically connected to the 2 nd signal line, and has a cross-sectional area smaller than a cross-sectional area of the 5 th electrode portion in the intersecting direction.

16. The semiconductor device as set forth in claim 15,

the cross-sectional area of the 2 nd electrode portion increases as it is farther from the 1 st electrode portion.

17. The semiconductor device as set forth in claim 15,

the 3 rd electrode portion has a 1 st region connected to the 4 th electrode portion and a 2 nd region facing the insulating layer.

18. The semiconductor device as set forth in claim 15,

the cross-sectional area of the 2 nd electrode portion along the intersecting direction is 3 times or more larger than the largest cross-sectional area of the 1 st electrode portion.

19. The semiconductor device as set forth in claim 15,

further provided with:

a 3 rd conductive layer provided between the 2 nd electrode portion and a lower portion of the insulating layer, and connected to the 1 st conductive layer; and

and a 4 th conductive layer provided between the 1 st electrode portion and a portion of the insulating layer surrounding the 1 st electrode portion, and connected to the 3 rd conductive layer and the 1 st signal line.

20. The semiconductor device as set forth in claim 15,

the 1 st conductive layer and the 2 nd conductive layer contain titanium.

21. The semiconductor device as set forth in claim 15,

the 1 st electrode portion, the 2 nd electrode portion, the 3 rd electrode portion, the 4 th electrode portion, the 5 th electrode portion, and the 6 th electrode portion contain copper.

Technical Field

Embodiments of the present invention relate to a semiconductor device.

Background

As a semiconductor device, a structure has been proposed in which integrated circuits having various functions are individually fabricated on a wafer level, and then the wafers are bonded to each other to form 1 chip.

Disclosure of Invention

The present invention provides a semiconductor device capable of ensuring bonding strength and conductivity between wafers.

A semiconductor device of the technical scheme is provided with a 1 st wafer, a 1 st wiring layer, a 1 st insulating layer, a 1 st electrode, a 2 nd wafer, a 2 nd wiring layer, a 2 nd insulating layer, a 2 nd electrode and a 1 st layer. The 1 st wiring layer is provided on the 1 st wafer. The 1 st insulating layer is provided on the 1 st direction side with respect to the 1 st wiring layer. The 1 st electrode is provided in the 1 st insulating layer, and has a 1 st surface connected to the 1 st wiring layer, a 2 nd surface located at a position distant from the 1 st surface on the 1 st direction side, a 3 rd surface located at a position distant from the 1 st surface than the 2 nd surface on the 1 st direction side, a 1 st side surface facing the 2 nd surface from the 1 st surface, and a 4 th surface facing the 3 rd surface from the 2 nd surface. The 2 nd wiring layer is provided on the 2 nd wafer. The 2 nd insulating layer is provided on the other side of the 1 st direction with respect to the 2 nd wiring layer. The 2 nd electrode is provided in the 2 nd insulating layer, and has a 5 th surface connected to the 2 nd wiring layer, a 6 th surface located at a position distant from the 5 th surface on the other side in the 1 st direction, a 7 th surface located at a position distant from the 5 th surface than the 6 th surface on the other side in the 1 st direction and connected to the 3 rd surface, a 2 nd side surface facing the 6 th surface from the 5 th surface, and an 8 th surface facing the 7 th surface from the 6 th surface. The 1 st layer is provided between the 4 th surface and a portion of the 1 st insulating layer surrounding the 4 th surface, and is provided apart from the 3 rd surface in the 1 st direction.

Drawings

Fig. 1 is an enlarged sectional view showing a semiconductor device according to an embodiment.

Fig. 2 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 3 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 4 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 5 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 6 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 7 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 8 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 9 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 10 is a process diagram for explaining the steps of manufacturing the semiconductor device according to the embodiment.

Fig. 11 is a process diagram for explaining a manufacturing process of a semiconductor device according to the embodiment.

Fig. 12 is an enlarged sectional view corresponding to fig. 1 of a modification of the embodiment.

Fig. 13 is an enlarged sectional view corresponding to fig. 1 of a modification of the embodiment.

Fig. 14 is an enlarged sectional view corresponding to fig. 1 of a modification of the embodiment.

Fig. 15 is an enlarged sectional view corresponding to fig. 1 of a modification of the embodiment.

Fig. 16 is an enlarged sectional view corresponding to fig. 1 of a modification of the embodiment.

Description of the reference symbols

1 … semiconductor device; 21 … 1 st wiring layer (1 st signal layer); 41 … 1 st interlayer insulating layer (1 st insulating layer, insulating layer); 42 … insulating layer 1 (layer 3); 62 … layer 1 (conductive layer 1); 62a … part 1 (conductive layer 1); 62b … part 2 (conductive layer 3); 62c … part 3 (conductive layer 4); 63 … electrode No. 1; 71 … electrode part 1 (part 1); 71a … lower end face (1 st face); 71b … side (1 st side); 72 … electrode part 2 (part 2); 72a … lower end face (2 nd face); 72b … side (4 th side); 73 … electrode part 3 (part 2); 73a … side (4 th surface, 2 nd area), upper surface 73b (3 rd surface, 1 st area); 101 … the 2 nd wiring layer; 111 … nd interlayer insulating layer 2 (2 nd insulating layer); 143 … No. 2 electrode (electrode); 150 … th electrode section 4; 150b … lower surface (7 th surface); 151 … electrode part 5 (part 3); 151a … side (face 8); 151b … upper end face (6 th face); 152 … electrode part 6 (part 4); 152a … upper end face (5 th face); 152b … side (2 nd side).

Detailed Description

Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings.

In the following description, structures having the same or similar functions are given the same reference numerals. Moreover, a repetitive description of these configurations may be omitted. The drawings are schematic or conceptual drawings, and the relationship between the thickness and the width of each part, the ratio of the sizes of the parts, and the like are not necessarily the same as those in reality.

The term "connected" in the present specification is not limited to a case of physical connection, and includes a case of electrical connection. That is, the above-mentioned "connection" is not limited to the case where 2 members are in direct contact with each other, and includes the case where another member is interposed between 2 members. In another aspect, the term "contacting" refers to direct contact. The terms "overlap" and "face" in the present specification are not limited to the case where 2 members directly face each other, and include the case where another member exists between the 2 members. The terms "overlap" and "face" also include the case where respective parts of 2 members overlap or face each other. The "thickness" is a convenient expression and may be referred to as "dimension" instead. Further, the term "face" means that at least a part of 2 members overlap. That is, the "opposed" is not limited to the case where 2 members are stacked over the entire body, but includes the case where 2 members are partially stacked with a shift from each other.

In addition, the X direction, the Y direction, and the Z direction are defined first. The X direction is one of directions substantially parallel to the surfaces of the 1 st module 10 and the 2 nd module 11 (see fig. 1). The Y direction (2 nd direction) is a direction intersecting (e.g., substantially orthogonal to) the X direction among directions substantially parallel to the surfaces of the 1 st module 10 and the 2 nd module 11. The Z direction is a direction substantially orthogonal to the surfaces of the 1 st module 10 and the 2 nd module 11, and is a direction intersecting (e.g., substantially orthogonal to) the X direction and the Y direction. The + Z direction (1 st direction) is a direction from the 2 nd module 11 toward the 1 st module 10 (see fig. 1). the-Z direction is the opposite direction to the + Z direction. In the case where the + Z direction is not distinguished from the-Z direction, the + Z direction is simply referred to as "Z direction". In this specification, "+ Z direction" is sometimes referred to as "up" and "-Z direction" is sometimes referred to as "down". However, these expressions are for convenience, and the direction of gravity is not specified.

Fig. 1 is an enlarged sectional view showing a semiconductor device 1 according to an embodiment. As shown in fig. 1, the semiconductor device 1 is, for example, a memory device. The semiconductor device 1 is configured by stacking a 1 st module 10 and a 2 nd module 11 in the Z direction.

The 1 st block 10 is, for example, a CMOS (Complementary metal oxide semiconductor) block. The 1 st block 10 constitutes more than 1 CMOS circuit. Specifically, the 1 st module 10 includes a 1 st insulating film 20, a 1 st wiring layer (1 st signal layer) 21, and a 1 st connection layer 22.

The 1 st insulating film 20 is formed of, for example, silicon oxide (SiO) or the like. The 1 st insulating film 20 may constitute a portion of the 1 st wafer of the 1 st module 10. In the present embodiment, the 1 st wafer is not limited to the substrate of the 1 st module 10 itself, and may be a laminate including a component in which CMOS circuits are laminated in addition to the substrate, as long as the component is provided with the 1 st wiring layer 21. In addition, wafer 1 may or may not include a substrate.

The 1 st wiring layer 21 is provided in plural at intervals in the X direction and the Y direction, for example. The 1 st wiring layer 21 is divided by a 1 st insulating film 24.

The 1 st connection layer 22 includes a 1 st foundation layer 40, a 1 st interlayer insulating layer (1 st insulating layer, insulating layer) 41, a 1 st insulating layer (3 rd layer) 42, and a 1 st pad portion 43. The 1 st base layer 40 is provided above the 1 st module 10 (+ Z direction, 1 st direction side). First base layer 1 is formed by, for example, adding silicon carbide (SiCN) or the like to nitrogen.

The 1 st interlayer insulating layer 41 is provided on the 1 st base layer 40. The thickness (thickness in the Z direction) of the 1 st interlayer insulating layer 41 is thicker than the 1 st foundation layer 40. In this embodiment, the 1 st interlayer insulating layer 41 is formed of, for example, silicon oxide (SiO) or the like.

The 1 st connection layer 22 is formed with a 1 st recess 48 penetrating the 1 st connection layer 22 in the Z direction. The 1 st recessed portion 48 overlaps with any one of the 1 st wiring layers 21 in a plan view seen from the Z direction. The shape of the 1 st recessed portion 48 in plan view may be rectangular, circular, polygonal, or the like, and may be appropriately modified. The 1 st recessed portion 48 is formed in a stepped shape whose outer shape is gradually reduced in a plan view as it goes downward (-Z direction, the other side in the 1 st direction). Specifically, the 1 st recess 48 includes the 1 st pad recess 50 and the 1 st via hole 51.

The 1 st pad recess 50 is formed in a tapered shape whose outer shape is gradually reduced in a plan view as going downward. The upper end of the 1 st pad recess 50 reaches the upper end of the 1 st interlayer insulating layer 41. The lower end of the 1 st pad recess 50 is located within the 1 st interlayer insulating layer 41. The 1 st via hole 51 extends downward from the center portion in a plan view in the 1 st pad recess 50. The 1 st via hole 51 is formed in a tapered shape whose outer shape is gradually reduced in a downward direction in a plan view. The 1 st via hole 51 penetrates the 1 st interlayer insulating layer 41 and the 1 st underlying layer 40 in the Z direction. The lower end of the 1 st via hole 51 reaches the lower surface of the 1 st matrix layer 40. That is, the 1 st wiring layer 21 is connected to the 1 st pad portion 43 in the 1 st recess 48 through the lower end of the 1 st via hole 51.

The 1 st insulating layer 42 is formed following the inner surface of the 1 st recessed portion 48, and is also formed between the 1 st pad section 43 and the 1 st wiring layer 21. The 1 st insulating layer 42 has a function of suppressing diffusion of the 1 st pad portion 43 to the periphery of the 1 st pad portion 43 and the like as a barrier metal. In this embodiment mode, the 1 st insulating layer 42 is formed of, for example, tantalum (Ta), tantalum nitride (TaN), or the like.

The 1 st pad portion 43 is embedded in the 1 st recess 48. Specifically, the 1 st pad portion 43 includes the 1 st layer (1 st conductive layer) 62 and the 1 st electrode 63. The 1 st layer 62 is formed to follow the inner surface of the 1 st insulating layer 61 in the 1 st recess 48. In the present embodiment, the film thickness of the 1 st layer 62 (the thickness along the normal direction of the inner surface of the 1 st recess 48) is thicker than the film thickness of the 1 st insulating layer 42. However, the film thickness of the 1 st layer 62 may be thinner than the film thickness of the 1 st insulating layer 42. The 1 st layer 62 is formed of a material having conductivity and a lower etching rate than the 1 st electrode 63. As such a material, a material containing titanium (Ti) is preferably used in this embodiment. The 1 st layer 62 may be made of an insulating material. In this case, it is preferable that the 1 st layer 62 is not sandwiched between the 1 st wiring layer 21 and the 1 st electrode 63.

The upper end of the 1 st layer 62 is located below the upper end of the 1 st interlayer insulating layer 41. Therefore, in the 1 st recess 48, a receiving portion 65 is formed between the inner surface of the 1 st recess 48 (the inner surface of the 1 st insulating layer 61) and the upper end of the 1 st layer 62. The inner surface of the receiving portion 65 faces upward and the inside of the 1 st recess 48. A portion surrounded by the virtual line L1 extending along the inner surface of the 1 st layer 62, the virtual line L2 extending along the upper end of the 1 st interlayer insulating layer 41, the upper end of the 1 st layer 62, and the inner surface of the 1 st insulating layer 61 is the volume S of the housing portion 65.

In the present embodiment, the receiving portion 65 is formed to have a uniform depth in the Z direction over the entire circumference of the 1 st recess 48. In the present embodiment, the depth of the receiving portion 65 is deeper than the thickness of the 1 st layer 62. However, the receiving portion 65 may be formed at least partially around the 1 st recess 48. The Z-direction depth of the receiving portion 65 may not be the same.

The 1 st electrode 63 is provided in the 1 st recess 48. Specifically, the 1 st electrode 63 includes a 1 st electrode portion (1 st part) 71, a 2 nd electrode portion (2 nd part) 72, and a 3 rd electrode portion (2 nd part) 73. The 1 st electrode portion 71 is embedded inside the 1 st via hole 51 following the inner surface shape of the 1 st layer 62. The 1 st electrode portion 71 is surrounded by the 1 st underlying layer 40 and the 1 st interlayer insulating layer 41. The lower end surface (1 st surface) 71a of the 1 st electrode portion 71 is electrically connected to the 1 st wiring layer 21 via the 1 st insulating layer 42 and the 1 st layer 62. The side surfaces (1 st side surfaces) 71b of the 1 st electrode portion 71 facing in the Y direction extend in directions away from each other as they face upward. Therefore, the sectional area of the 1 st electrode portion 71 in the XY plane gradually increases upward.

The 2 nd electrode portion 72 is embedded inside the 1 st pad recess 50 following the inner surface shape of the 1 st layer 62. The periphery of the 2 nd electrode portion 72 is surrounded by the 1 st interlayer insulating layer 41. The 2 nd electrode portion 72 is integrally provided on the 1 st electrode portion 71. The lower end surface 72a of the 2 nd electrode portion 72 (the 2 nd surface: the boundary portion with the 1 st electrode portion 71) is electrically connected to the upper end of the 1 st electrode portion 71. The lower end surface 72a of the 2 nd electrode portion 72 is spaced upward from the lower end surface 71a of the 1 st electrode portion 71, and extends outward from the upper end of the 1 st electrode portion 71 to the outer peripheral side. The minimum length (2 nd length) D2 of the 2 nd electrode portion 72 in the Y direction is longer than the maximum length (1 st length) D1 of the 1 st electrode portion 71 in the Y direction. The minimum length D2 of the 2 nd electrode portion 72 is the length of the lower end surface 72a of the 2 nd electrode portion 72, and is the distance between the inner surfaces of the 1 st layer 62. The maximum length D1 of the 1 st electrode portion 71 is the length of the 1 st electrode portion 71 in the Y direction at the upper end thereof.

The side surfaces (4 th surfaces) 72b of the 2 nd electrode portion 72 facing in the Y direction extend in directions away from each other as they face upward. Therefore, the sectional area of the 2 nd electrode portion 72 gradually increases upward. The 2 nd electrode portion 72 has a larger cross-sectional area in the XY plane than the 1 st electrode portion 71. In the present embodiment, the maximum cross-sectional area of the 2 nd electrode portion 72 is preferably 3 times or more the maximum cross-sectional area of the 1 st electrode portion 71.

The 3 rd electrode portion 73 is integrally provided on the 2 nd electrode portion 72 inside the 1 st pad recess 50. The length of the upper surface (3 rd surface, 1 st region) 73b of the 3 rd electrode portion 73 in the Y direction is longer than the length of the lower end surface 72a of the 2 nd electrode portion 72 in the Y direction. In the present embodiment, a case where the 3 rd surface of the 1 st electrode 63 is the upper surface 73b of the 3 rd electrode portion 73 will be described. In this case, the upper surface 73b may be a surface including one line segment appearing in a cross section orthogonal to the Z direction at a boundary portion between the 1 st block 10 and the 2 nd block 11, for example, or the 3 rd surface of the 1 st electrode 63 may be a surface orthogonal to the Z direction at an arbitrary position in the Z direction in the 3 rd electrode portion 73.

The minimum length (3 rd length) D3 of the 3 rd electrode portion 73 in the Y direction is longer than the maximum length D2 of the 2 nd electrode portion 72 in the Y direction. In the 3 rd electrode portion 73, side surfaces 73a facing each other in the Y direction extend in directions away from each other as they face upward. Thus, in the present embodiment, the minimum length of the 3 rd electrode portion 73 is the length of the 3 rd electrode portion 73 in the Y direction at the lower end. The 3 rd electrode portion 73 has a larger cross-sectional area in the XY plane than the 2 nd electrode portion 72. Specifically, the sectional area of the 3 rd electrode portion 73 gradually increases upward.

The portion of the 3 rd electrode portion 73 that protrudes further toward the outer peripheral side than the 2 nd electrode portion 72 constitutes a protruding portion 74 located on the 1 st layer 62. In the present embodiment, the extension portion 74 is formed over the entire circumference of the 3 rd electrode portion 73. The protruding portion 74 is embedded in the receiving portion 65 without a gap. Thus, a portion of the 1 st electrode 63 is disposed between the upper end of the 1 st layer 62 and the upper surface 73b of the 3 rd electrode portion 73.

In this way, the 1 st insulating layer 42 extends between the lower end face 71a of the 1 st electrode portion 71 and the 1 st wiring layer 21, between the side face 71b of the 1 st electrode portion 71 and the 1 st interlayer insulating layer 41, between the lower end face 72a of the 2 nd electrode portion 72 and the 1 st interlayer insulating layer 41, between the side face 72b of the 2 nd electrode portion 72 and the 1 st interlayer insulating layer 41, and between the side face 73a of the 3 rd electrode portion 73 and the 1 st interlayer insulating layer 41. On the other hand, the 1 st layer 62 extends between the lower end face 71a of the 1 st electrode portion 71 and the 1 st wiring layer 21, between the side face 71b of the 1 st electrode portion 71 and the 1 st interlayer insulating layer 41, between the lower end face 72a of the 2 nd electrode portion 72 and the 1 st interlayer insulating layer 41, and between the side face 72b of the 2 nd electrode portion 72 and the 1 st interlayer insulating layer 41. In this case, a portion of the 1 st layer 62 located between the side surface 72b of the 2 nd electrode portion 72 and the 1 st interlayer insulating layer 41 constitutes the 1 st portion (1 st conductive layer) 62 a. A portion of the 1 st layer 62 located between the lower end face 72a of the 2 nd electrode portion 72 and the 1 st interlayer insulating layer 41 constitutes a 2 nd portion (3 rd conductive layer) 62 b. Further, a portion of the 1 st layer 62 located between the side face 71b of the 1 st electrode portion 71 and the 1 st interlayer insulating layer 41 constitutes a 3 rd portion (4 th conductive layer) 62 c.

Therefore, the 1 st layer 62 is not sandwiched between the 3 rd electrode portion 73 and the 1 st insulating layer 61 in a plane passing through the 3 rd electrode portion 73 in the XY plane. On the other hand, in a plane passing through the 1 st electrode portion 71 in the XY plane, the 1 st layer 62 is sandwiched between the 1 st electrode portion 71 and the 1 st insulating layer 61.

The 2 nd module 11 is, for example, a unit (セル) module. The 2 nd block 11 includes a plurality of memory cells charged and discharged by the CMOS circuit. For example, the 2 nd module 11 includes a 2 nd insulating film 100, a 2 nd wiring layer 101, and a 2 nd connection layer 102.

The 2 nd insulating film 100 is formed of, for example, silicon oxide (SiO) or the like. The 2 nd insulating film 100 may also constitute a part of the 2 nd wafer of the 2 nd module 11. In the present embodiment, the 2 nd wafer described above is not limited to the substrate of the 2 nd module 11 itself as long as it is a member provided with the 2 nd wiring layer 101, and may be a laminate including a member in which memory cells are laminated in addition to the substrate. In addition, wafer No. 2 may or may not include a substrate.

The 2 nd wiring layer 101 is provided in plural at intervals in the X direction and the Y direction, for example. Each 2 nd wiring layer 101 is divided by a 2 nd insulating film 100.

The 2 nd connecting layer 102 is located below the 2 nd insulating film 100. The 2 nd connecting layer 102 is joined to the 1 st connecting layer 22 to connect the 1 st module 10 and the 2 nd module 11 to each other. The 2 nd connecting layer 102 includes a 2 nd base layer 110, a 2 nd interlayer insulating layer (2 nd insulating layer) 111, a 2 nd insulating layer 112, and a 2 nd pad portion 113, similarly to the 1 st connecting layer 22. The 2 nd connecting layer 102 is formed vertically symmetrically with respect to the XY plane and the 1 st connecting layer 22 described above. In the following description, the same structure as that of the 1 st connecting layer 22 will be omitted as appropriate.

The 2 nd connection layer 101 is formed with a 2 nd recess 120 penetrating the 2 nd connection layer 101 in the Z direction. The 2 nd concave portion 120 faces the 1 st concave portion 48 in the Z direction.

The 2 nd pad recess 130 in the 2 nd recess 120 is formed in a tapered shape whose outer shape is gradually reduced as viewed from above. The upper end of the 2 nd pad recess 130 is located within the 2 nd interlayer insulating layer 103. The lower end of the 2 nd pad recess 130 reaches the lower surface of the 2 nd interlayer insulating layer 103. The 2 nd via hole 131 in the 2 nd recess 120 extends upward from the center portion in the 2 nd pad recess 130 in plan view. The 2 nd via hole 131 is formed in a tapered shape whose outer shape is gradually reduced in a plan view as going upward. The 2 nd via hole 131 penetrates the 2 nd interlayer insulating layer 111 and the 2 nd base layer 110 in the Z direction. The upper end of the 2 nd via hole 131 reaches the upper surface of the 2 nd substrate layer 110. That is, the 2 nd wiring layer 102 is connected to the 2 nd pad part 113 in the 2 nd concave part 120 through the upper end of the 2 nd via hole 131.

The 2 nd insulating layer 112 is formed following the inner surface of the 2 nd recessed portion 120, and is also formed between the 2 nd pad portion 113 and the 2 nd wiring layer 102. The 2 nd pad portion 113 is buried in the 2 nd concave portion 120. Specifically, the 2 nd pad portion 113 includes a 2 nd layer (2 nd conductive layer) 142 and a 2 nd electrode (electrode) 143. The 2 nd layer 142 is formed to follow the inner surface of the 2 nd insulating layer 112 in the 2 nd recess 120. The 2 nd layer 142 is formed of a material having conductivity and having a lower etching rate than the 2 nd electrode 143.

The lower end of the 2 nd layer 142 is located above the lower surface of the 2 nd interlayer insulating layer 111. Therefore, in the 2 nd recess 120, a receiving portion 149 is formed between the inner surface of the 2 nd recess 120 (the inner surface of the 2 nd insulating layer 112) and the lower end of the 2 nd layer 142. The inner surface of the receiving portion 149 faces downward and toward the inside of the 2 nd recess 120.

The 2 nd electrode 143 is provided in the 2 nd recess 120. Specifically, the 2 nd electrode 143 includes a 4 th electrode portion 150, a 5 th electrode portion (3 rd portion) 151, and a 6 th electrode portion (4 th portion) 152. The 4 th electrode portion 150 is provided on the 3 rd electrode portion 73 inside the 2 nd pad recess portion 130. The length of the lower surface (7 th surface) 150b of the 4 th electrode part 150 in the Y direction is longer than the length of the upper end surface 151b of the 5 th electrode part 151 in the Y direction. In the present embodiment, a case where the 7 th surface of the 2 nd electrode 143 is the lower surface 150b of the 4 th electrode portion 150 will be described. In this case, the lower surface 150b may be a surface including one line segment appearing in a cross section orthogonal to the Z direction at a boundary portion between the 1 st block 10 and the 2 nd block 11, for example, or the 7 th surface of the 2 nd electrode 143 may be a surface orthogonal to the Z direction at an arbitrary position in the Z direction in the 4 th electrode part 150.

The minimum length D4 of the 4 th electrode part 150 in the Y direction is longer than the maximum length D2 of the 2 nd electrode part 72. The 4 th electrode portion 150 has a larger cross-sectional area in the XY plane than the 2 nd electrode portion 72. In the present embodiment, the side surfaces 150a of the 4 th electrode portion 150 facing in the Y direction extend in directions away from each other as they face downward. In the illustrated example, the cross-sectional area of the 4 th electrode portion 150 gradually increases downward.

The portion of the 4 th electrode portion 150 located below the 2 nd layer 142 constitutes a protruding portion 154 protruding to the outer peripheral side of the inner surface of the 2 nd layer 142. In the present embodiment, the extension portion 154 is formed over the entire circumference of the 4 th electrode portion 150. The extension portion 154 is embedded in the receiving portion 149 without a gap.

The 5 th electrode portion 151 follows the inner surface shape of the 2 nd layer 142 and is embedded inside the 2 nd pad recess 130. The 5 th electrode portion 151 is surrounded by the 2 nd interlayer insulating layer 111. The 5 th electrode part 151 is integrally provided on the 4 th electrode part 150. The lower end of the 5 th electrode part 151 is electrically connected to the upper end of the 4 th electrode part 150. The 5 th electrode portion 151 has a smaller cross-sectional area in the XY plane than the 4 th electrode portion 150. The minimum length (4 th length) D5 of the 5 th electrode part 151 in the Y direction is longer than the maximum length D4 of the 4 th electrode part 150. The minimum length D5 of the 5 th electrode part 151 is the length of the upper end surface (6 th surface) 151b of the 5 th electrode part 151, and is the interval between the inner surfaces of the 2 nd layer 142. In the YZ plane, side surfaces (8 th surfaces) 151a of the 5 th electrode portion 151 facing in the Y direction extend in directions away from each other as they face downward. Therefore, the sectional area of the 5 th electrode portion 151 gradually increases downward.

The 6 th electrode portion 152 is embedded inside the 2 nd via hole 131 following the inner surface shape of the 2 nd layer 142. The 6 th electrode portion 152 is surrounded by the 2 nd base layer 110 and the 2 nd interlayer insulating layer 111. The upper end surface (5 th surface) 152a of the 6 th electrode portion 152 is electrically connected to the 2 nd wiring layer 102 via the 2 nd insulating layer 112 and the 2 nd layer 142. The 6 th electrode portion 152 has side surfaces (2 nd side surfaces) 152b facing in the Y direction extending in directions away from each other in a downward direction. The minimum length D4 in the Y direction of the 5 th electrode part 151 is longer than the maximum length (5 th length) D5 in the Y direction of the 6 th electrode part 152. Therefore, the cross-sectional area of the 6 th electrode portion 152 in the XY plane gradually increases downward.

In this way, the 2 nd insulating layer 112 extends between the upper end surface 152a of the 6 th electrode portion 152 and the 2 nd wiring layer 101, between the side surface 152b of the 6 th electrode portion 152 and the 2 nd interlayer insulating layer 111, between the upper end surface 151b of the 5 th electrode portion 151 and the 2 nd interlayer insulating layer 111, between the side surface 151a of the 5 th electrode portion 151 and the 2 nd interlayer insulating layer 111, and between the side surface 150a of the 4 th electrode portion 150 and the 2 nd interlayer insulating layer 111. On the other hand, the 2 nd layer 142 extends between the upper end surface 152a of the 6 th electrode section 152 and the 2 nd wiring layer 101, between the side surface 152b of the 6 th electrode section 152 and the 2 nd interlayer insulating layer 111, between the upper end surface 151b of the 5 th electrode section 151 and the 2 nd interlayer insulating layer 111, and between the side surface 151a of the 5 th electrode section 151 and the 2 nd interlayer insulating layer 111. In this case, a portion of the 2 nd layer 142 located between the side surface 151a of the 5 th electrode portion 151 and the 2 nd interlayer insulating layer 111 constitutes a 4 th portion (2 nd conductive layer) 142 a. A portion of the 2 nd layer 142 located between the upper end face 151b of the 5 th electrode portion 151 and the 2 nd interlayer insulating layer 111 constitutes a 5 th portion 142 b. Further, a portion of the 2 nd layer 142 located between the side surface 152b of the 6 th electrode portion 152 and the 2 nd interlayer insulating layer 111 constitutes a 6 th portion 142 c.

In the present embodiment, in a plane passing through the 4 th electrode portion 150 in the XY plane, only the 2 nd insulating layer 112 and the 4 th electrode portion 150 are located within the 2 nd pad recess portion 130. On the other hand, in a plane passing through the 5 th electrode part 151 in the XY plane, there are the 2 nd insulating layer 112, the 2 nd layer 142, and the 5 th electrode part 151.

The 1 st module 10 and the 2 nd module 11 are connected to each other via the 1 st connection layer 22 and the 2 nd connection layer 102. Specifically, the interlayer insulating layers 41 and 111 are bonded to each other in the Z direction. The pad portions 43 and 113 are bonded to each other with the 3 rd electrode portion 73 and the 4 th electrode portion 150 facing each other in the Z direction.

In the present embodiment, the extension portion 74 is a remaining amount of the 3 rd electrode portion 73 which overflows to the outer peripheral side at the time of bonding the 1 st pad portion 43 and the 2 nd pad portion 113. The extension portion 154 is a remaining amount of the 4 th electrode portion 150 which overflows to the outer peripheral side at the time of bonding the 1 st pad portion 43 and the 2 nd pad portion 113.

Next, a method for manufacturing the semiconductor device 1 will be described. In the following description, a manufacturing process of the 1 st connection layer 22 and a laminating process of the 1 st module 10 and the 2 nd module 11 will be mainly described.

Fig. 2 to 11 are process diagrams for explaining the manufacturing process of the semiconductor device 1. As shown in fig. 2, a 1 st base layer 40 and a 1 st interlayer insulating layer 41 are sequentially stacked on a 1 st insulating film 20 on which a 1 st wiring layer 21 is formed (1 st film forming step). The 1 st underlying layer 40 and the 1 st interlayer insulating layer 41 are formed by, for example, a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.

Next, the 1 st pad portion 43 is formed on the 1 st foundation layer 40 and the 1 st interlayer insulating layer 41. In the present embodiment, the 1 st pad portion 43 is formed by, for example, a dual damascene (dual damascene) method. First, as shown in fig. 3, the 1 st via hole 51 (see fig. 1) is formed in the 1 st underlying layer 40 and the 1 st interlayer insulating layer 41 (via hole forming step). Specifically, first, a lower layer resist film 200, an SOG (Spin ON Glass) layer 201, and an upper layer resist film 202 are sequentially formed ON the 1 st interlayer insulating layer 41 (so-called SMAP (Stacked Mask Process)). Next, the upper layer resist film 202 is exposed and developed, whereby an opening 202a corresponding to the 1 st via hole 51 is formed in the upper layer resist film 202. Then, the SOG film 201 is patterned by etching or the like through the opening 202a, thereby forming an opening 201a corresponding to the 1 st via hole 51 in the SOG film 201. Next, the lower layer resist film 200 is patterned by etching or the like through the opening 201a, thereby forming an opening 200a corresponding to the 1 st via hole 51 in the lower layer resist film 200.

Next, as shown in fig. 4, the 1 st base layer 40 and the 1 st interlayer insulating layer 41 are etched using the lower layer resist film 200 as a mask (etching step). The Etching process is performed by RIE (Reactive Ion Etching), for example. Thereby, the 1 st via hole 51 described above is formed. After the etching step is completed, the lower layer resist film 200 is removed by ashing.

Next, as shown in fig. 5, a 1 st pad recess 50 (see fig. 1) is formed on the 1 st interlayer insulating layer 41 (pad recess forming step). Specifically, after the lower layer resist film 205, the SOG film 206, and the upper layer resist film 207 are formed in the same manner as in the via hole forming step described above, the lower layer is patterned using the openings of the upper layer (for example, the opening 206a and the opening 207a) as a mask. Thereby, the opening 205a corresponding to the 1 st pad recess 50 is formed in the lower layer resist film 205.

Next, as shown in fig. 6, the 1 st interlayer insulating layer 41 is etched using the lower layer resist film 205 as a mask (etching step). The etching process is performed by RIE, for example. Thereby, the 1 st pad recess 50 described above is formed. Next, after the etching step is completed, the lower layer resist film 205 is peeled off by ashing. Thereby, the 1 st recess 48 is formed.

Next, as shown in fig. 7, the 1 st insulating layer 61, the 1 st layer 62, and the seed layer 210 are sequentially formed on the inner surface of the 1 st recess 48 and on the 1 st interlayer insulating layer 41 (the 2 nd film forming step). The seed layer 210 functions as an electrode film for subsequent electroplating and is formed of the same material as the constituent material (e.g., a material containing copper (Cu)) of the 1 st electrode 63 (see fig. 1). The 1 st insulating layer 61, the 1 st layer 62, and the seed layer 210 are formed by, for example, a CVD method, a sputtering method, or the like.

Next, as shown in fig. 8, a plating layer 211 is formed in the 1 st concave portion 48 (1 st electrode forming step). Specifically, the 1 st module 10 formed up to the seed layer 210 is subjected to electroplating using the seed layer 210 as an electrode film. Then, the plating layer 211 is deposited on the seed layer 210. Then, after the module 2 is annealed, the plating layer 211 is planarized by CMP (Chemical Mechanical Polishing) or the like (post-treatment step).

Next, as shown in fig. 9, a bump 212 is formed on the plating layer 211 by electroless plating or the like. The bump 212 is formed of copper (Cu) or the like as in the plating layer 211. The bump 212 is raised upward with respect to the upper surface of the 1 st interlayer insulating layer 41. Further, an intermediate body of the 1 st electrode 63 is formed by the seed layer 210, the plating layer 211, and the bump 212. The ridge portion 212 may be formed by a method other than electroless plating.

Next, as shown in fig. 10, a housing portion 65 is formed in the 1 st recess 48 (housing portion forming step). Specifically, the 1 st module 10 is subjected to wet etching. In this embodiment, an etchant is used in which the etching rate of the 1 st layer 62 is higher than that of the 1 st electrode 63 (seed layer 210, plating layer 211, and bump 212). As such an etchant, for example, alkalis are used.

In the receiving portion forming step, if wet etching is performed, the 1 st layer 62 is etched more actively than the 1 st electrode 63. Thus, in the 1 st recess 48, a receiving portion 65 is formed which is directed upward and inward of the 1 st recess 48 and surrounded by the 1 st insulating layer 61, the 1 st layer 62, and the 1 st electrode 63.

In addition, in the 2 nd module 11, the 2 nd connection layer 101 is also formed by the same method as the method for forming the 1 st connection layer 22 described above.

Next, as shown in fig. 11, the 1 st module 10 and the 2 nd module 11 are bonded to each other (bonding step). Specifically, the modules 10 and 11 subjected to the pretreatment such as the plasma treatment and the water washing treatment are subjected to the annealing treatment in a state where the pad portions 43 and 113 are opposed to each other. The annealing treatment is performed, for example, at a temperature of 250 to 400 ℃ for about 1 hour. Then, the 1 st module 10 and the 2 nd module 11 are brought close to each other, and the 1 st module 10 and the 2 nd module 11 are pressure-bonded to each other. Thereby, in the 1 st module 10 and the 2 nd module 11, the interlayer insulating layers 41 and 101 are bonded to each other (covalent bonding), and the electrodes 63 and 143 of the pad portions 43 and 113 are bonded to each other (metal bonding). Then, the 1 st and 2 nd modules 10 and 11 are returned to normal temperature, and the bonding process is completed.

After the bonding step, if the temperature of the 1 st block 10 and the 2 nd block 11 is lowered, the electrodes 63 and 143 mainly contract. In this case, if the volume of the electrodes 63 and 143 is insufficient with respect to the volume of the 1 st recess 48 and the 2 nd recess 120, stress migration due to contraction of the electrodes 63 and 143 may cause voids to be generated in the 1 st recess 48 or the 2 nd recess 120. In particular, if voids are generated in the via holes 51 and 131, opening failure or the like may occur, and the reliability of conduction may be lowered. On the other hand, if the 1 st module 10 and the 2 nd module 11 are bonded to each other with the electrodes 63 and 143 protruding from the interlayer insulating layers 41 and 111, the portion of the electrodes 63 and 143 that is expanded by pressure bonding is sandwiched between the interlayer insulating layers 41 and 111. This reduces the bonding area between the interlayer insulating layers 41 and 111, and may not provide a desired bonding strength.

In the present embodiment, the bump portions 212 are formed on the pad portions 43 and 113 in a state before the 1 st module 10 and the 2 nd module 11 are bonded. Therefore, in the above-described joining step, when the 1 st block 10 and the 2 nd block 11 are pressed against each other, the ridges 212 are pressed against each other, and the 1 st block 10 and the 2 nd block 11 approach each other.

Here, the expanded portion of the ridge portion 212 is accommodated in the accommodation portions 65 and 149. This can prevent the expanded portion of the ridge portion 212 from protruding from the 1 st concave portion 48 and the 2 nd concave portion 120, and can form a desired amount of the electrodes 63 and 143 in the 1 st concave portion 48 and the 2 nd concave portion 120.

In this way, in the present embodiment, the extension portions 74 of the 1 st pad portion 43 are sandwiched between the 1 st layer 62 and the 2 nd pad portion 113. According to this configuration, by opening the receiving portion 65 above the 1 st layer 62 before the 1 st pad portion 43 and the 2 nd pad portion 113 are bonded, the remaining portion of the 1 st pad portion 43 which is expanded at the time of bonding can be received as the extending portion 74 in the receiving portion 65. That is, in a state before the 1 st pad portion 43 and the 2 nd pad portion 113 are bonded, the 1 st electrode 63 can be raised above the upper surface of the 1 st interlayer insulating layer 41, and therefore, the volume of the 1 st electrode 63 after bonding can be secured. This can suppress generation of voids due to shrinkage of the 1 st electrode 63 after bonding, and can suppress opening defects and the like. Further, since the 1 st electrode 63 that is pressed and expanded can be suppressed from overflowing between the interlayer insulating layers 41 and 111, the bonding strength between the interlayer insulating layers 41 and 111 can be ensured. Further, by forming the extension portion 74, the joint area between the pad portions 43, 113 can be secured. This can suppress the increase in resistance of the 1 st pad portion 43 accompanying the formation of the 1 st layer 62. As a result, the semiconductor device 1 of the present embodiment can ensure the bonding strength and good conductivity between the modules 10 and 11. Further, the volume S of the housing portion 65 and the volume of the bulge portion 212 can be adjusted to adjust the bonding strength generated during contraction.

In the present embodiment, the 1 st layer 62 is formed to follow the inner surface of the 1 st recess 48. With this configuration, the 1 st insulating layer 61, the 1 st layer 62, and the 1 st electrode 63 can be sequentially formed to follow the inner surface of the 1 st recess 48. This can improve the manufacturing efficiency. Further, the 1 st electrode 63 pressed toward the outer peripheral side can be accommodated in the accommodating portion 65 before reaching the interlayer insulating layers 41 and 111. This can effectively prevent the 1 st electrode 63 from protruding into the interlayer insulating layers 41 and 111.

In the present embodiment, the thickness of the 1 st layer 62 is thinner than the depth of the housing section 65. With this configuration, the volume of the housing portion 65 can be more easily ensured while the sectional area of the 1 st electrode 63 orthogonal to the Z direction is ensured. As a result, the 1 st pad portion 43 can be prevented from increasing in resistance with the formation of the 1 st layer 62.

In this embodiment, since the 1 st layer 62 has conductivity, the 1 st pad portion 43 can be suppressed from being increased in resistance as compared with the case where the 1 st layer 62 is formed of an insulating material. The 1 st layer 62 is formed of a material having a higher etching rate than the 1 st electrode 63. According to this structure, the 1 st layer 62 and the 1 st electrode 63 are formed and then etched together, so that the receiving portion 65 can be formed above the 1 st layer 62. This can suppress a decrease in manufacturing efficiency associated with addition of the 1 st layer 62.

In the present embodiment, the following structure is provided: in the bonding step, the 1 st pad portion 43 and the 2 nd pad portion 113, and the 1 st interlayer insulating layer 41 and the 2 nd interlayer insulating layer 111 are bonded to each other while pressing the 1 st pad portion 43 and the 2 nd pad portion 113 against each other to expand a part of the electrodes 63 and 143 into the receiving portion 65. According to this configuration, by forming the housing portion 65 in advance before the joining step, the 1 st module 10 and the 2 nd module 11 approach each other while the swelling portions 212 are pressed and expanded in the joining step. The expanded portion of the ridge portion 212 is accommodated in the accommodation portion 65. This can prevent the expanded portion of the ridge portion 212 from protruding from the 1 st concave portion 48 and the 2 nd concave portion 120, and can form a desired amount of the electrodes 63 and 143 in the 1 st concave portion 48 and the 2 nd concave portion 120.

In the above-described embodiment, the configuration in which the solder pad sections 43 and 113 are entirely overlapped with each other has been described, but the present invention is not limited to this configuration. For example, as shown in fig. 12, the pad portions 43 and 113 may overlap each other at least partially in a plan view. In the above-described embodiment, the case where the pad portions 43 and 113 are formed vertically symmetrically has been described, but the present invention is not limited to this structure. For example, as shown in fig. 13, the depth of the 1 st layer 62 and the 2 nd layer 142 may be different between the pad portions 43 and 113. In the above-described embodiment, the description has been given of the structure in which each of the pad portions 43 and 113 has the 1 st layer 62 and the 2 nd layer 142, but the structure is not limited to this structure. For example, as shown in fig. 14, it is sufficient if at least only the 1 st pad portion 43 has the 1 st layer 62.

In the above-described embodiment, the configuration in which the pad recesses 50 and 130 are formed in the tapered shape has been described, but the configuration is not limited to this. For example, as shown in fig. 15, the pad recesses 50 and 130 may have a uniform outer shape in plan view over the entire Z direction. In the above-described embodiment, the case where the inner surfaces of the recesses 48 and 120 are smooth surfaces has been described, but the present invention is not limited to this configuration. For example, as shown in fig. 16, the inner surfaces of the recesses 48 and 120 may be concave-convex surfaces.

In the above-described embodiment, the structure in which the 1 st layer 62 is formed following the inner surface of the 1 st recess 48 has been described, but the structure is not limited to this structure. The 1 st layer 62 can be formed at any position in the 1 st recess 48 as long as it is recessed from the upper surface of the 1 st interlayer insulating layer 41. In this case, the 1 st layer 62 may extend in a rod-like shape in the Z direction at the center portion in plan view in the 1 st recess 48. Further, the size of the receiving portion 65 can be changed as appropriate by setting the volume S of the receiving portion 65 and the volume of the bulge portion 212 to be equal. In the above-described embodiment, the structure in which both the recesses 48 and 120 penetrate the connection layers 22 and 102 in the Z direction has been described, but the present invention is not limited to this structure. The recesses 48 and 120 may not penetrate the connection layers 22 and 102, as long as they are configured such that at least the 1 st pad portion 43 and the 2 nd pad portion 113 are bonded to each other.

According to at least one embodiment described above, the semiconductor device includes a 1 st wiring layer, a 1 st insulating layer, a 1 st electrode, a 2 nd wafer, a 2 nd wiring layer, a 2 nd insulating layer, a 2 nd electrode, and a 1 st layer. The 1 st wiring layer is provided on the 1 st wafer. The 1 st insulating layer is provided on the 1 st direction side with respect to the 1 st wiring layer. The 1 st electrode is provided in the 1 st insulating layer, and has a 1 st surface connected to the 1 st wiring layer, a 2 nd surface located at a position distant from the 1 st surface on the 1 st direction side, a 3 rd surface located at a position distant from the 1 st surface than the 2 nd surface on the 1 st direction side, a 1 st side surface facing the 2 nd surface from the 1 st surface, and a 4 th surface facing the 3 rd surface from the 2 nd surface. The 2 nd wiring layer is provided on the 2 nd wafer. The 2 nd insulating layer is provided on the other side of the 1 st direction with respect to the 2 nd wiring layer. The 2 nd electrode is provided in the 2 nd insulating layer, and has a 5 th surface connected to the 2 nd wiring layer, a 6 th surface located at a position distant from the 5 th surface on the other side in the 1 st direction, a 7 th surface located at a position distant from the 5 th surface than the 6 th surface on the other side in the 1 st direction and connected to the 3 rd surface, a 2 nd side surface facing the 6 th surface from the 5 th surface, and an 8 th surface facing the 7 th surface from the 6 th surface. The 1 st layer is provided between the 4 th surface and a portion of the 1 st insulating layer surrounding the 4 th surface, and is provided apart from the 3 rd surface in the 1 st direction. With this structure, the bonding strength between the substrates is ensured, and good conductivity is obtained.

Hereinafter, a plurality of semiconductor devices will be described.

[1] A semiconductor device is provided with: a 1 st insulating layer formed with a 1 st recess recessed in a 1 st direction; a 1 st pad part provided in the 1 st recess part and having a 1 st conductor; a 2 nd insulating layer in which a 2 nd recessed portion is formed to face the 1 st recessed portion in the 1 st direction, and which is laminated in the 1 st direction with respect to the 1 st insulating layer; and a 2 nd pad portion including a 2 nd conductor and an interlayer, the 2 nd conductor including a main portion extending in the 1 st direction in the 2 nd recess and an extension portion extending in the 2 nd direction intersecting the 1 st direction from an end portion of the main portion in the vicinity of the 1 st pad portion, the interlayer being provided on an opposite side of the 1 st pad portion with respect to the extension portion in the 1 st direction.

[2] In the semiconductor device according to [1], the interlayer is provided so as to follow an inner surface of the 2 nd recess; an end edge of the interlayer in the 1 st direction close to the 1 st land portion is provided on the opposite side of the 1 st land portion in the 1 st direction with respect to an opening end of the 2 nd recessed portion.

[3] In the semiconductor device according to [2], a thickness of the interlayer in a normal direction of an inner surface of the 2 nd concave portion is smaller than a distance in the 1 st direction from an edge of the 2 nd concave portion in the vicinity of the 1 st pad portion to an edge of the interlayer in the vicinity of the 1 st pad portion.

[3] In the semiconductor device according to [2], the 2 nd pad portion includes a metal layer between an inner surface of the 2 nd recessed portion and the interlayer.

[4] In the semiconductor device according to [2], the 2 nd pad portion includes: a conductive portion including the 2 nd conductor and the interlayer; and a metal layer provided between the conductive portion and an inner surface of the 2 nd recessed portion.

[5] In the semiconductor device according to [4], the metal layer extends closer to the vicinity of the 1 st pad portion than the interlayer.

[6] The semiconductor device according to [4], wherein the metal layer contains tantalum or tantalum nitride.

[7] In the semiconductor device according to [1], the 2 nd conductor is formed over the entire opening surface of the 2 nd recess.

[8] The semiconductor device according to [1], wherein the 2 nd conductor contains copper.

[9] The semiconductor device according to [1], wherein the interlayer is formed of a material having conductivity and having an etching rate higher than that of the 2 nd conductor.

[10] The semiconductor device according to [1], wherein the interlayer contains titanium.

[11] The semiconductor device according to [1], wherein the 1 st conductor has a main portion extending in the 1 st direction in the 1 st recess, and an extension portion extending in the 2 nd direction from an end portion of the main portion close to the 2 nd pad portion; the 1 st land portion has an interlayer provided on the opposite side of the 1 st pad portion from the 1 st direction with respect to the extension portion of the 1 st conductor.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and do not limit the scope of the invention. These embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.