阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 薛琇文 吴采伶 曾雅晴 陈启平 杨能杰 于 2020-09-25 设计创作，主要内容包括：此处公开半导体装置与其制造方法。例示性的半导体装置包括层间介电层,位于基板上；第一导电结构,至少部分地埋置于层间介电层中；介电层,位于层间介电层上并对准层间介电层,其中介电层的上表面高于第一导电结构的上表面；蚀刻停止层,位于介电层与第一导电结构上；以及第二导电结构,位于第一导电结构上,其中第二导电结构的第一部分的第一下表面接触第一导电结构的上表面,且第二导电结构的第二部分的第二下表面接触介电层的上表面。(Semiconductor devices and methods of fabricating the same are disclosed herein. An exemplary semiconductor device includes an interlayer dielectric layer on a substrate; a first conductive structure at least partially embedded in the interlayer dielectric layer; a dielectric layer on and aligned to the interlayer dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the first conductive structure; an etch stop layer on the dielectric layer and the first conductive structure; and a second conductive structure located on the first conductive structure, wherein a first lower surface of a first portion of the second conductive structure contacts an upper surface of the first conductive structure, and a second lower surface of a second portion of the second conductive structure contacts an upper surface of the dielectric layer.)

1. A semiconductor device, comprising:

an interlayer dielectric layer on a substrate;

a first conductive structure at least partially embedded in the interlayer dielectric layer;

a dielectric layer on and aligned to the interlayer dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the first conductive structure;

an etch stop layer on the dielectric layer and the first conductive structure; and

a second conductive structure on the first conductive structure, wherein a first lower surface of a first portion of the second conductive structure contacts the upper surface of the first conductive structure and a second lower surface of a second portion of the second conductive structure contacts the upper surface of the dielectric layer.

Technical Field

Embodiments of the present invention generally relate to semiconductor devices and methods of fabricating the same, and more particularly, to forming conductive structures (e.g., metal lines and vias) in a self-aligned scheme during integrated circuit fabrication.

Background

The electronics industry continues to grow in demand for smaller and faster electronic devices that can simultaneously support larger and more complex functions. These goals are achieved by reducing the size of semiconductor integrated circuits (e.g., minimum feature size), which in turn improves throughput and reduces associated costs.

However, the significant reduction in the size of the integrated circuit makes the semiconductor manufacturing process more complicated and causes problems in the semiconductor device. For example, as the size of integrated circuits, such as pitch and critical dimension, is greatly reduced, it is difficult to control the distance between conductive structures, especially the distance between conductive structures of different layers. For example, due to the shrinking space size, via-to-line breakdown (tiger's teeth) may occur during the back-end process of manufacturing integrated circuits. The tiger-tooth problem affects device reliability, such as reducing time-dependent dielectric breakdown and/or increasing parasitic capacitance of the semiconductor device. There is therefore a need to improve the problems in these areas.

Disclosure of Invention

The semiconductor device provided by the embodiment of the invention comprises an interlayer dielectric layer, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the interlayer dielectric layer is positioned on a substrate; a first conductive structure at least partially embedded in the interlayer dielectric layer; a dielectric layer on and aligned to the interlayer dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the first conductive structure; an etch stop layer on the dielectric layer and the first conductive structure; and a second conductive structure located on the first conductive structure, wherein a first lower surface of a first portion of the second conductive structure contacts an upper surface of the first conductive structure, and a second lower surface of a second portion of the second conductive structure contacts an upper surface of the dielectric layer.

The semiconductor device provided by the embodiment of the invention comprises an interlayer dielectric layer, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the interlayer dielectric layer is positioned on a substrate; the first conductive structure is embedded in the interlayer dielectric layer, wherein the upper surface of the first conductive structure is lower than the upper surface of the interlayer dielectric layer; a dielectric layer formed on the interlayer dielectric layer and aligned with the interlayer dielectric layer; and an etch stop layer on the dielectric layer and the first conductive structure, wherein a first portion of the etch stop layer contacts a sidewall surface of the dielectric layer and extends from an upper surface of the dielectric layer to an upper surface of the first conductive structure.

A method for forming a semiconductor device according to an embodiment of the present invention includes: forming a first conductive structure in an interlayer dielectric layer on a substrate; selectively depositing a cap layer on the first conductive structure and aligning the cap layer with the first conductive structure; selectively coating a barrier layer on the cover layer and aligning the cover layer; depositing a dielectric layer on the interlayer dielectric layer and aligning the interlayer dielectric layer, wherein the barrier layer is formed to prevent the dielectric layer from being deposited thereon; removing the barrier layer to expose the cap layer; and depositing an etch stop layer on the dielectric layer and the cap layer.

Drawings

Fig. 1 is a flow chart of a method of forming a semiconductor device in some embodiments of the invention.

Fig. 2-8 are cross-sectional views of a semiconductor device at an intermediate stage of the method of fig. 1 in some embodiments of the invention.

Fig. 9-16 are cross-sectional views of a semiconductor device at an intermediate stage of the method of fig. 1 in some embodiments of the invention.

Fig. 17A and 17B are cross-sectional views of a region a of fig. 8 and a region B of fig. 16, respectively, in accordance with some other embodiments of the present invention.

Wherein the reference numerals are as follows:

a, B: region(s)

D1, D2: distance between two adjacent plates

T1, T2, T3, T4: thickness of

T5: amount of dishing

T6: height

W1, W1', W2, W2': width of

100: method of producing a composite material

102,104,106,108,110,112,114,116,118,120: step (ii) of

200: device for measuring the position of a moving object

202: substrate

204: structure of the product

206: a first etch stop layer

208: first interlayer dielectric layer

210,210A, 210B: first conductive structure

212: barrier layer

214: cover layer

216: barrier layer

218: dielectric layer

220: a second etch stop layer

220-A: first etch stop layer

220-B: second etching stop layer film

220-C: third etch stop layer

220-1,226-1,226' -1: the first part

Second portion of 220-2, 226' -2

220-3: third part

222: second interlayer dielectric layer

223: metal line trench

224: through-hole trench

226,226': through hole

228: metal circuit

230: barrier layer

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact.

Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence. In addition, a structure of an embodiment of the invention may be formed on, connected to, and/or coupled to another structure, may be in direct contact with the other structure, or may form additional structures between the structure and the other structure. Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relative relationship of one element to another in the figures. The spatially relative terms may be extended to other elements used in other orientations than the orientation illustrated. Further, when a value or range of values is described as "about", "approximately", or the like, it includes +/-10% of the stated value, unless otherwise specified. For example, the term "about 5 nm" includes a size range between 4.5nm to 5.5 nm.

Embodiments of the present invention generally relate to semiconductor devices and methods of fabricating the same, and more particularly, to forming conductive structures (e.g., metal lines and vias) in a self-aligned scheme during integrated circuit fabrication.

As the size of integrated circuits is greatly reduced, the method of fabricating semiconductor devices has a problem of overlay (mask shift). When forming interconnect layers, it is very difficult to control the distance between conductive structures of different layers (such as the distance between a metal line and a via) because of the small critical dimension and the selectivity challenge between adjacent materials. Via-to-line breakdown may occur between adjacent conductive structures, causing manufacturing defects and/or leakage currents.

The embodiment of the invention introduces a self-alignment scheme for forming the conductive structure, can relieve the breakdown problem from a through hole to a circuit, and can achieve higher pattern density. In embodiments of the present invention, a dielectric self-aligned scheme layer comprises a metal oxide or metal nitride material that may be deposited on an underlying dielectric layer (e.g., an interlevel dielectric layer) without contacting an underlying conductive structure (e.g., a metal line). The dielectric self-aligned scheme layer then prevents the upper conductive structure from collapsing into the lower dielectric layer during the formation of the upper conductive structure (e.g., via). In summary, the overlying conductive structure may comprise a first portion that is landed on the underlying conductive structure and a second portion that is landed on the dielectric self-aligned scheme layer. The distance between the adjacent lower layer conductive structure and the upper layer conductive structure can be increased. In some embodiments, the underlying conductive structures may be further recessed to further increase the distance between adjacent underlying and overlying conductive structures. Therefore, the breakdown problem from the through hole to the circuit can be relieved, the parasitic capacitance can be reduced, and the efficiency of the semiconductor device can be improved. These advantages are, of course, merely examples and no particular advantage is necessarily required of any particular embodiment.

Fig. 1 is a flow chart of a method 100 of forming a semiconductor device 200 in some embodiments of the invention. The method 100 is exemplary only, and is not intended to limit embodiments of the invention to those places where no claim is actually made. Additional steps may be performed before, during, and after the method 100, and additional embodiments of the method may replace, omit, or swap some of the steps described. The method 100 will be described below with reference to other figures, which show various cross-sectional views of the device 200 at intermediate steps of the method 100. Specifically, fig. 2-8 show cross-sectional views of the device 200 according to some embodiments of the present invention, and fig. 9-16 show cross-sectional views of the device 200 during fabrication steps according to some embodiments of the present invention.

The device 200 may be an intermediate device fabricated when processing an integrated circuit or portion thereof, which may include static random access memory and/or other logic circuitry, passive components (e.g., resistors, capacitors, or inductors), and active components (e.g., p-type field effect transistors, n-type field effect transistors, fin-type field effect transistors, wrap-around gate transistors, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells). The device 200 may be part of a core region (typically considered a logic region), a memory region (e.g., an sram region), an analog region, a peripheral region (typically considered an input/output region), a dummy region, other suitable regions, or a combination thereof, of an integrated circuit. Embodiments of the invention are not limited to any particular number of devices or device regions or any particular device arrangement. For example, although the device 200 is illustrated as a three-dimensional field effect transistor device (e.g., a finfet), embodiments of the present invention may also be used to fabricate planar field effect transistor devices. Fig. 2 to 16, 17A, and 17B have been simplified to clearly understand the inventive concept of the embodiments of the present invention. Additional structures may be added to the device 200, and other embodiments of the device 200 may replace, adjust, or omit some of the structures described below.

As shown in step 102 of the method 100 of fig. 1 and 2, an initial device 200 is provided. In the embodiment illustrated in fig. 2, the device 200 includes a substrate 202. In the illustrated embodiment, the substrate 202 is a silicon-containing base substrate. In other or additional embodiments, the base substrate comprises another semiconductor element (e.g., germanium), a semiconductor compound (e.g., silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and/or cadmium telluride), other group III-V materials, other group II-VI materials, or combinations thereof. In other embodiments, the substrate 202 is a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a silicon germanium-on-insulator substrate, or a germanium-on-insulator substrate. The semiconductor-on-insulator substrate may be fabricated by discrete implantation of oxygen, wafer bonding, and/or other suitable methods. The substrate 202 may include various doped regions. In some examples, the substrate 202 may include a doped n-type dopant such as phosphorus (e.g., phosphorus)³¹P), arsenic, other n-type dopants, or combinations thereof (e.g., n-type wells). In such embodiments, the substrate 202 may include a doped p-type dopant such as boron (e.g., boron)¹¹B or boron difluoride), indium, other p-type dopants, or a combination thereof (e.g., a p-type well). In some embodiments, the substrate 202 includes a doped region of a combination of p-type and n-type dopants. For example, various doped regions may be formed directly on and/or in the substrate 202 to provide a p-well structure, an n-well structure, a twin-well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and/or other suitable doping processes may be performed to form the various doped regions.

The apparatus 200 also includes a structure 204 on the substrate 202. The structure 204 is part of a multi-level interconnect structure configured to connect various structures of the device 200 to form functional circuitry. In some embodiments, the structure 204 may be a portion of an interlayer dielectric layer, which may include a dielectric material such as silicon oxide, silicon oxynitride, an oxide of tetraethoxysilane, phosphosilicate glass, borophosphosilicate glass, a low dielectric constant (less than 3.9) dielectric material, or a combination thereof. In some other embodiments, the structure 204 may be part of a conductive structure such as an electrode of a transistor, such as a source, a drain, or a gate. The source or drain may comprise n-type doped silicon for n-type field effect transistors, p-type doped silicon germanium for p-type field effect transistors, or other suitable materials. The source or drain may also comprise a silicide such as nickel silicide, titanium silicide, cobalt silicide, or other suitable silicide or germanosilicide. The gate may comprise aluminum, tungsten, cobalt, and/or other suitable materials. In some other embodiments, the structure 204 may be a portion of a conductive structure such as a contact structure (source contact, drain contact, or gate contact), and may comprise cobalt, tungsten, ruthenium, rhodium, iridium, molybdenum, other metals, metal nitrides (such as titanium nitride or tantalum nitride), or combinations thereof. In some embodiments, the structure 204 may be a portion of a conductive structure such as an interconnect structure (e.g., a metal line or a metal plug), and may include copper, cobalt, tungsten, ruthenium, rhodium, iridium, molybdenum, other metals, metal nitrides (e.g., titanium nitride or tantalum nitride), or combinations thereof.

The apparatus 200 also includes a first etch stop layer 206 over the structure 204. In some embodiments, the first etch stop layer 206 comprises a dielectric material, such as a silicon, oxygen, and/or nitrogen containing material. For example, the first etch stop layer 206 may comprise aluminum oxide, aluminum oxynitride, silicon carbide, silicon oxide, silicon oxycarbide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, other dielectric materials, or combinations thereof. The first etch stop layer 206 may be formed by a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable methods, or a combination thereof. In some embodiments, the first etch stop layer 206 may be optionally formed or omitted.

The device 200 also includes a first interlayer dielectric layer 208 formed on the substrate 202. First interlayer dielectric layer 208 include dielectric materials such as silicon oxide, silicon oxynitride, an oxide of tetraethoxysilane, phosphosilicate glass, borophosphosilicate glass, low dielectric constant (e.g., less than 3.9) dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of low dielectric constant dielectric materials include fluorine-doped silicate glass, carbon-doped silicon oxide, Black(Applied Materials, Santa Clara, Calif.), xerogels, aerogels, parylene, benzocyclobutene, SiLK (Dow Chemical, Midland, Michigan), polyimides, other low dielectric constant dielectric Materials, or combinations thereof. The first interlayer dielectric layer 208 may comprise a multi-layer structure of multiple dielectric materials, and may be formed by a deposition process such as chemical vapor deposition (e.g., plasma-assisted chemical vapor deposition or flowable chemical vapor deposition), spin-on-glass, other suitable methods, or a combination thereof. After the first interlayer dielectric layer 208 is deposited, a chemical mechanical polishing process and/or other planarization processes may be performed to planarize the upper surface of the device 200.

The device 200 also includes first conductive structures 210A and 210B (both referred to as first conductive structures 210). The first conductive structure 210 may also be considered a lower layer conductive structure, which may be a conductive interconnect structure such as a contact, via, or metal line, such as a conductive link disposed between semiconductor components of the device 200. In the illustrated embodiment, the first conductive structure 210 is a metal line. In some embodiments, the metal lines, such as the first conductive structure 210, comprise a conductive material, such as tantalum, tantalum nitride, titanium nitride, copper, cobalt, ruthenium, molybdenum, tungsten, other conductive materials, or combinations thereof. In some embodiments, the metal lines, such as the first conductive structure 210, are formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, plating, or other deposition processes. In some embodiments, the method of forming the metal lines, such as the first conductive structure 210, is a single damascene process or a dual damascene process. For example, a first dual damascene process first deposits a masking layer of a negative pattern (e.g., a pattern that is the inverse of the pattern of metal lines, such as the first conductive structures 210) on the first interlayer dielectric layer 208. The first interlayer dielectric layer 208 is then patterned (e.g., etched) along the mask layer to form metal line trenches therein. After the mask layer is removed, a barrier layer 212 (comprising tantalum, tantalum nitride, titanium nitride, other suitable materials, or combinations thereof) may be deposited on the patterned first interlayer dielectric layer 208 and in the metal line trenches. The barrier layer 212 may provide a diffusion barrier property that prevents diffusion of conductive materials (e.g., copper) of metal lines, such as the first conductive structure 210, into the first interlayer dielectric layer 208. A seed layer (not shown, comprising a conductive material for a metal line) may then be deposited over the barrier layer 212. Conductive material for vias 226 and metal lines 228 may then be formed on the seed layer, which may be formed by electrochemical plating. The device 200 may be subjected to a planarization process, such as chemical mechanical polishing, to remove excess conductive material and expose the upper surface of the first interlayer dielectric layer 208. The remaining conductive material may form metal lines, such as the first conductive structures 210 (including metal lines, such as the first conductive structures 210A and 210B). As shown in fig. 2, the top surface of the device 200 exposes metal lines such as conductive structures 210 and barrier layer 212. In the illustrated embodiment, the length directions of the metal lines, such as the first conductive structures 210A and 210B, extend in parallel along the y-direction.

In step 106 of fig. 1 and 3, a cap layer 214 is formed on a metal line, such as the first conductive structure 210. As shown in FIG. 3, a cap layer 214 is formed on and aligned with respective metal lines, such as the first conductive structures 210A and 210B and the barrier layer 212. In other words, the cap layer 214 is formed on the conductive material (e.g., metal lines such as the first conductive structure 210 and the barrier layer 212) on the upper surface of the device 200, but not on the dielectric upper surface of the first ILD 208. In some embodiments, the cap layer 214 comprises a conductive material such as cobalt. The cobalt cap layer 214 protects metal lines, such as the first conductive structure 210 (e.g., containing copper), from oxidation and may increase the reliability of copper metal lines, such as the first conductive structure 210. In some embodiments, the cap layer 214 is formed by selective chemical vapor deposition, other selective metal cap processes, or a combination thereof. In some embodiments, the thickness T1 of the cap layer 214 in the z-direction is about 2.5nm to about 3.5 nm.

At step 108, shown in fig. 1 and 4, a barrier layer 216 is formed on the cap layer 214. As shown in fig. 4, a barrier layer 216 is coated on the cap layer 214 and aligned to the cap layer 214. In other words, the barrier layer 216 does not cover the upper surface of the first interlayer dielectric layer 208. In some embodiments, barrier layer 216 comprises a self-assembled monolayer material that includes a hydrophobic head group and a hydrophobic tail group. For example, the barrier layer 216 may include a chemical species that includes a phosphate group or a high nitrogen group. The barrier layer 216 may be an organic layer, a self-crosslinking layer, a self-adhesive layer, other suitable layer, or a combination thereof. In some embodiments, the method of coating the self-assembled monolayer of the barrier layer 216 on the cap layer 214 may be a chemical adsorption process, such that only the metal surface of the cap layer 214 adsorbs the chemical species of the barrier layer 216, while the dielectric material of the first interlayer dielectric layer 208 does not adsorb the chemical species of the barrier layer 216 (due to the difference in polarity). As shown in fig. 4, barrier layer 216 has a thickness T2 in the z-direction. The thickness T2 may be adjusted according to a distance D1 or D2 (see fig. 8, 9, and 17) that needs to be increased between a subsequently formed upper conductive structure (e.g., via 226) and an adjacent lower conductive structure (e.g., a metal line such as the first conductive structure 210B). In some embodiments, the thickness T2 is about 1.5nm to about 4 nm.

In step 110 of fig. 1 and 5, a dielectric layer 218 is formed on the first interlayer dielectric layer 208. The upper conductive structures (e.g., vias 226) may be formed as a self-aligned solution layer. Self-aligned scheme layers, such as dielectric layer 218, prevent the tiger's teeth portion of the upper conductive structure from collapsing into the first interlayer dielectric layer 208, thereby increasing the distance between the upper conductive structure (via) and the adjacent lower conductive structure (metal line, such as first conductive structure 210B) and alleviating the leakage current problem therebetween. As shown in fig. 5, a self-aligned scheme layer, such as dielectric layer 218, is formed along the sidewalls of cap layer 214 and barrier layer 216. In other words, the self-alignment scheme layer, such as the dielectric layer 218, is formed on the first interlayer dielectric layer 208 and aligned with the first interlayer dielectric layer 208, because the barrier layer 216 formed on the metal line, such as the first conductive structure 210, and aligned with the metal line, such as the first conductive structure 210, may block the self-alignment scheme layer, such as the dielectric layer 218. As shown in fig. 5, the sidewall surfaces of the self-aligned scheme layer, such as dielectric layer 218, contact the sidewall surfaces of cap layer 214 and barrier layer 216. The etch rate of the material of the self-aligned scheme layer, such as the dielectric layer 218, is different from the etch rate of the second etch stop layer 220 and the second interlayer dielectric layer 222 (see fig. 8 and 9) formed later. Thus, self-aligned scheme layers, such as dielectric layer 218, may remain substantially unchanged due to the different etch selectivity when forming via trenches. In some embodiments, a self-aligned scheme layer, such as dielectric layer 218, includes a metal oxide or metal nitride material, such as aluminum oxide, aluminum nitride, but aluminum oxide, other suitable dielectric materials, or combinations thereof. In some embodiments, the self-aligned scheme layer, such as dielectric layer 218, is formed by a selective atomic layer deposition process and is thus formed only on the top surface of the first interlayer dielectric layer 208. As described above, the first interlayer dielectric layer 208 comprises a low-k dielectric material (e.g., silicon oxide), and the barrier layer 216 comprises an organic compound. The material of the self-aligned scheme layer, such as the dielectric layer 218 (e.g., aluminum oxide, aluminum nitride, and/or aluminum oxynitride) bonds only to the low-k dielectric material of the first interlayer dielectric layer 208 and not to the self-aligned monolayer of the organic compound of the barrier layer 216 because of the different chemical affinity. As shown in FIG. 5, the thickness T3 in the z-direction of the self-aligned solution layer, such as dielectric layer 218, is greater than the thickness T1 in the z-direction of cap layer 214. Similar to the barrier layer 216, the thickness T3 of the self-aligned scheme layer, such as the dielectric layer 218, may be adjusted according to the increased distance D1 or D2 (see fig. 8 or fig. 16) between the subsequently formed upper conductive structure, such as the via 226, and the adjacent lower conductive structure, such as the metal line, such as the first conductive structure 210B. In some embodiments, the thickness T3 is about 3nm to about 5 nm.

At step 112 of fig. 1 and 6, the barrier layer 216 is removed to expose the cap layer 214 on the top surface of the device 200. In some embodiments, the removal process of barrier layer 216 is a hydrogen process. For example, a reactive gas comprising hydrogen gas (at a pressure of about 1torr to about 3torr) may be applied to the upper surface of device 200 to react the organic material of barrier layer 216 with the hydrogen gas to remove barrier layer 216. In some other embodiments, the method of removing the barrier layer 216 is a nitrogen treatment (such as nitrogen or ammonia) and the treatment temperature is about 250 ℃ to about 400 ℃. As shown in fig. 6, after removing the barrier layer 216, the sidewall surface of the self-aligned scheme layer, such as the dielectric layer 218, contacts the sidewall surface of the cap layer 214 and extends above the sidewall surface of the cap layer 214.

In step 114 of fig. 1 and 7, a second etch stop layer 220 is deposited on the device 200, particularly on the self-aligned scheme layers such as the dielectric layer 218 and the cap layer 214. As shown in FIG. 7, the second etch stop layer 220 extends from the upper surface of the self-aligned solution layer, such as the dielectric layer 218, to the upper surface of the cap layer 214 due to the difference between the thickness of the self-aligned solution layer, such as the dielectric layer 218, and the thickness of the cap layer 214 (the thickness T3 of the self-aligned solution layer, such as the dielectric layer 218, is greater than the thickness T1 of the cap layer 214). In the embodiment, a first portion 220-1 of the second etch stop layer 220 contacts a portion of the sidewall surface of a self-aligned scheme layer, such as dielectric layer 218. A second portion 220-2 of the second etch stop layer 220 covers the upper surface of the self-aligned scheme layer, such as the dielectric layer 218, and the upper surface of the cap layer 214. The second etch stop layer 220 comprises a dielectric material having an etch rate that is different from the etch rate of the dielectric material of the self-aligned scheme layer, such as the dielectric layer 218. In some embodiments, the second etch stop layer 220 comprises a dielectric material, such as a silicon, oxygen, and/or nitrogen containing material. For example, the second etch stop layer 220 may comprise silicon carbide, silicon oxide, silicon oxycarbide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, other dielectric materials, or combinations thereof. The second etch stop layer 220 may be formed by a deposition process, such as atomic layer deposition, other suitable methods, or a combination thereof. The thickness T4 of the second etch stop layer 220 in the z-direction may be adjusted due to the resistive and/or capacitive performance requirements of the device 200, as well as to alleviate the hillock problem. In some embodiments, the thickness T4 of the second etch stop layer 220 in the z-direction is about 1nm to about 3 nm.

As shown in steps 116 and 118 of fig. 1 and 8, more conductive structures (upper conductive structures, such as via 226 and metal line 228) are formed on one of the first conductive structures 210 (lower conductive structure). The upper conductive structure may be formed by a single damascene process, a dual damascene process, other suitable processes, or a combination thereof. For example, step 116 in the dual damascene process may form a second interlayer dielectric layer 222 on the second etch stop layer 220. The material of the second interlayer dielectric layer 222 is different from that of a self-aligned scheme layer, such as the dielectric layer 218, so as to have different etch rates in subsequent processes for forming the metal line trench 223 and the via trench 224. The method of forming the second interlayer dielectric layer 222 is similar to the method of forming the first interlayer dielectric layer 208.

In step 118 of fig. 8, metal line trenches 223 and via trenches 224 are patterned in the second ild layer 222. The metal line trench 223 and the via trench 224 form an I-shape in the X-Z plane. The metal line trench 223 and the via trench 224 may be formed by an etching process (e.g., dry etching, wet etching, or a combination thereof) through one or more patterned hard masks. The width and depth of the trench depend on the design requirements of the device 200. Due to the small size of the integrated circuit and process limitations, an offset may occur in forming the metal line trench 223 and/or the via trench 224. As shown in fig. 8, the via trench 224 includes a main portion (left side of dashed line) that lands on a metal line, such as the first conductive structure 210A, and an offset portion (right side of dashed line) that lands on a self-aligned scheme layer, such as the dielectric layer 218.

Barrier layer 230 may then be deposited in metal line trench 223 and via trench 224, and the material of barrier layer 230 may comprise tantalum, tantalum nitride, titanium nitride, other suitable materials, or combinations thereof. A seed layer (shown as a conductive material that may include vias and/or metal lines) may then be deposited over the barrier layer 230. The conductive material of vias 226 and metal lines 228 may then be formed on the seed layer in metal line trenches 223 and via trenches 224, which may be formed by electrochemical plating. The conductive material may comprise tantalum, titanium, aluminum, copper, cobalt, tungsten, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. The device 200 may be subjected to a planarization process, such as chemical mechanical polishing, to remove excess conductive material and expose the top surface of the second ild layer 222. The conductive material in the via trenches 224 forms vias 226, while the conductive material remaining in the metal line trenches 223 may form metal lines 228. As shown in fig. 8, the via 226 includes a first portion 226-1 that lands on a metal line, such as the first conductive structure 210A, and a second portion 226-2 that lands on a self-aligned scheme layer, such as the dielectric layer 218. In some embodiments, the offset ratio of the width W1 of the second portion 226-2 to the width W2 of the via 226 (W1/W2) is about 15% to about 30%. Here, the width W1 and the width W2 are the average width of the second portion 226-2 in the X direction and the average width of the through hole 226 in the X direction, respectively.

As described above, due to the small critical dimensions of the device 200, it is difficult to ensure that the via trenches are perfectly formed on the metal lines, such as the first conductive structure 210A, and overlay shift is often a problem when forming the via trenches. The via trench may include a main portion and an offset portion. In prior semiconductor structures that did not form self-aligned scheme layers such as dielectric layer 218, due to the selectivity challenges of the interlevel dielectric layer and the etch stop layer, the materials of the interlevel dielectric layer and the etch stop layer may be removed together when forming the via trench. The offset portion of the via trench may break through the second etch stop layer and insert the first interlayer dielectric layer. The subsequently formed via thus includes two portions, such as a first portion on the underlying metal line and a second portion formed outside the first portion and interposed by the first interlayer dielectric layer. The second portion of the via may be considered a tiger's tooth portion that reduces the distance between the via and the adjacent underlying metal wire land. In some critical situations, the tiger teeth of the upper conductive structure may form a breakdown path and induce leakage current to the adjacent lower conductive structure.

However, in the present embodiment, a self-aligned scheme layer, such as dielectric layer 218, is formed between the first interlayer dielectric layer 208 and the second etch stop layer 220. Due to the different etch selectivity between self-aligned scheme layers, such as the dielectric layer 218 and the second etch stop layer 220, the offset portion of the via trench terminates at the dielectric layer 218 of the self-aligned scheme layer. Thus, as shown in FIG. 8, a via 226 of an embodiment of the present invention includes two portions, such as a first portion 226-1 on a metal line, such as first conductive structure 210A, and a second portion 226-2 on a self-aligned scheme layer, such as dielectric layer 218. In other words, the dielectric layer 218 of the self-aligned solution layer may prevent the via 226 from breaking down into the first interlayer dielectric layer 208. The distance D1 between the via 226 (upper conductive structure) and an adjacent metal line, such as the first conductive structure 210B (adjacent lower conductive structure), is ensured. Thus, breakdown path and/or leakage current problems may be mitigated and the reliability of the device 200 increased. The second conductive structure fabricated in the embodiments of the present invention can be regarded as a self-aligned scheme.

Additional processing may be performed to complete the fabrication of the device 200, as shown in step 120 of FIG. 1. For example, various contacts and/or vias, lines, and multilevel interconnect structures (e.g., interlevel dielectrics or etch stop layers) may be formed on the device 200 according to the design requirements of the device 200.

The method 100 may also include step 104 between step 102 of receiving an initial semiconductor device having a first conductive structure formed in a first interlevel dielectric layer and step 106 of forming a cap layer over the first conductive structure. Fig. 9-16 show cross-sectional views of the device 200 at an intermediate stage of the method 100 including step 104. The same reference numerals in fig. 9-16 may be used to identify the same components and/or structures of fig. 2-8, which comprise the same materials and are formed by the same fabrication process as described above. The critical dimensions of the same components and/or structures are also the same as described above, unless otherwise specified below.

As shown in fig. 1 and 9, an apparatus 200 for receiving an initial semiconductor. The initial device 200 of fig. 10 has the same components and/or structure as fig. 2.

In step 104 shown in fig. 1 and 10, the top of the first conductive structures 210 (metal lines, such as the first conductive structures 210A and 210B) is recessed such that the top surfaces of the first conductive structures 210A and 210B are lower than the top surface of the first interlayer dielectric layer 208. In some embodiments, the top of the first conductive structure 210 is removed with a wet etch. Since the materials of the barrier layer 212, the first conductive structure 210, and the first interlayer dielectric layer 208 are different, the wet etching process only removes the top of the first conductive structure 210, while the barrier layer 212 and the first interlayer dielectric layer 208 remain substantially unchanged. In some embodiments, the apparatus 200 is immersed in a wet etchant such as dilute hydrofluoric acid, other suitable chemistry, or a combination thereof. Various process conditions such as time and temperature may be adjusted to adjust or quantitatively control the amount of dishing. In some embodiments, the amount of recess T5 of the first conductive structure 210 is about 10% to about 20% of the height T6 of the first conductive structure 210. In some other embodiments, the amount of dishing T5 is about 2nm to about 5 nm.

In step 106 of fig. 1 and 11, a cap layer 214 is deposited on the first conductive structure 210. In some embodiments, the cap layer 214 may be considered as part of the first conductive structure 210. As shown in fig. 11, the top surface of the cap layer 214 is lower than the top surface of the first interlayer dielectric layer 208.

At step 108, shown in fig. 1 and 12, a barrier layer 216 is formed on the conductive cap layer 214 without contacting the dielectric material of the first interlayer dielectric layer 208. As shown in fig. 12, the upper surface of the barrier layer 216 is higher than the upper surface of the first interlayer dielectric layer 208.

At step 110 of fig. 1 and 13, a dielectric self-aligned scheme layer, such as dielectric layer 218, is formed on the first interlayer dielectric layer 208 and spaced apart from the first conductive structure 210 and the barrier layer 212. Similar to the above description, due to the difference in chemical affinity, self-assembly scheme layers such as the dielectric layer 218 do not bond with the barrier layer and are therefore formed only on the first interlayer dielectric layer 208 and aligned with the first interlayer dielectric layer 208.

At step 112 of fig. 1 and 14, the barrier layer 216 is removed to expose the upper surface of the cap layer 214 and the upper surface and at least a portion of the sidewall surface of the barrier layer 212 from the top of the device 200.

In step 114 of fig. 1 and 15, a second etch stop layer 220 is deposited on the device 200. As shown in fig. 15, the second etch stop layer 220 forms a step over the self-aligned scheme layers, such as the dielectric layer 218, the barrier layer 212, and the cap layer 214, due to the thickness difference between the self-aligned scheme layers, such as the dielectric layer 218 and the barrier layer 212, and the thickness difference between the barrier layer 212 and the cap layer 214. The second etch stop layer 220 extends from the top surface of the self-aligned solution layer, such as the interfacial layer 218, along the sidewall surfaces of the self-aligned solution layer, such as the interfacial layer 218, further extends over the top surface of the barrier layer 212 and along portions of the sidewall surfaces of the barrier layer 212, and further extends over the top surface of the cap layer 214. As shown in FIG. 15, the second etch stop layer 220 includes three portions, such as a first portion 220-1 that contacts the sidewall surface of the self-aligned solution layer, such as the dielectric layer 218, a second portion 220-2 that covers the upper surface of the self-aligned solution layer, such as the dielectric layer 218, and the upper surface of the cap layer 214, and a third portion 220-3 that contacts the portion of the sidewall surface of the barrier layer 212.

In steps 116 and 118 of fig. 1 and 16, more conductive structures such as vias 226' and metal lines 228 are formed on the first conductive structure 210A (metal line). The formation process and materials of the vias 226' and the metal lines 228 may be similar to those of the vias 226 and the metal lines 228 shown in fig. 8. In the example of fig. 16, the via 226' includes a first portion 226' -1 overlying a metal line, such as the first conductive structure 210A, and a second portion 226' -2 (e.g., a tiger tooth portion) that lands on a self-aligned scheme layer, such as the dielectric layer 218. In some embodiments, the offset ratio (W1'/W2') is about 15% to about 30%, for example, the ratio of the width W1 'of the second portion 226' -2 and the width W2 'of the through-hole 226'. Here, the width W1 'and the width W2' are an average width of the second portion 226'-2 in the X direction and an average width of the via hole 226' in the X direction, respectively. Due to the recessing process of step 104, the top surface of each of the first conductive structures 210A and 210B (e.g., metal lines) is lower than the bottom surface of the self-aligned scheme layer, such as the dielectric layer 218 (e.g., the top surface of the first interlayer dielectric layer 208). The distance D2 between the tiger's tooth portion, e.g., second portion 226' -2, of the via 226 'in fig. 16 and the adjacent metal line, e.g., first conductive structure 210B, is therefore greater than the distance D1 between the tiger's tooth portion, e.g., second portion 226-2, of the via 226 in fig. 8 and the adjacent metal line, e.g., first conductive structure 210B. The distance D1 and the distance D2 are both larger than the distance between the tiger's teeth part of the through hole and the adjacent lower metal line in the prior semiconductor device. As compared to the embodiments of fig. 16 and 8, the increased distance D2 may further alleviate the breakdown path and/or leakage current problems, further increase the reliability of the semiconductor device, reduce via-to-line parasitic capacitance, and speed up the device 200.

Additional processing may be performed to complete the device 200, as shown in step 120 of FIG. 1.

Fig. 17A and 17B are cross-sectional views of some other embodiments of a device 200. Fig. 17A and 17B refer to the device 200 shown in region a of fig. 8 and region B of fig. 16, respectively. As shown in fig. 17A and 17B, the second etch stop layer 220 includes a multi-layer structure. Taking fig. 17A as an example, the first etch stop layer 220-a of the second etch stop layer 220 has a portion of the sidewall that contacts the self-aligned scheme layer, such as the dielectric layer 218, and forms a step extending from the self-aligned scheme layer, such as the dielectric layer 218, to the upper surface of the cap layer 214. The second etch stop layer 220-B of the second etch stop layer 220 is located on the first etch stop layer 220-a. The first etch stop layer 220-a may be formed by atomic layer deposition and the second etch stop layer 220-B may be formed by chemical vapor deposition and/or physical vapor deposition. During a chemical vapor deposition or physical vapor deposition process, the second etchstop film 220-B may be incorporated on top of the first conductive structure 210A, thereby forming a substantially planar upper surface. The second etch stop layer 220-B may planarize the level difference of the first etch stop layer 220-a. In some embodiments, the second ESL 220 may also comprise further ESLs, such as the third ESL 220-C shown in FIG. 17A, deposited on a previous ESL, and deposited by CVD, PVD, ALD, other suitable processes, or a combination thereof. Similarly, the first etch stop layer 220-a of the second etch stop layer 220 in fig. 17B has a first portion contacting the sidewalls of the self-assembly layer, such as the dielectric layer 218, a second portion contacting the sidewalls of the barrier layer 212, and forms a step extending from the self-aligned layer, such as the dielectric layer 218, to the upper surface of the barrier layer 212 and further to the upper surface of the cap layer 214. The second etch stop layer 220 may also include a second etch stop layer 220-B disposed on the first etch stop layer 220-A. The first etch stop layer 220-A may be formed by atomic layer deposition, and the second etch stop layer 220-B may be formed by chemical vapor deposition and/or physical vapor deposition, such that the second etch stop layer 220-B may planarize the height difference of the first etch stop layer 220-A. In some embodiments, the second etch stop layer 220 may also comprise further etch stop layers, such as the third etch stop layer 220-C shown in fig. 17B deposited on a previous etch stop layer, and the deposition method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable processes, or a combination thereof.

One or more embodiments of the present invention provide many advantages to, but are not limited to, semiconductor devices and processes for forming the same. For example, embodiments of the present invention provide semiconductor devices having conductive interconnect structures formed in a self-aligned manner. In an embodiment of the present invention, a dielectric self-aligned scheme layer is formed between an upper etch stop layer (e.g., second etch stop layer 220) and a lower interlayer dielectric layer (e.g., first interlayer dielectric layer 208). The self-aligned solution layer includes a dielectric material different from the material of the upper etch stop layer and the upper interlayer dielectric layer, so that the self-aligned solution layer can remain substantially unchanged during formation of the upper conductive structure. The self-aligned scheme layer thus prevents the upper conductive structure from collapsing into the underlying interlayer dielectric layer and increases the distance between the upper conductive structure (e.g., via 226) and the adjacent underlying conductive structure (e.g., metal line such as first conductive structure 210B). Thus, breakdown path and/or leakage current problems may be reduced, resulting in a semiconductor device with a preferred reliability. In some embodiments, if the lower conductive structure is recessed to further increase the distance between the upper conductive structure and the adjacent lower conductive structure, the parasitic capacitance can be reduced and the performance of the semiconductor device can be further improved. The fabrication process can be integrated into existing process flows and can be used for various technology generations.

The present invention provides many different embodiments. The semiconductor device includes an interlayer dielectric layer on a substrate; a first conductive structure at least partially embedded in the interlayer dielectric layer; a dielectric layer on and aligned to the interlayer dielectric layer, wherein the upper surface of the dielectric layer is higher than the upper surface of the first conductive structure; an etch stop layer on the dielectric layer and the first conductive structure; and a second conductive structure on the first conductive structure, wherein a first lower surface of a first portion of the second conductive structure contacts an upper surface of the first conductive structure, and a second lower surface of a second portion of the second conductive structure contacts an upper surface of the dielectric layer.

In some embodiments, the semiconductor device further includes a cap layer on and aligned with the first conductive structure. In some embodiments, the thickness of the dielectric layer is greater than the thickness of the cap layer, such that the sidewall surface of the dielectric layer extends above the cap layer. In some embodiments, the etch stop layer includes a portion of the sidewall surface that contacts the dielectric layer, and wherein the etch stop layer extends from the upper surface of the dielectric layer to the upper surface of the cap layer. In some embodiments, a first of the etch stop layers has a portion that contacts the sidewall surface of the dielectric layer and extends from the upper surface of the dielectric layer to the upper surface of the cap layer, and a second of the etch stop layers is over the first etch stop layer.

In some embodiments, the semiconductor device further includes a barrier layer surrounding the first conductive structure and between the first conductive structure and the interlayer dielectric layer. In some embodiments, the dielectric layer is spaced a distance from the first conductive structure.

In some embodiments, an upper surface of the interlayer dielectric layer is higher than an upper surface of the first conductive structure.

Another semiconductor device includes an interlayer dielectric layer on a substrate; the first conductive structure is embedded in the interlayer dielectric layer, wherein the upper surface of the first conductive structure is lower than that of the interlayer dielectric layer; a dielectric layer formed on the interlayer dielectric layer and aligned with the interlayer dielectric layer; and an etch stop layer on the dielectric layer and the first conductive structure, wherein a first portion of the etch stop layer contacts a sidewall surface of the dielectric layer and extends from an upper surface of the dielectric layer to an upper surface of the first conductive structure.

In some embodiments, the semiconductor device further comprises a barrier layer surrounding the first conductive structure and between the first conductive structure and the interlayer dielectric layer, wherein the etch stop layer further comprises a second portion on a sidewall surface of the barrier layer. In some embodiments, the first conductive structure has a top surface lower than the top surface of the barrier layer and lower than the top surface of the dielectric layer. In some embodiments, the first conductive structure includes a metal plug, and a cap layer on and aligned with the metal plug. In some embodiments, the semiconductor device further comprises a second conductive structure, a first portion of the second conductive structure landing on the first conductive structure, and a second portion of the second conductive structure landing on the dielectric layer via the etch stop layer.

An exemplary method of forming a semiconductor device includes: forming a first conductive structure in an interlayer dielectric layer on a substrate; selectively depositing a cap layer on the first conductive structure and aligning the cap layer with the first conductive structure; selectively coating a barrier layer on the cover layer and aligning the cover layer; depositing a dielectric layer on the interlayer dielectric layer and aligning the interlayer dielectric layer, wherein the barrier layer is formed to prevent the dielectric layer from being deposited thereon; removing the barrier layer to expose the cap layer; and depositing an etch stop layer on the dielectric layer and the cap layer.

In some embodiments, the method further comprises: the first conductive structure is recessed prior to forming the cap layer such that an upper surface of the first conductive structure is lower than an upper surface of the interlayer dielectric layer. In some embodiments, the step of selectively depositing a cap layer over and aligning the first conductive structure includes depositing the cap layer with a thickness such that an upper surface of the cap layer is lower than an upper surface of the interlayer dielectric layer.

In some embodiments, the step of selectively coating the barrier layer comprises depositing a self-aligned monolayer comprising nitrogen in a chemisorption process. In some embodiments, the step of depositing the dielectric layer comprises depositing a metal oxide or metal nitride containing dielectric layer by selective atomic layer deposition. In some embodiments, the step of removing the barrier layer comprises removing the barrier layer with a hydrogen treatment. In some embodiments, the step of selectively depositing the cap layer comprises depositing a cobalt-containing layer by chemical vapor deposition.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalents may be substituted and/or modified without departing from the spirit and scope of the present invention.