阅读说明：本技术 晶圆级芯片封装结构及封装方法 (Wafer-level chip packaging structure and packaging method ) 是由 徐罕 陈彦亨 吴政达 林正忠 薛亚媛 于 2019-09-30 设计创作，主要内容包括：本发明提供一种晶圆级封装结构及封装方法,封装方法包括：提供待封装晶圆；制备导电柱；于待封装晶圆中制备凹槽结构；形成封装层,延伸至凹槽结构中；制备引出焊垫；显露形成于凹槽结构中的封装层；自凹槽结构对应的位置进行切割。本发明采用基于凹槽结构切割晶圆的晶圆级封装方法,在扇出型晶圆级封装中,有利于保护芯片,防止晶圆破裂,有利于缩短制程,减小作业周期,提升产品产率,有利于产品成本的降低,采用表贴层还实现了对晶圆级芯片进行有效的六面封装,更好的包装芯片,提高产品的可靠性,采用基于平坦化辅助层及金属连接层制备的引出焊垫进行待封装芯片的电性引出,可以提高引出的电学性能及连接稳定性,提高封装结构的整体性能。(The invention provides a wafer level packaging structure and a packaging method, wherein the packaging method comprises the following steps: providing a wafer to be packaged; preparing a conductive column; preparing a groove structure in a wafer to be packaged; forming a packaging layer extending into the groove structure; preparing a lead-out welding pad; exposing the packaging layer formed in the groove structure; and cutting from the corresponding position of the groove structure. The invention adopts the wafer level packaging method for cutting the wafer based on the groove structure, is beneficial to protecting the chip and preventing the wafer from cracking in fan-out type wafer level packaging, is beneficial to shortening the manufacturing process, reducing the operation period, improving the product yield and reducing the product cost, also realizes effective six-side packaging of the wafer level chip by adopting the surface pasting layer, better packages the chip and improves the reliability of the product, and adopts the lead-out welding pad prepared based on the flattening auxiliary layer and the metal connecting layer to carry out the electrical lead-out of the chip to be packaged, thereby improving the electrical property and the connection stability of the lead-out and improving the overall performance of the packaging structure.)

1. A wafer level chip packaging method is characterized by comprising the following steps:

providing a wafer to be packaged, wherein the wafer to be packaged is provided with a first surface and a second surface which are opposite;

preparing a conductive column on the first surface, wherein the conductive column is electrically connected with the wafer to be packaged;

preparing a groove structure in the wafer to be packaged, wherein the groove structure extends from the first surface to the interior of the wafer to be packaged so as to divide the wafer to be packaged into a plurality of chips to be packaged;

forming an encapsulation layer surrounding the conductive posts and exposing tops of the conductive posts on the first surface, wherein the encapsulation layer extends into the groove structures;

preparing a lead-out welding pad on the packaging layer, wherein the lead-out welding pad is electrically connected with the conductive column;

thinning the second surface of the wafer to be packaged to expose the packaging layer formed in the groove structure;

and cutting the wafer to be packaged from the position corresponding to the groove structure to obtain a packaging structure.

2. The wafer-level chip packaging method as claimed in claim 1, wherein the depth of the groove structure is not more than half of the thickness of the wafer to be packaged.

3. The wafer-level chip packaging method as claimed in claim 1, further comprising the steps of, before forming the groove structure: and forming a supporting film layer on the second surface of the wafer to be packaged.

4. The wafer-level chip packaging method according to claim 1, wherein the step of forming the packaging layer comprises: forming a packaging material layer on the first surface of the wafer to be packaged, wherein the upper surface of the packaging material layer is higher than the upper surfaces of the conductive posts; and thinning the packaging material layer to obtain the packaging layer.

5. The wafer-level chip packaging method according to claim 4, wherein a distance from an upper surface of the packaging material layer to an upper surface of the conductive pillar is greater than 50 μm.

6. The wafer-level chip packaging method according to claim 4, wherein the roughness of the upper surface of the packaging layer obtained after grinding is less than 0.2 μm.

7. The wafer-level chip packaging method according to claim 1, wherein the lead-out pad comprises a planarization auxiliary layer and a metal connection layer on the planarization auxiliary layer, wherein the planarization auxiliary layer is prepared based on a sputtering process, and the metal connection layer is prepared based on an electroplating process.

8. The semiconductor wafer-level chip packaging method according to claim 1, further comprising a step of preparing a redistribution layer on the package layer before forming the lead-out pad, wherein the lead-out pad is electrically connected to the conductive pillar through the redistribution layer, and the step of preparing the redistribution layer comprises: and forming a dielectric layer and a metal laminated structure on the upper surface of the packaging layer, wherein the metal laminated structure is electrically connected with the conductive post, the metal laminated structure is positioned in the dielectric layer, the metal laminated structure comprises a plurality of metal wire layers which are arranged at intervals and metal plugs, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.

9. The wafer-level chip packaging method according to any one of claims 1 to 8, wherein before the wafer to be packaged is cut, the method further comprises the following steps: and forming a surface-mount layer on the second surface of the wafer to be packaged, wherein the surface-mount layer is in contact with both the wafer to be packaged and the packaging layer in the groove structure.

10. A wafer level chip package structure, comprising:

a package wafer having a first surface and a second surface opposite to each other;

the conductive columns are formed on the first surface of the packaging wafer and electrically connected with the packaging wafer;

the groove structure penetrates through the packaging wafer to divide the packaging wafer into a plurality of packaging chips;

the packaging layer is formed on the first surface of the packaging wafer, extends into the groove structure and surrounds the conductive posts and exposes the tops of the conductive posts; and

and the lead-out welding pad is formed on the packaging layer and is electrically connected with the conductive column.

11. The wafer-level chip package structure according to claim 10, wherein the roughness of the upper surface of the encapsulation layer is less than 0.2 μm.

12. The wafer-level chip package structure of claim 10, wherein the lead-out pad comprises a planarization auxiliary layer and a metal connection layer on the planarization auxiliary layer.

13. The wafer level chip package structure of claim 10, wherein a redistribution layer is further formed between the lead-out pad and the package layer, the lead-out pad is electrically connected to the conductive pillar through the redistribution layer, the redistribution layer includes a dielectric layer and a metal stack structure, the metal stack structure is electrically connected to the conductive pillar, the metal stack structure is located in the dielectric layer, the metal stack structure includes a plurality of metal wire layers arranged at intervals and metal plugs, and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

14. The wafer-level chip package structure according to any one of claims 10 to 13, further comprising a surface-mount layer formed on the second surface of the package wafer, the surface-mount layer contacting both the package chip and the package layer in the groove structure.

15. A chip package structure, the package structure comprising:

a packaged chip having opposing first and second surfaces;

the conductive column is formed on the first surface of the packaged chip and is electrically connected with the packaged chip;

the packaging layer is formed on the first surface of the packaging chip and extends to the side face of the wafer to be packaged, and the packaging layer surrounds the conductive posts and exposes the tops of the conductive posts; and

and the lead-out welding pad is formed on the packaging layer and is electrically connected with the conductive column.

16. The chip package structure according to claim 15, wherein a roughness of an upper surface of the encapsulation layer is less than 0.2 microns.

17. The chip package structure according to claim 15, wherein the lead pads comprise a planarization auxiliary layer and a metal connection layer on the planarization auxiliary layer.

18. The chip package structure according to claim 15, wherein a redistribution layer is further formed between the lead-out pad and the package layer, the lead-out pad is electrically connected to the conductive pillar through the redistribution layer, the redistribution layer includes a dielectric layer and a metal stack structure, the metal stack structure is electrically connected to the conductive pillar, the metal stack structure is located in the dielectric layer, the metal stack structure includes a plurality of metal wire layers arranged at intervals and metal plugs, and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

19. The chip package structure according to any one of claims 15 to 18, further comprising a surface mount layer formed on the second surface of the packaged chip, the surface mount layer contacting both the packaged chip and the package layer on the side of the packaged chip.

Technical Field

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a wafer-level chip packaging structure and a packaging method.

Background

With the increasing functionality, performance and integration level of integrated circuits, and the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. Meanwhile, as the feature size of the integrated circuit reaches the nanometer level, the transistor is developed to a higher density and a higher clock frequency, and the package is also developed to a higher density.

Because the fan-out wafer level package (fowlp) technology has the advantages of miniaturization, low cost, high integration, better performance, and higher energy efficiency, the fan-out wafer level package (fowlp) technology has become an important packaging method for high-demand electronic devices such as mobile/wireless networks, and is one of the most promising packaging technologies currently.

However, in the existing fan-out package, it is difficult to realize a simple and effective overall package for the wafer-level package structure, and the wafer is easily broken in the packaging process, so the packaging process is long, the preparation period is long, and the operation efficiency is affected.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a wafer level chip package structure and a packaging method thereof, which are used to solve the problems in the prior art that it is difficult to achieve a simple and effective overall package, and that the wafer is prone to crack and the process cycle is long.

To achieve the above and other related objects, the present invention provides a wafer level chip packaging method, including the steps of:

providing a wafer to be packaged, wherein the wafer to be packaged is provided with a first surface and a second surface which are opposite;

preparing a conductive column on the first surface, wherein the conductive column is electrically connected with the wafer to be packaged;

preparing a groove structure in the wafer to be packaged, wherein the groove structure extends from the first surface to the interior of the wafer to be packaged so as to divide the wafer to be packaged into a plurality of chips to be packaged;

forming an encapsulation layer surrounding the conductive posts and exposing tops of the conductive posts on the first surface, wherein the encapsulation layer extends into the groove structures;

preparing a lead-out welding pad on the packaging layer, wherein the lead-out welding pad is electrically connected with the conductive column;

thinning the second surface of the wafer to be packaged to expose the packaging layer formed in the groove structure;

and cutting the wafer to be packaged from the position corresponding to the groove structure to obtain a packaging structure.

Optionally, the depth of the groove structure is not more than half of the thickness of the wafer to be packaged.

Optionally, before forming the groove structure, the method further includes: and forming a supporting film layer on the second surface of the wafer to be packaged.

Optionally, the step of forming the encapsulation layer includes: forming a packaging material layer on the first surface of the wafer to be packaged, wherein the upper surface of the packaging material layer is higher than the upper surfaces of the conductive posts; and thinning the packaging material layer to obtain the packaging layer.

Optionally, the upper surface of the encapsulation material layer is higher than the upper surface of the conductive pillar by a distance greater than 50 micrometers.

Optionally, the roughness of the upper surface of the encapsulation layer obtained after grinding is less than 0.2 microns.

Optionally, the lead-out pad includes a planarization auxiliary layer and a metal connection layer on the planarization auxiliary layer, wherein the planarization auxiliary layer is prepared based on a sputtering process, and the metal connection layer is prepared based on an electroplating process.

Optionally, before forming the lead-out pad, a step of preparing a redistribution layer on the encapsulation layer is further included, where the lead-out pad is electrically connected to the conductive pillar through the redistribution layer, and the step of preparing the redistribution layer includes: and forming a dielectric layer and a metal laminated structure on the upper surface of the packaging layer, wherein the metal laminated structure is electrically connected with the conductive post, the metal laminated structure is positioned in the dielectric layer, the metal laminated structure comprises a plurality of metal wire layers which are arranged at intervals and metal plugs, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.

Optionally, before the wafer to be packaged is cut, the method further includes: and forming a surface-mount layer on the second surface of the wafer to be packaged, wherein the surface-mount layer is in contact with both the wafer to be packaged and the packaging layer in the groove structure.

The invention also provides a wafer-level chip packaging structure, which is preferably prepared on the basis of the wafer-level chip packaging method, and the packaging structure comprises the following components:

a package wafer having a first surface and a second surface opposite to each other;

the conductive columns are formed on the first surface of the packaging wafer and electrically connected with the packaging wafer;

the groove structure penetrates through the packaging wafer to divide the packaging wafer into a plurality of packaging chips;

the packaging layer is formed on the first surface of the packaging wafer, extends into the groove structure and surrounds the conductive posts and exposes the tops of the conductive posts; and

and the lead-out welding pad is formed on the packaging layer and is electrically connected with the conductive column.

Optionally, the roughness of the upper surface of the encapsulation layer is less than 0.2 microns.

Optionally, the lead pad includes a planarization auxiliary layer and a metal connection layer on the planarization auxiliary layer.

Optionally, a redistribution layer is further formed between the lead-out pad and the package layer, the lead-out pad is electrically connected to the conductive pillar through the redistribution layer, the redistribution layer includes a dielectric layer and a metal stacked structure, the metal stacked structure is electrically connected to the conductive pillar, the metal stacked structure is located in the dielectric layer, the metal stacked structure includes a plurality of metal wire layers arranged at intervals and metal plugs, and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

Optionally, the wafer-level chip package structure further includes a surface-mount layer, the surface-mount layer is formed on the second surface of the package wafer, and the surface-mount layer is in contact with both the package chip and the package layer in the groove structure.

The invention also provides a chip packaging structure, which is preferably prepared based on the wafer-level chip packaging method, and the packaging structure comprises the following components:

a packaged chip having opposing first and second surfaces;

the conductive column is formed on the first surface of the packaged chip and is electrically connected with the packaged chip;

the packaging layer is formed on the first surface of the packaging chip and extends to the side face of the wafer to be packaged, and the packaging layer surrounds the conductive posts and exposes the tops of the conductive posts; and

and the lead-out welding pad is formed on the packaging layer and is electrically connected with the conductive column.

Optionally, the roughness of the upper surface of the encapsulation layer is less than 0.2 microns.

Optionally, the lead pad includes a planarization auxiliary layer and a metal connection layer on the planarization auxiliary layer.

Optionally, a redistribution layer is further formed between the lead-out pad and the package layer, the lead-out pad is electrically connected to the conductive post through the redistribution layer, the redistribution layer includes a dielectric layer and a metal laminated structure, the metal laminated structure is electrically connected to the conductive post, the metal laminated structure is located in the dielectric layer, the metal laminated structure includes a plurality of metal wire layers arranged at intervals and metal plugs, and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

Optionally, the chip package structure further includes a surface mount layer formed on the second surface of the package chip, and the surface mount layer is in contact with the package chip and the package layer on the side surface of the package chip.

As described above, the wafer level chip package structure and the package method of the present invention adopt the wafer level package method of cutting the wafer based on the groove structure, which is beneficial to protecting the chip, preventing the wafer from breaking, shortening the manufacturing process, reducing the operation period, improving the product yield and reducing the product cost in the fan-out type wafer level package.

Drawings

FIG. 1 is a process flow diagram of a wafer level chip packaging method according to the present invention.

FIG. 2 is a schematic diagram of a wafer to be packaged according to the wafer level chip packaging method of the present invention.

Fig. 3 is a schematic structural diagram illustrating the formation of the conductive pillars in the wafer level chip packaging method according to the present invention.

FIG. 4 is a schematic diagram illustrating a structure of a groove structure formed in the wafer level chip packaging method according to the present invention.

FIG. 5 is a schematic view illustrating a structure of a packaging material layer formed in the wafer level chip packaging method according to the present invention.

FIG. 6 is a schematic diagram illustrating a structure of a package layer formed in the wafer level chip packaging method according to the present invention.

FIG. 7 is a schematic diagram illustrating a structure of a lead pad formed in the wafer level chip packaging method according to the present invention.

Fig. 8 is a schematic structural view illustrating the second surface thinning performed in the wafer-level chip packaging method according to the present invention.

FIG. 9 is a schematic diagram illustrating a structure of a surface mount layer formed in the wafer level chip packaging method according to the present invention.

FIG. 10 is a schematic diagram illustrating dicing performed in the wafer level chip packaging method according to the present invention.

Fig. 11 is a schematic structural diagram of a chip package structure obtained after dicing in the wafer-level chip packaging method according to the present invention.

Description of the element reference numerals

100 wafer to be packaged

100a package wafer

100b packaged chip

1001 electrode area

101 conductive column

102 groove structure

103 supporting film layer

104 layer of encapsulating material

105 encapsulation layer

106 lead out pad

106a planarization auxiliary layer

106b metal connection layer

107 surface layer

S1-S7

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1-11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The first embodiment is as follows:

as shown in fig. 1, the present invention provides a wafer level chip packaging method, which includes the following steps:

providing a wafer to be packaged, wherein the wafer to be packaged is provided with a first surface and a second surface which are opposite;

preparing a conductive column on the first surface, wherein the conductive column is electrically connected with the wafer to be packaged;

preparing a groove structure in the wafer to be packaged, wherein the groove structure extends from the first surface to the interior of the wafer to be packaged so as to divide the wafer to be packaged into a plurality of chips to be packaged;

forming an encapsulation layer surrounding the conductive posts and exposing tops of the conductive posts on the first surface, wherein the encapsulation layer extends into the groove structures;

preparing a lead-out welding pad on the packaging layer, wherein the lead-out welding pad is electrically connected with the conductive column;

thinning the second surface of the wafer to be packaged to expose the packaging layer formed in the groove structure;

and cutting the wafer to be packaged from the position corresponding to the groove structure to obtain a packaging structure.

The method for packaging wafer level chips according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in S1 in fig. 1 and fig. 2, a wafer 100 to be packaged is provided, where the wafer 100 to be packaged has a first surface and a second surface opposite to each other.

Specifically, the wafer 100 to be packaged has a first surface and a second surface opposite to each other, where the first surface may be a front surface of a chip, and the second surface may be a back surface of the wafer 100 to be packaged, in an example, the wafer 100 to be packaged further has an electrode region 1001, and the electrode region 1001 is disposed at the first surface to implement electrical connection of the chip to be packaged. In this example, the wafer 100 to be packaged is a wafer-level chip, and a plurality of chips may be formed on the wafer for packaging. The wafer 100 to be packaged may be an Incoming wafer type from CTM (Incoming wafer) directly from a merchant.

As shown in S2 in fig. 1 and fig. 3, a conductive pillar 101 is prepared on the first surface, and the conductive pillar 101 is electrically connected to the wafer 100 to be packaged.

Specifically, a conductive pillar 101, such as a conductive copper pillar, is further prepared on the wafer 100 to be packaged, in an example, the conductive pillar 101 is prepared on the electrode region 1001 to realize the electrical connection of the wafer 100 to be packaged, and a preparation process of the conductive pillar 101 may adopt a preparation process of a conductive connection pillar, such as a copper pillar preparation process, which is commonly used in the art. In one example, the process for preparing the copper pillar may include: firstly, pre-cleaning a wafer for receiving materials, then sputtering a titanium layer on the upper surface of the wafer for receiving materials, sputtering a copper layer on the titanium layer, then depositing a photoresist layer on the copper layer and patterning the photoresist layer to expose an area where a copper column needs to be formed, further electroplating copper in a patterned photoresist opening through an electroplating process, then removing the surrounding photoresist layer to expose the sputtered copper layer, and then etching and removing the initially sputtered copper layer and the initially sputtered titanium layer to finally form the conductive column 101 comprising Ti/Cu/Cu.

As shown in S3 in fig. 1 and fig. 4, a groove structure 102 is prepared in the wafer 100 to be packaged, and the groove structure 102 extends from the first surface to the inside of the wafer 100 to be packaged, so as to divide the wafer 100 to be packaged into a plurality of chips to be packaged.

As an example, the depth of the groove structure 102 is not more than half of the thickness of the wafer 100 to be packaged.

As an example, before forming the groove structure 102, the method further includes the steps of: a supporting film 103 is formed on the second surface of the wafer 100 to be packaged.

Specifically, in this step, the groove structures 102 are prepared on the wafer 100 to be packaged, the groove structures 102 divide the wafer 100 to be packaged into a plurality of chips to be independently packaged, the number of the groove structures 102 is set according to actual requirements, the groove structures 102 may be formed by mechanical cutting or laser cutting, and in this embodiment, the groove structures are preferably formed by mechanical cutting, so as to facilitate accurate control of the depth of the groove structures. In an example, the position of the groove structure 102 is correspondingly formed between the wafers 100 to be packaged corresponding to the two conductive pillars 101, preferably at the center of the adjacent conductive pillars 101, in an alternative example, the depth of the groove structure 102 is not more than one half of the thickness of the wafer 100 to be packaged, where the depth refers to the distance between the surface of the wafer 100 to be packaged and the bottom of the groove structure 102, so as to facilitate preventing the wafer 100 to be packaged from being chipped, optionally, the depth of the groove structure 102 is 1/2 of the wafer 100 to be packaged, and the depth of the groove structure 102 is greater than the depth of the electrode region 1001 of the wafer 100 to be packaged.

Specifically, in an example, before forming the groove structure 102, a supporting film 103 is further formed on the second surface of the wafer 100 to be packaged, and the supporting film may be an adhesive film as a carrier, so that the wafer 100 to be packaged may be protected as a dicing carrier, and in an example, the supporting film may be removed after forming the groove structure 102 and before performing the next packaging.

As shown in S4 of fig. 1 and fig. 5-6, the encapsulation layer 105 surrounding the conductive pillars 101 and exposing the tops of the conductive pillars 101 is formed on the first surface, and the encapsulation layer 105 extends into the groove structure 102.

As an example, the step of forming the encapsulation layer 105 includes: forming a packaging material layer 104 on the first surface of the wafer 100 to be packaged, wherein an upper surface of the packaging material layer 104 is higher than an upper surface of the conductive pillar 101; the packaging material layer 104 is thinned to obtain the packaging layer 105.

As an example, the upper surface of the encapsulation material layer 104 is higher than the upper surface of the conductive pillar 101 by a distance greater than 50 micrometers.

As an example, the roughness of the upper surface of the encapsulation layer 105 obtained after grinding is less than 0.2 microns.

Specifically, the method for encapsulating the wafer 100 to be encapsulated by using the encapsulation layer 105 includes one of compression molding, transfer molding, liquid encapsulation, vacuum lamination and spin coating, and the material of the encapsulation layer 105 includes one of polyimide, silica gel and epoxy resin. The method may include forming a packaging material layer 104 on a structure to be packaged, and then thinning the packaging material layer 105 to expose the conductive pillars 101 to the packaging layer 105, wherein in an example, in the process of forming the packaging material layer 104, a distance between an upper surface of the packaging material layer 104 and an upper surface of the conductive pillars 101 is controlled to be greater than 50 micrometers, preferably greater than 100 micrometers, so as to facilitate improving an influence of thickness uniformity of the whole wafer 100 to be packaged in a packaging process and facilitating a subsequent grinding process. In an alternative example, the roughness of the upper surface of the encapsulation layer 105 (e.g., epoxy resin) obtained after grinding is less than 0.2 μm, which is beneficial for the subsequent process, and the adhesion of the lead-out pad 106 (bonding pad) or the redistribution layer (RDL) to the surface of the encapsulation layer 105 (e.g., resin material) can be improved.

As shown in S5 in fig. 1 and fig. 7, a lead pad 106 is prepared on the package layer 105, and the lead pad 106 is electrically connected to the conductive pillar 101.

As an example, the lead-out pad 106 includes a planarization auxiliary layer 106a and a metal connection layer 106b on the planarization auxiliary layer 106a, wherein the planarization auxiliary layer 106a is prepared based on a sputtering process, and the metal connection layer 106b is prepared based on an electroplating process.

As an example, before forming the lead-out pad 106, a step of preparing a redistribution layer on the encapsulation layer 105 is further included, the lead-out pad 106 is electrically connected to the conductive pillar 101 through the redistribution layer, and the step of preparing the redistribution layer includes: forming a dielectric layer and a metal laminated structure on the upper surface of the packaging layer 105, wherein the metal laminated structure is electrically connected with the conductive post 101, the metal laminated structure is located in the dielectric layer, the metal laminated structure comprises a plurality of metal wire layers and metal plugs which are arranged at intervals, and the metal plugs are located between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.

Specifically, after the package layer 105 is formed, the lead pad 106 electrically connected to the conductive pillar 101 is formed on the package layer 105, where the lead pad 106 may be directly electrically connected to the conductive pillar 101, or may be electrically connected to the conductive pillar 101 through a redistribution layer disposed between the lead pad 106 and the package layer 105.

In one example, the step of forming the extraction pad 106 includes:

preparing a patterned surface layer (not shown) on the encapsulation layer 105 or the redistribution layer, wherein the patterned surface layer exposes a pad region on the redistribution layer where the lead-out pad 106 is to be formed; or the upper surface of the conductive pillar 101 may be directly exposed, in which case the upper surface of the conductive pillar 101 constitutes the pad area, an

Forming the lead-out pad 106 on the pad region based on the patterned surface layer, in an example, the lead-out pad 106 includes a planarization auxiliary layer 106a and a metal connection layer 106b stacked in sequence from bottom to top, the planarization auxiliary layer 106a is prepared by a sputtering process, and the metal connection layer 106b is prepared by an electroplating process. In an example, the patterned surface layer may also be removed after processing.

As an example, the planarization auxiliary layer 106a includes a titanium layer and a copper layer stacked in sequence from bottom to top, and the metal connection layer 106b112b includes a copper layer, a nickel layer and a gold layer stacked in sequence from bottom to top.

As an example, the planarization auxiliary layer 106a has a thickness of less than 0.3 μm.

Specifically, the lead-out pad 106 is prepared on the redistribution layer or the package layer 105, the lead-out pad 106 is electrically connected with the metal wire layer in the redistribution layer or electrically connected with the conductive pillar 101, wherein the lead-out pad 106 is formed by the planarization auxiliary layer 106a and the metal connection layer 106b, the planarization auxiliary layer 106a can be used as a material layer directly formed on the surface of the metal wire layer of the redistribution layer, so as to provide a structural foundation for the preparation of the subsequent metal connection layer 106b, so that the subsequent metal connection layer 106b can be more planar, particularly, when the metal connection layer is formed by electroplating, a highly uneven condition is likely to occur during electroplating in a groove formed by a patterned surface layer, thereby affecting the electrical performance and the connection stability, and the formation of the planarization auxiliary layer 106a is beneficial to the improvement of the above condition, in one example, the planarization auxiliary layer 106a is prepared by a sputtering process, the metal connection layer 106b is prepared by adopting a metal plating mode, so that the performance and reliability of the product are improved, and optionally, the thickness of the planarization auxiliary layer 106a is less than 0.3 μm, and can be 0.8 μm or 1.5 μm, so that the arrangement of the thicknesses of the two structural layers when the lead-out welding pad 106 is formed is facilitated. In one example, the planarization auxiliary layer 106a includes a titanium layer and a copper layer stacked in sequence from bottom to top, and the metal connection layer 106b includes a copper (Cu) layer, a nickel (Ni) layer, and a gold (Au) layer stacked in sequence from bottom to top. Of course, in other examples, other material layers are also possible, and the invention is not limited thereto.

Specifically, the rewiring layer may include a plurality of dielectric layers and a plurality of metal line layers arranged according to a pattern requirement, and two adjacent metal line layers are connected by a metal plug. The dielectric layer can be made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the dielectric layer may be made of PI (polyimide), so as to further reduce the process difficulty and the process cost. The metal wire layer is made of one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium, in this embodiment, the metal wire layer is made of copper, and the metal plug is made of copper.

As shown in S6 in fig. 1 and fig. 8-9, the second surface of the wafer 100 to be packaged is thinned to expose the encapsulation layer 105 formed in the groove structure 102.

As an example, before the dicing of the wafer 100 to be packaged, the method further includes the steps of: forming a surface mount layer 107 on the second surface of the wafer 100 to be packaged, wherein the surface mount layer 107 is in contact with both the wafer 100 to be packaged and the package layer 105 in the groove structure 102.

Specifically, in this step, the back side grinding is performed on the wafer 100 to be packaged, so that the packaging layer 105 of the groove structure 102 is exposed from the bottom of the groove structure 102, so as to achieve subsequent cutting, in an example, after the grinding is performed, the method further includes a step of forming a surface mounting layer 107 on the ground surface, the surface mounting layer 107 may be made of PI (polyimide) or epoxy (epoxy resin), the surface mounting layer 107 may further increase reliability of a consolidated product, and meanwhile, the formation of the surface mounting layer 107 may enable the surface mounting layer 107 and the packaging layer 105 to jointly package a chip to be packaged, so as to achieve an effect of six-sided packaging.

As shown in S7 in fig. 1 and fig. 10-11, the wafer 100 to be packaged is diced from the position corresponding to the groove structure 102 to obtain a package structure.

Specifically, the formed packaging structure is cut finally, and the packaging layer 105 formed in the groove structure 102 is cut, so that the required packaging structure is obtained, the cutting mode is favorable for protecting the integrity of the wafer 100 to be packaged and preventing the wafer from being cracked.

Example two:

as shown in fig. 10, referring to fig. 1 to 9, the present invention further provides a wafer level chip package structure, which is preferably prepared based on the wafer level chip package method of the present invention, and the package structure includes:

a package wafer 100a, the package wafer 100a having a first surface and a second surface opposite to each other;

conductive pillars 101 formed on the first surface of the package wafer 100a and electrically connected to the package wafer 100 a;

a groove structure 102, wherein the groove structure 102 penetrates through the package wafer 100a to divide the package wafer 100a into a plurality of package chips;

an encapsulation layer 105 formed on the first surface of the package wafer 100a, wherein the encapsulation layer 105 extends into the groove structure 102 and the encapsulation layer 105 surrounds the conductive pillars 101 and exposes the tops of the conductive pillars 101; and

and a lead pad 106 formed on the package layer 105 and electrically connected to the conductive pillar 101.

Specifically, the package wafer 100a has a first surface and a second surface opposite to each other, the first surface may be a front surface of a chip, and the second surface may be a back surface of the package wafer 100a, in an example, the package wafer 100a further has an electrode region 1001, and the electrode region 1001 is disposed at the first surface to achieve electrical connection of the package chip. In this example, the packaged wafer 100a is a wafer level chip, and a plurality of chips may be formed on the wafer for packaging. The packaged wafer 100a may be an Incoming wafer type from CTM (Incoming wafer) directly from a merchant. It should be noted that, the packaged wafer 100a is a wafer obtained after the packaging process is performed on the wafer 100a to be packaged 100, and a person skilled in the art should understand the relationship between the two, and here, the packaged wafer 100a and the wafer 100a to be packaged 100 are used to distinguish the names of the two.

Specifically, the package wafer 100a is further prepared with conductive pillars 101, such as conductive copper pillars, in an example, the conductive pillars 101 are prepared on the electrode region 1001 to realize the electrical connection of the package wafer 100a, and in an example, the conductive pillars 101 including Ti sputtering/Cu electroplating are finally formed.

Specifically, a groove structure 102 is formed on the package wafer 100a, the groove structure 102 divides the package wafer 100a into a plurality of chips to be independently packaged, the number of the groove structures 102 is set according to actual requirements, in an example, the position of the groove structure 102 is correspondingly formed between the to-be-packaged wafers 100a100 corresponding to the two conductive pillars 101, and is preferably located at the center of the adjacent conductive pillars 101.

As an example, the roughness of the upper surface of the encapsulation layer 105 is less than 0.2 microns.

Specifically, the material of the encapsulation layer 105 includes one of polyimide, silicone, and epoxy resin. In an alternative example, the roughness of the upper surface of the encapsulation layer 105 (e.g., epoxy resin) obtained after grinding is less than 0.2 μm, which is beneficial for the subsequent process, and the adhesion of the lead-out pad 106 (bonding pad) or the redistribution layer (RDL) to the surface of the encapsulation layer 105 (e.g., resin material) can be improved.

As an example, the lead pad 106 includes a planarization auxiliary layer 106a and a metal connection layer 106b on the planarization auxiliary layer 106 a.

As an example, a redistribution layer is further formed between the lead-out pad 106 and the package layer 105, the lead-out pad 106 is electrically connected to the conductive pillar 101 through the redistribution layer, the redistribution layer includes a dielectric layer and a metal stacked structure, the metal stacked structure is electrically connected to the conductive pillar 101, the metal stacked structure is located in the dielectric layer, the metal stacked structure includes a plurality of metal wire layers and metal plugs, which are arranged at intervals, and the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

Specifically, the lead pad 106 may be directly electrically connected to the conductive pillar 101, or may be electrically connected to the conductive pillar 101 through a redistribution layer disposed between the lead pad 106 and the package layer 105. The auxiliary planarization layer 106a and the metal connection layer 106b are used to form the lead-out pad 106, the auxiliary planarization layer 106a can be used as a material layer directly formed on the surface of the metal wire layer of the redistribution layer, so as to provide a structural foundation for the preparation of the subsequent metal connection layer 106b, so that the auxiliary planarization layer can be more planar, and particularly, when the metal connection layer is formed by electroplating, a highly uneven condition is easily generated in a groove formed by a patterned surface layer during electroplating, so as to affect the electrical performance and connection stability, and the formation of the auxiliary planarization layer 106a is beneficial to the improvement and solution of the above condition, in one example, the auxiliary planarization layer 106a is prepared by a sputtering process, the metal connection layer 106b is prepared by a metal electroplating method, so as to improve the performance and reliability of the product, and optionally, the thickness of the auxiliary planarization layer 106a is less than 0.3 μm, may be 0.8 μm, 1.5 μm, facilitating the arrangement of the thickness of the two structural layers when constituting the lead-out pad 106. In one example, the planarization auxiliary layer 106a includes a titanium layer and a copper layer stacked in sequence from bottom to top, and the metal connection layer 106b includes a copper (Cu) layer, a nickel (Ni) layer, and a gold (Au) layer stacked in sequence from bottom to top. Of course, in other examples, other material layers are also possible, and the invention is not limited thereto.

Specifically, the rewiring layer may include a plurality of dielectric layers and a plurality of metal line layers arranged according to a pattern requirement, and two adjacent metal line layers are connected by a metal plug. The dielectric layer can be made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the dielectric layer may be made of PI (polyimide), so as to further reduce the process difficulty and the process cost. The metal wire layer is made of one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium, in this embodiment, the metal wire layer is made of copper, and the metal plug is made of copper.

As an example, the wafer-level chip package structure further includes a surface mount layer 107, the surface mount layer 107 is formed on the second surface of the package wafer 100a, and the surface mount layer 107 is in contact with both the package chip and the package layer 105 in the groove structure 102.

Specifically, in an example, a surface mount layer 107 is further formed on the ground surface, that is, the second surface, the material of the surface mount layer 107 may be PI (polyimide) or epoxy (epoxy), the surface mount layer 107 may further increase the reliability of the consolidated product, and meanwhile, the surface mount layer 107 and the encapsulation layer 105 may jointly encapsulate the chip to be encapsulated, so that a six-sided encapsulation effect is achieved.

Example three:

as shown in fig. 11 and referring to fig. 1 to 10, the present invention further provides a chip package structure, which is preferably prepared based on the wafer level chip package method of the present invention, and the package structure includes:

a packaged chip 100b, the packaged chip 100b having a first surface and a second surface opposite to each other;

a conductive pillar 101 formed on the first surface of the packaged chip 100b and electrically connected to the packaged chip 100 b;

a package layer 105 formed on the first surface of the packaged chip 100b and extending to the side surface of the wafer 100 to be packaged, wherein the package layer 105 surrounds the conductive pillars 101 and exposes the tops of the conductive pillars 101; and

and a lead pad 106 formed on the package layer 105 and electrically connected to the conductive pillar 101.

Optionally, the roughness of the upper surface of the encapsulation layer 105 is less than 0.2 microns.

Optionally, the lead pad 106 includes a planarization auxiliary layer 106a and a metal connection layer 106b on the planarization auxiliary layer 106 a.

Optionally, a redistribution layer is further formed between the lead-out pad 106 and the package layer 105, the lead-out pad 106 is electrically connected to the conductive post 101 through the redistribution layer, the redistribution layer includes a dielectric layer and a metal stacked structure, the metal stacked structure is electrically connected to the conductive post 101, the metal stacked structure is located in the dielectric layer, the metal stacked structure includes a plurality of metal wire layers arranged at intervals and metal plugs, and the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

Optionally, the chip package structure further includes a surface mount layer 107 formed on the second surface of the package chip 100b, and the surface mount layer 107 is in contact with both the package chip 100b and the package layer 105 on the side surface of the package chip 100 b.

Specifically, the embodiment further provides a chip packaging structure, wherein the chip packaging structure is obtained by packaging based on the wafer level chip packaging method provided in the first embodiment of the present invention, and the difference from the second embodiment is that in the structure of the second embodiment, a packaged wafer is cut along the groove structure 102 to obtain a packaged chip of the third embodiment, that is, the packaged chip is a chip obtained by performing packaging processing on the wafer 100 to be packaged.

In summary, the present invention provides a wafer level package structure and a packaging method, wherein the packaging method includes: providing a wafer to be packaged, wherein the wafer to be packaged is provided with a first surface and a second surface which are opposite; preparing a conductive column on the first surface, wherein the conductive column is electrically connected with the wafer to be packaged; preparing a groove structure in the wafer to be packaged, wherein the groove structure extends from the first surface to the interior of the wafer to be packaged so as to divide the wafer to be packaged into a plurality of chips to be packaged; forming an encapsulation layer surrounding the conductive posts and exposing tops of the conductive posts on the first surface, wherein the encapsulation layer extends into the groove structures; preparing a lead-out welding pad on the packaging layer, wherein the lead-out welding pad is electrically connected with the conductive column; thinning the second surface of the wafer to be packaged to expose the packaging layer formed in the groove structure; and cutting the wafer to be packaged from the position corresponding to the groove structure to obtain a packaging structure. Through the scheme, the wafer level packaging method for cutting the wafer based on the groove structure is adopted, the chip is protected favorably in fan-out type wafer level packaging, the wafer is prevented from being broken, the manufacturing process is shortened, the operation period is shortened, the product yield is improved, and the product cost is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.