阅读说明：本技术 半导体封装 (Semiconductor package ) 是由 千镇豪 安振镐 郑泰和 秦正起 崔朱逸 藤崎纯史 于 2020-07-30 设计创作，主要内容包括：提供了半导体封装,其包括再分布基板和安装在再分布基板上的半导体芯片。再分布基板可以包括下保护层、设置在下保护层上的第一导电图案、围绕第一导电图案并设置在下保护层上的第一绝缘层、以及设置在第一绝缘层上的第二绝缘层。第一绝缘层可以包括第一上表面,第一上表面包括平行于下保护层的上表面延伸的第一平坦部分、以及面对下保护层并与第一导电图案接触的第一凹陷。第一凹陷可以直接连接到第一导电图案。(A semiconductor package is provided that includes a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface including a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and contacting the first conductive pattern. The first recess may be directly connected to the first conductive pattern.)

1. A semiconductor package, comprising:

a redistribution substrate; and

a semiconductor chip on the redistribution substrate,

wherein the redistribution substrate comprises:

a lower protective layer;

a first conductive pattern on the lower protective layer;

a first insulating layer surrounding the first conductive pattern and on the lower protective layer, the first insulating layer including a first upper surface including a first flat portion extending parallel to an upper surface of the lower protective layer, the first upper surface of the first insulating layer further including a first recess directly connected to the first conductive pattern; and

a second insulating layer on the first insulating layer.

2. The semiconductor package of claim 1, wherein the first planar portion of the first upper surface of the first insulating layer is coplanar with an upper surface of the first conductive pattern.

3. The semiconductor package of claim 1, wherein the second insulating layer is in contact with the first upper surface of the first insulating layer, and a portion of the second insulating layer is in the first recess of the first insulating layer.

4. The semiconductor package of claim 1, wherein the first recess comprises a side surface directly connected to the first conductive pattern and inclined with respect to the upper surface of the lower protective layer;

a distance between a first portion of the side surface of the first recess and a side surface of the first conductive pattern is longer than a distance between a second portion of the side surface of the first recess and the side surface of the first conductive pattern, an

A distance from the upper surface of the lower protective layer to the first portion of the side surface of the first recess is shorter than a distance from the upper surface of the lower protective layer to the second portion of the side surface.

5. The semiconductor package of claim 1, wherein the first recess comprises a side surface and a lower surface, and the side surface of the first recess is directly connected to the first conductive pattern and is located between the first conductive pattern and the lower surface of the first recess, and

a distance from the upper surface of the lower protective layer to the lower surface of the first recess is 0.7 times to 0.9 times a distance from the upper surface of the lower protective layer to the first flat portion of the first upper surface of the first insulating layer.

6. The semiconductor package of claim 1, wherein the first planar portion of the first upper surface of the first insulating layer is planar.

7. The semiconductor package of claim 1, further comprising a second conductive pattern on the first conductive pattern,

wherein the second insulating layer surrounds the second conductive pattern.

8. The semiconductor package of claim 7, wherein the second insulating layer comprises a second upper surface comprising a second flat portion extending parallel to the upper surface of the lower protective layer; and

the second upper surface of the second insulating layer further includes a second recess between the second flat portion of the second upper surface of the second insulating layer and the second conductive pattern.

9. The semiconductor package of claim 7, further comprising a terminal pad on the second insulating layer and electrically connecting the second conductive pattern to the semiconductor chip.

10. The semiconductor package of claim 1, further comprising a third conductive pattern extending from the first conductive pattern and extending between the second insulating layer and the first insulating layer.

11. The semiconductor package according to claim 1, wherein a distance between the first flat portion of the first upper surface of the first insulating layer and the upper surface of the lower protective layer is longer than a distance between an upper surface of the first conductive pattern and the upper surface of the lower protective layer.

12. The semiconductor package of claim 1, further comprising an upper protective layer on the second insulating layer,

wherein the first insulating layer and the second insulating layer comprise a photosensitive insulating material, an

The upper protective layer includes an oxide or a nitride.

13. A semiconductor package, comprising:

a lower protective layer;

a first conductive pattern on the lower protective layer;

a first insulating layer on the lower protective layer and contacting a side surface of the first conductive pattern;

a second insulating layer on the first insulating layer and the first conductive pattern; and

a semiconductor chip on the second insulating layer,

wherein the first insulating layer includes a first upper surface and an inclined surface adjacent to the side surface of the first conductive pattern,

the first upper surface of the first insulating layer extends parallel to an upper surface of the lower protective layer, an

A distance from the upper surface of the lower protective layer to a first portion of the inclined surface of the first insulating layer is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface of the first insulating layer.

14. The semiconductor package according to claim 13, wherein a distance from the upper surface of the lower protective layer to the first upper surface of the first insulating layer is equal to or longer than a distance from the upper surface of the lower protective layer to an upper surface of the first conductive pattern.

15. The semiconductor package of claim 13, wherein a distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and

the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is shorter than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

16. The semiconductor package of claim 13, wherein a distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and

the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is longer than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

17. The semiconductor package of claim 13, further comprising:

a second conductive pattern extending through the second insulating layer and contacting the first conductive pattern, wherein the second conductive pattern is electrically connected to the semiconductor chip; and

an upper protective layer on the second insulating layer and the second conductive pattern.

18. The semiconductor package of claim 17, wherein the first and second insulating layers comprise a photosensitive insulating material, an

The upper protective layer includes an oxide or a nitride.

19. A semiconductor package, comprising:

a redistribution substrate;

a semiconductor chip on the redistribution substrate; and

molding a film on the redistribution substrate and on a side surface of the semiconductor chip,

wherein the redistribution substrate comprises:

a lower protective layer;

a first conductive pattern on the lower protective layer;

a first insulating layer on the lower protective layer and surrounding the first conductive pattern;

a second insulating layer on the first insulating layer and the first conductive pattern; and

a terminal pad on the second insulating layer and electrically connected to the semiconductor chip, an

Wherein the first insulating layer includes an inclined surface, a first upper surface and a second upper surface,

the second upper surface is coplanar with an upper surface of the first conductive pattern,

a distance from an upper surface of the lower protective layer to the first upper surface is shorter than a distance from the upper surface of the lower protective layer to the second upper surface, an

A distance from the upper surface of the lower protective layer to a first portion of the inclined surface is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface.

20. The semiconductor package of claim 19, wherein a distance between the first portion of the inclined surface and a side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and

the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is shorter than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

21. The semiconductor package of claim 19, wherein a highest end of the inclined surface is at an equal level with the second upper surface of the first insulating layer and the upper surface of the first conductive pattern.

22. The semiconductor package of claim 19, wherein a distance between the first portion of the inclined surface and a side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and

the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is greater than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

23. The semiconductor package of claim 19, further comprising:

a second conductive pattern extending from the upper surface of the first conductive pattern onto the first insulating layer and extending between the second insulating layer and the first insulating layer, an

A third conductive pattern extending through the second insulating layer and electrically connected to the second conductive pattern.

24. The semiconductor package of claim 19, further comprising an upper protective layer on the second insulating layer,

wherein the terminal pad extends through the upper protective layer and is electrically connected to the first conductive pattern.

25. The semiconductor package of claim 19, wherein the first and second insulating layers comprise a photosensitive insulating material.

Technical Field

The present disclosure relates to semiconductor packages.

Background

Semiconductor packages in which integrated circuit chips are included may be included in electronic devices. A semiconductor package may be manufactured by mounting semiconductor chips on a substrate such as a Printed Circuit Board (PCB) and electrically connecting the semiconductor chips to each other using bonding wires or bumps.

With the development of the electronics industry, there is an increasing demand for high-function, high-speed and smaller electronic components. Accordingly, a semiconductor device or a semiconductor package having high-speed signal transmission, reduced size, and wire redistribution has been developed.

Disclosure of Invention

According to an example embodiment of the inventive concepts, there is provided a semiconductor package including: a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate includes: a lower protective layer; a first conductive pattern disposed on the lower protective layer; a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, the first insulating layer including a first upper surface including a first flat portion extending parallel to an upper surface of the lower protective layer and a first recess facing the lower protective layer and directly connected to the first conductive pattern; and a second insulating layer disposed on the first insulating layer.

According to an example embodiment of the inventive concepts, there is provided a semiconductor package including: a lower protective layer; a first conductive pattern disposed on the lower protective layer; a first insulating layer on the lower protective layer in contact with a side surface of the first conductive pattern; a second insulating layer covering or extending over the first insulating layer and the first conductive pattern; and a semiconductor chip disposed on the second insulating layer. The first insulating layer may include a first upper surface and an inclined surface adjacent to a side surface of the first conductive pattern, and the first upper surface of the first insulating layer may extend parallel to the upper surface of the lower protective layer, and a distance from the upper surface of the lower protective layer to the inclined surface varies toward the first conductive pattern.

According to an example embodiment of the inventive concepts, there is provided a semiconductor package including: a redistribution substrate; a semiconductor chip mounted on the redistribution substrate; and a molding film covering or extending over the side surface of the semiconductor chip on the redistribution substrate. The redistribution substrate may include: a lower protective layer; a first conductive pattern disposed on the lower protective layer; a first insulating layer surrounding the first conductive pattern on the lower protective layer; a second insulating layer covering the first insulating layer and the first conductive pattern; and a terminal pad disposed on the second insulating layer and to which the semiconductor chip is electrically connected, the first insulating layer including an inclined surface, a first upper surface, and a second upper surface sequentially positioned from the first conductive pattern, the second upper surface being located at the same level as the upper surface of the first conductive pattern. The first upper surface is located at a lower level than the second upper surface, and a distance from the upper surface of the lower protective layer to the inclined surface varies from the first upper surface to the first conductive pattern.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor package according to an example embodiment of the inventive concepts.

Fig. 2A illustrates a plan view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concepts.

Fig. 2B illustrates a cross-sectional view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concepts.

Fig. 3A to 3C show enlarged views of the region a of fig. 2B.

Fig. 4 illustrates a cross-sectional view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concepts.

Fig. 5A is a plan view illustrating a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concepts.

Fig. 5B and 5C illustrate cross-sectional views of a redistribution substrate of a semiconductor package according to example embodiments of the inventive concepts.

Fig. 6 to 11 illustrate cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments of the inventive concepts.

Detailed Description

Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same constituent elements, and a repetitive description thereof may be omitted.

Fig. 1 illustrates a cross-sectional view of a semiconductor package according to an example embodiment of the inventive concepts. Fig. 2A is a plan view illustrating a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concepts. Fig. 2A schematically illustrates the redistribution substrate of the semiconductor package of fig. 1, and for ease of description, some components are not shown. Fig. 2B illustrates a cross-sectional view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concept, and corresponds to a cross-section taken along line I-I' of fig. 2A. Fig. 3A to 3C show enlarged views of the region a of fig. 2B.

Referring to fig. 1, 2A and 2B, a semiconductor package 1000 may include a redistribution substrate 10, a semiconductor chip 20, and a molding layer 30.

The redistribution substrate 10 may include a lower protection layer 100 and first and second wiring layers 200 and 300 stacked on the lower protection layer 100.

The lower protective layer 100 may protect and support the wiring layers 200 and 300. The lower protective layer 100 may include a silicon substrate and/or an insulating substrate. For example, the lower protective layer 100 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and/or a polyamide-based polymer material, but the lower protective layer 100 is not limited thereto. The lower protective layer 100 may be omitted. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The first wiring layer 200 may be disposed on the lower protection layer 100. The first wiring layer 200 may include a first conductive pattern 210 and a first insulating layer 220.

The first conductive pattern 210 may be disposed on the lower protective layer 100. The first conductive pattern 210 may include various components constituting a circuit in the first wiring layer 200. For example, the first conductive pattern 210 may be a conductive pad to which an external terminal or a conductive via is connected. In fig. 2B, the first conductive pattern 210 is illustrated as a conductive pad, but the inventive concept is not limited thereto. For example, the first conductive pattern 210 may include: a conductive via electrically connecting the upper wiring layer and the lower wiring layer; conductive wirings extending in a direction parallel to the upper surface of the lower protective layer 100 to form a circuit; or a conductive pad having a width wider than a line width of the conductive via or the conductive cloth. Conductive vias, conductive wires, external solder balls, etc. may be connected to the conductive pads.

As used herein, "electrically connected" (or similar language) may mean "directly or indirectly electrically connected". The first conductive pattern 210 may include a conductive material. For example, the first conductive pattern 210 may include copper (Cu), a copper alloy, and/or aluminum (Al).

A plurality of first conductive patterns 210 may be provided. As shown in fig. 1 and 2A, the first conductive patterns 210 may be disposed on the lower protective layer 100, and may be horizontally spaced apart from each other. In this case, the distance between the first conductive patterns 210 may be greater than the width of the first recesses RS1 of the first insulating layer 220 (which will be described later). One of the first conductive patterns 210 may include a conductive pad, and the other of the first conductive patterns 210' may include a passive element.

For example, the passive component may be a capacitor as shown in fig. 1. In some implementations, the passive elements can include various passive elements, such as resistive elements. In some embodiments, the first conductive pattern 210 may include both conductive pads and passive elements, or only conductive pads or passive elements.

The first insulating layer 220 may be disposed on the lower protective layer 100. The first insulating layer 220 may surround the first conductive pattern 210 in a plan view. The first insulating layer 220 may contact the side surface 210b of the first conductive pattern 210. The first insulating layer 220 may include an insulating material. For example, the first insulating layer 220 may include a Dry Film Resist (DFR) and/or a Photo Imageable Dielectric (PID). The upper surface of the first insulating layer 220 may include a first upper surface 220a surrounding the first conductive pattern 210, a second upper surface 220b between the first conductive pattern 210 and the first upper surface 220a, and a first inclined surface 220c extending from the second upper surface 220b to face the side surface 210b of the first conductive pattern 210. That is, the second upper surface 220b may be located inside the first upper surface 220a in a plan view, and may surround the first conductive pattern 210. In addition, the first inclined surface 220c may be located inside the second upper surface 220b in a plan view, and may surround the first conductive pattern 210.

The first upper surface 220a may be substantially flat. The first upper surface 220a may be parallel to the upper surface of the lower protective layer 100. As shown in fig. 3A, the first upper surface 220a may be located at the same level as the upper surface 210a of the first conductive pattern 210. The first upper surface 220a may be coplanar with the upper surface 210a of the first conductive pattern 210, as shown in fig. 3A. In some embodiments, the first upper surface 220a may be located at a higher level than the upper surface 210a of the first conductive pattern 210, as shown in fig. 3B. A distance between the first upper surface 220a and the lower protective layer 100 may be longer than a distance between the upper surface 210a of the first conductive pattern 210 and the lower protective layer 100, as shown in fig. 3B. In some embodiments, the first upper surface 220a may be located at a lower level than the upper surface of the first conductive pattern 210, as shown in fig. 3C. A distance between the first upper surface 220a and the lower protective layer 100 may be shorter than a distance between the upper surface 210a of the first conductive pattern 210 and the lower protective layer 100, as shown in fig. 3C. In some embodiments, the second upper surface 220b may be located at a lower level than the first upper surface 220 a. The distance between the second upper surface 220B and the lower protective layer 100 may be shorter than the distance between the first upper surface 220a and the lower protective layer 100, as shown in fig. 3A, 3B, and 3C. "distance between element a and element B" (or similar language) may refer to the shortest distance between element a and element B.

For example, the first insulating layer 220 may include a first recess RS1 recessed toward the lower protection layer 100. The lowermost (i.e., lowermost) point LP of the first recess RS1 may be lower than the first upper surface 220 a. The first recess RS1 may be located between the first conductive pattern 210 and the first upper surface 220a of the first insulating layer 220. For example, as shown in fig. 2A, in a plan view, the first recess RS1 may be formed in a portion of the first insulating layer 220 adjacent to the first conductive pattern 210, and the first recess RS1 may surround the first conductive pattern 210. That is, the first recess RS1 may separate the first conductive pattern 210 from the first upper surface 220a of the first insulating layer 220.

The bottom surface of the first recess RS1 may be the same component as the second upper surface 220b, and the same reference numerals may be used herein. In some embodiments, the second upper surface 220b may define a bottom surface of the first recess RS 1. A distance from the upper surface of the lower protection layer 100 to the bottom surface 220b of the first recess RS1 may be, for example, 0.5 to 1 times a distance from the upper surface of the lower protection layer 100 to the first upper surface 220 a. In some embodiments, the distance from the upper surface of the lower protective layer 100 to the lower surface 220b of the first recess RS1 is 0.7 times to 0.9 times the distance from the upper surface of the lower protective layer 100 to the first upper surface 220a, as shown in fig. 3A.

The first inclined surface 220c may extend from one end of the second upper surface 220b to the side surface 210b of the first conductive pattern 210. The first inclined surface 220c may be inclined with respect to the second upper surface 220 b. According to fig. 3A, the first inclined surface 220c may be a first side of the first recess RS1, which extends from the bottom surface 220b of the first recess RS1 toward the side surface 210b of the first conductive pattern 210. The first inclined surface 220c may define a first side surface of the first recess RS 1. Here, the first side surface of the first recess RS1 adjacent to the first conductive pattern 210 may be the same member as the first inclined surface 220c, and thus the same reference numerals may be used.

The first side surface 220c of the first recess RS1 may be inclined with respect to both the side surface 210b of the first conductive pattern 210 and the first upper surface 220a of the first insulating layer 220. A distance between the first side surface 220c and the lower protective layer 100 may increase from the second upper surface 220b toward the first conductive pattern 210. In some embodiments, the distance between the first side surface 220C and the lower protective layer 100 may increase as the distance from the second upper surface 220b increases, as shown in fig. 3A to 3C.

In detail, as shown in fig. 3A, a first distance D1 between the lowest point LP of the first side surface 220c of the first recess RS1 and the lower protective layer 100 may be shorter than a second distance D2 between the first upper surface 220a and the lower protective layer 100. That is, the first inclined surface 220c may be a surface extending in an obliquely upward direction from the second upper surface 220b corresponding to the bottom surface 220b of the first recess RS 1. The first distance D1 may be equal to the distance between the second upper surface 220b and the lower protective layer 100. A third distance D3 between the highest point TP of the first side surface 220c of the first recess RS1 and the lower protective layer 100 may be equal to a second distance D2 between the first upper surface 220a of the first insulating layer 220 and the lower protective layer 100. That is, the highest point TP of the first side surface 220c of the first recess RS1 may be located at the same level as the upper surface 210a of the first conductive pattern 210. The highest point TP of the first side surface 220c may be the highest point of the first insulating layer 220.

In some embodiments, the highest point TP of the first side surface 220C of the first recess RS1 may be located at a level lower than the upper surface 210a of the first conductive pattern 210, as shown in fig. 3C. That is, a distance between the highest point TP of the first side surface 220c of the first recess RS1 and the lower protection layer 100 may be shorter than a distance between the upper surface 210a of the first conductive pattern 210 and the lower protection layer 100.

In an example embodiment, the first inclined surface 220c of the first insulating layer 220 may be inclined with respect to the second upper surface 220 b. Fig. 4 illustrates a cross-sectional view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concepts. As shown in fig. 4, the distance between the first inclined surface 220c and the lower protective layer 100 may decrease as the distance from the second upper surface 220b increases. In detail, a distance between the lowest point LP of the first inclined surface 220c and the lower protection layer 100 may be shorter than a distance between the second upper surface 220b of the first insulation layer 220 and the lower protection layer 100. That is, the first inclined surface 220c may be a surface extending downward from the second upper surface 220 b. The first inclined surface 220c may extend from the second upper surface 220b toward the lower protection layer 100, as shown in fig. 4. A distance from the lower protective layer 100 to the lowest point LP of the first inclined surface 220c may be, for example, 0.5 to 1 times a distance from the lower protective layer 100 to the first upper surface 220 a. Hereinafter, the description will be continued with reference back to fig. 1, 2A, and 2B.

Referring back to fig. 1, 2A, and 2B, a second wiring layer 300 may be disposed on the first wiring layer 200. The second wiring layer 300 may include a second conductive pattern 310, a third conductive pattern 320, and a second insulating layer 330.

The second conductive pattern 310 and the third conductive pattern 320 may be disposed on the first wiring layer 200. In detail, the second conductive pattern 310 may be disposed on the first conductive pattern 210. The third conductive pattern 320 may be disposed on the first insulating layer 220. The second conductive pattern 310 and the third conductive pattern 320 may include various components constituting a circuit in the second wiring layer 300. For example, the second conductive pattern 310 may be a conductive pad connected to the first conductive pattern 210 of the first wiring layer 200, and the third conductive pattern 320 may be a conductive wire extending from the upper surface 210a of the first conductive pattern 210 to the upper surface of the first insulating layer 220 to constitute a circuit. In some embodiments, similar to the first conductive pattern 210 described above, the second conductive pattern 310 may include a passive element, such as a capacitor or a resistive element. A plurality of second conductive patterns 310 may be provided. As shown in fig. 2B, one 312 of the second conductive patterns 310 may be connected to the first conductive pattern 210, and the other 314 of the second conductive patterns 310 may be provided on the first insulating layer 220. The second conductive patterns 310 may be electrically connected through the third conductive patterns 320. The third conductive pattern 320 may extend along the top surface of the first insulating layer 220.

The third conductive pattern 320 extends from the top surface 210a of the first conductive pattern 210 along the bottom surface 220b of the first recess RS1 of the first insulating layer 220. The third conductive pattern 320 may extend from the first recess RS1 to the first upper surface 220 a. The thickness of the third conductive pattern 320 may be thinner than that of the second conductive pattern 310. Each of the second conductive pattern 310 and the third conductive pattern 320 may include a conductive material. For example, each of the second and third conductive patterns 310 and 320 may independently include copper (Cu), a copper alloy, and/or aluminum (Al). In some embodiments, the second conductive pattern 310 and the third conductive pattern 320 may include different conductive materials.

The second insulating layer 330 may be disposed on the first insulating layer 220. The second insulating layer 330 may cover the first insulating layer 220 and the first conductive pattern 210. In this case, the second insulating layer 330 may fill the first recesses RS1 of the first insulating layer 220. That is, the second insulating layer 330 may be in contact with the first and second upper surfaces 220a and 220b of the first insulating layer 220. The second insulating layer 330 may surround the second conductive pattern 310. The second insulating layer 330 may cover the third conductive pattern 320. The second insulating layer 330 may be in contact with the side surface 310b of the second conductive pattern 310. The second insulating layer 330 may include an insulating material. It will be understood that "element a covers element B" (or similar language) means that element a extends over element B, but does not necessarily mean that element a completely covers element B. It should also be understood that as used herein, "element a fills element B" (or similar language) means that element a is in element B, but does not necessarily mean that element a completely fills element B.

For example, the second insulating layer 330 may include a Dry Film Resist (DFR) and/or a photo-imageable dielectric (PID). The second insulating layer 330 may include a third upper surface 330a surrounding the second conductive pattern 310, a fourth upper surface 330b disposed between the second conductive pattern 310 and the third upper surface 330a, and a second inclined surface 330c extending from the fourth upper surface 330b toward the side surface 310b of the second conductive pattern 310.

The third upper surface 330a may be substantially flat. The third upper surface 330a may be parallel to the upper surface of the lower protective layer 100. The third upper surface 330a may be positioned at the same level as the upper surface 310a of the second conductive pattern 310. In some embodiments, the third upper surface 330a may be located at a level higher or lower than the upper surface 310a of the second conductive pattern 310, similar to the first upper surface 220a of the first insulating layer 220.

The fourth upper surface 330b may be located at a lower level than the third upper surface 330 a. For example, the second insulation layer 330 may include a second recess RS2, the second recess RS2 being recessed from the third upper surface 330a toward the lower protection layer 100. The lowest point of the second recess RS2 may be lower than the third upper surface 330 a. The second recess RS2 may be located between the second conductive pattern 310 and the third upper surface 330a of the second insulating layer 330.

The second inclined surface 330c may extend from one end of the fourth upper surface 330b to the side surface 310b of the second conductive pattern 310. The second inclined surface 330c may be inclined with respect to the fourth upper surface 330 b. According to fig. 3A to 3C, the second inclined surface 330C may be a second side surface 330C of the second recess RS2, which extends from the bottom surface 330b of the second recess RS2 toward the side surface 310b of the second conductive pattern 310. The distance between the second side surface 330c and the lower protective layer 100 may increase from the fourth upper surface 330b to the second conductive pattern 310. In some embodiments, the distance between the second side surface 330C and the lower protective layer 100 may increase as the distance from the fourth upper surface 330b increases, as shown in fig. 3A to 3C.

The second inclined surface 330c may be a surface extending in an obliquely upward direction from the bottom surface 330b of the second recess RS 2. The highest point of the second side surface 330c of the second recess RS2 may contact the upper surface 310a of the second conductive pattern 310. In some embodiments, the highest point of the second side surface 330c of the second recess RS2 may be directly connected to the upper surface 310a of the second conductive pattern 310. In some embodiments, the highest point of the second side surface 330c of the second recess RS2 may be located at a lower level than the top surface 310a of the second conductive pattern 310.

The upper protective layer 400 may be disposed on the second wiring layer 300. The upper protective layer 400 may cover the second insulating layer 330 and the second conductive pattern 310. In this case, the upper protection layer 400 may fill the second recess RS2 of the second insulation layer 330. That is, the upper protection layer 400 may contact the third and fourth upper surfaces 330a and 330b of the second insulation layer 330. The upper surface of the upper protective layer 400 may be substantially flat. The upper protection layer 400 may protect the first wiring layer 200 and the second wiring layer 300 of the redistribution substrate 10. The upper protection layer 400 may include an insulating material. For example, the upper protection layer 400 may include, but is not limited to, an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and/or a polyamide-based polymer material.

The terminal pad 410 may be disposed on the upper protective layer 400. The terminal pad 410 may be connected to the second conductive pattern 310, and may extend through the upper protective layer 400. The terminal pad 410 may include a conductive material, such as a metal. The redistribution substrate 10 of the semiconductor package is constructed as described above.

The connection terminals 420 may be disposed on the redistribution substrate 10. For example, the connection terminal 420 may be disposed on the terminal pad 410. The connection terminals 420 may be chip terminals of a semiconductor chip mounted on the redistribution substrate 10, or external terminals for mounting the redistribution substrate 10 on another substrate. The connection terminals 420 may include solder balls, solder bumps, and the like.

The external terminals 120 may be disposed under the redistribution substrate 10. For example, the substrate pads 110 may be disposed on the bottom surface of the lower protective layer 100 of the redistribution substrate 10. The substrate pad 110 may be connected to the first conductive pattern 210 of the first wiring layer 200 and may extend through the lower protective layer 100. The external terminal 120 may be disposed on the substrate pad 110. The external terminal 120 may be electrically connected to the first wiring layer 200 and the second wiring layer 300 through the substrate pad 110.

The semiconductor chip 20 may be mounted on the redistribution substrate 10. The lower surface of the semiconductor chip 20 facing the redistribution substrate 10 may be an active surface. The semiconductor chip 20 may be flip-chip mounted on the redistribution substrate 10. For example, the semiconductor chip 20 may be electrically connected to the redistribution substrate 10 through the connection terminals 420 provided on the bottom surface of the semiconductor chip 20. The connection terminals 420 may be connected to chip terminals (not shown) of the semiconductor chip 20 and the terminal pads 410 of the redistribution substrate 10. The connection terminal 420 may include a solder ball or a solder bump. The semiconductor chip 20 may be electrically connected to the second conductive pattern 310 through the connection terminal 420 and the terminal pad 410. The redistribution substrate 10 may electrically connect the semiconductor chips 20 using the first wiring layer 200 and the second wiring layer 300. The semiconductor chip 20 may include silicon (Si).

The molding layer 30 may be provided on the redistribution substrate 10. The molding layer 30 may cover the semiconductor chip 20 on the upper surface of the redistribution substrate 10. For example, the molding layer 30 may cover the top surface and the side surfaces of the semiconductor chip 20. The molding layer 30 may fill a space between the semiconductor chip 20 and the redistribution substrate 10. The molding layer 30 may include, for example, an insulating material such as an epoxy polymer. In some embodiments, the space between the semiconductor chip 20 and the redistribution substrate 10 may be filled with an underfill member.

Fig. 5A is a plan view illustrating a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concept, schematically illustrating the redistribution substrate of the semiconductor package of fig. 1, and some components may not be shown for convenience of description. Fig. 5B and 5C illustrate cross-sectional views of a redistribution substrate of a semiconductor package according to example embodiments of the inventive concepts, and correspond to a cross-section taken along line II-II' of fig. 5A. For convenience of description, in the following embodiments, components described in the embodiments of fig. 2A and 2B may be referred to using the same reference numerals, and a description thereof may be omitted or briefly described for convenience of description. That is, the following description will focus on differences from the redistribution substrate of fig. 2A and 2B.

Referring to fig. 5A and 5B, the first and second upper surfaces 220a and 220B of the first insulating layer 220 may be located at the same level. The first and second upper surfaces 220a and 220b may be coplanar and may be substantially planar. That is, the first upper surface 220a and the second upper surface 220b may form one surface. Hereinafter, the entirety of the first and second upper surfaces 220a and 220b will be referred to as a single upper surface 220a/220 b. The single upper surface 220a/220b may be located at a lower level than the top surface 210a of the first conductive pattern 210. The distance from the lower protective layer 100 to the single upper surface 220a/220b may be, for example, 0.5 to 1 times the distance from the lower protective layer 100 to the upper surface 210a of the first conductive pattern 210.

The first inclined surface 220c may extend from one end of the single upper surface 220a/220b to the side surface 210b of the first conductive pattern 210. The first inclined surface 220c may be located between the first conductive pattern 210 and the single upper surface 220a/220 b. For example, as shown in fig. 5A, the first inclined surface 220c may be formed on a portion of the first insulating layer 220 adjacent to the first conductive pattern 210 in a plan view, and the first inclined surface 220c may surround the first conductive pattern 210. The first inclined surface 220c may be positioned inside the single upper surface 220a/220b in a plan view, and may surround the first conductive pattern 210. That is, the first inclined surface 220c may separate the first conductive pattern 210 from the single upper surface 220a/220b of the first insulating layer 220.

The first inclined surface 220c may be inclined with respect to the single upper surface 220a/220 b. The distance between the first inclined surface 220c and the lower protective layer 100 may increase from the single upper surface 220a/220b toward the first conductive pattern 210. In some embodiments, the distance between the first inclined surface 220c and the lower protective layer 100 may increase as the distance from the single upper surface 220a/220B increases, as shown in fig. 5B. The highest point TP of the first inclined surface 220c may be located at the same level as the upper surface 210a of the first conductive pattern 210 or at a lower level than the upper surface 210 a. That is, the first inclined surface 220c may be a surface extending obliquely upward from the single upper surface 220a/220 b.

According to some embodiments, as shown in fig. 5C, the first and second upper surfaces 220a and 220b of the first insulating layer 220 may be located at the same level. The first and second upper surfaces 220a and 220b may be coplanar and may be substantially planar. The first and second upper surfaces 220a and 220b may be located at the same level as the upper surface 210a of the first conductive pattern 210. In some embodiments, the first and second upper surfaces 220a and 220b may be located at a level higher or lower than the upper surface 210a of the first conductive pattern 210.

The first inclined surface 220c of the first insulating layer 220 may be inclined with respect to the second upper surface 220 b. The distance between the first inclined surface 220c and the lower protective layer 100 may decrease from the second upper surface 220b toward the first conductive pattern 210. In some embodiments, the distance between the first inclined surface 220C and the lower protective layer 100 may decrease as the distance from the second upper surface 220b increases, as shown in fig. 5C. In detail, a distance between the lowest point LP of the first inclined surface 220c and the lower protective layer 100 may be less than or equal to a distance between the upper surface 210a of the first conductive pattern 210 and the lower protective layer 100. That is, the first inclined surface 220c may be a surface extending obliquely downward from the second upper surface 220 b. A distance from the lower protective layer 100 to the lowest point LP of the first inclined surface 220c may be, for example, 0.5 to 1 times a distance from the lower protective layer 100 to the upper surface 210a of the first conductive pattern 210. The redistribution substrate 10' of the semiconductor package may be constructed as described above with reference to fig. 5A-5C.

The connection terminals 420 may be disposed on the redistribution substrate 10'. External terminals (e.g., external terminals 120 in fig. 1) may be disposed below the redistribution substrate 10'. The semiconductor chip 20 may be mounted on the redistribution substrate 10'. The semiconductor chip 20 may be electrically connected to the redistribution substrate 10' through the connection terminals 420 provided on the bottom surface of the semiconductor chip 20. The molding layer 30 may be provided on the redistribution substrate 10'. The molding layer 30 may cover the semiconductor chip 20 on the upper surface of the redistribution substrate 10'.

Fig. 6 to 11 illustrate cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

Referring to fig. 6, a lower protective layer 100 may be provided. The lower protective layer 100 may include a first region RG1, a second region RG2 surrounding the first region RG1, and a third region RG3 disposed between the first region RG1 and the second region RG 2. The first region RG1 may be a region in which the first conductive pattern 210 of the first wiring layer 200 (e.g., the first wiring layer 200 in fig. 1) is formed, and the second region RG2 and the third region RG3 may each be a region in which the first insulating layer 220 of the first wiring layer 200 (e.g., the first insulating layer 220 in fig. 1) is formed.

A first wiring layer 200 including a first insulating layer 220 and a first conductive pattern 210 may be formed on the lower protective layer 100. Hereinafter, a process of forming the first wiring layer will be described in detail with reference to fig. 6 and 7.

Referring to fig. 6, the first conductive pattern 210 may be formed on the first region RG1 of the lower protective layer 100. For example, after forming a seed layer on the lower protection layer 100, a mask may be formed on the seed layer to expose the first region RG 1. Thereafter, the first conductive pattern 210 may be formed by filling a conductive material in the pattern of the mask through a plating process or the like. In some embodiments, after forming a conductive film on the lower protective layer 100, the first conductive pattern 210 may be formed by patterning the conductive film.

A first insulating film 222 may be formed on the lower protection layer 100. For example, the first insulating film 222 may be formed by coating or depositing an insulating material on the lower protective layer 100. The coating process of the insulating material may include a spin coating process or a roll coating process. The insulating material may include a photosensitive insulating material. For example, the insulating material may include a Dry Film Resist (DFR) and/or a photoimageable dielectric (PID).

The thickness of the first insulating film 222 may be the same as that of a first insulating layer 220 to be formed later (e.g., the first insulating layer 220 in fig. 7). The first insulating film 222 may cover the first conductive pattern 210. The first insulating film 222 disposed on the lower protective layer 100 and the first conductive pattern 210 may be elevated in the third region RG3 adjacent to the first conductive pattern 210 due to the thickness of the first conductive pattern 210 located on the upper surface of the lower protective layer 100.

The upper surface of the first insulating film 222 in the third region RG3 may gradually rise from the second region RG2 toward the first region RG 1. The first insulating film 222 may protrude upward in the first region RG1 and the third region RG3 adjacent to the first region RG 1. The height of the upper surface of the first insulating film 222 on the first region RG1 and the third region RG3 may be higher than the height of the upper surface of the first insulating film 222 on the second region RG 2. The height of the upper surface of the first insulating film 222 on the second region RG2 may be the same as the height of the upper surface of the first conductive pattern 210. In some embodiments, the upper surface of the first insulating film 222 on the second region RG2 and the upper surface of the first conductive pattern 210 may be coplanar with each other, and the upper surfaces of the first insulating film 222 on the first region RG1 and the third region RG3 may be higher than the upper surface of the first insulating film 222 on the second region RG2, as shown in fig. 6.

Referring to fig. 7, a first photo mask PM1 may be provided over the first insulating film 222. The first photo mask PM1 may be spaced apart from the first insulating film 222. The pattern PM1a of the first photomask PM1 may expose the first and third regions RG1 and RG3 of the lower protective layer 100. That is, the region exposed by the first photo mask PM1 may be a portion of the first insulating film 222, and is a region where the first conductive pattern 210 is located. The first photomask PM1 may include a Phase Shift Mask (PSM). For example, in the first photomask PM1, a chromium (Cr) pattern may be formed on a quartz substrate, and a phase shifter may be disposed between the quartz substrate and the chromium pattern. Accordingly, the resolution of the first photomask PM1 may be improved.

A portion of the first insulating film 222 may be removed to form a first insulating layer 220. In detail, a portion of the first insulating film 222 in the first region RG1 and the third region RG3 may be removed. For example, an exposure process may be performed on the first insulating film 222 using the first photomask PM 1. A portion 222a of the first insulating film 222 may be removed from the first region RG1 by an exposure process to expose the first conductive pattern 210. In addition, a portion 222b of the first insulating film 222 may be removed from the third region RG3 through an exposure process to form a first recess RS1 on the first insulating film 222. The first recess RS1 may have a shape recessed from the upper surface 220a of the first insulating film 222 on the second region RG2 toward the lower protection layer 100.

In this case, the depth of the first recess RS1 formed by removing the first insulating film 222 may be shallow in a region adjacent to the side surface 210b of the first conductive pattern 210 due to a variation or error of the exposure process. In detail, the depth to which the first insulating film 222 is removed may be shallower toward the first conductive pattern 210. Accordingly, the first side surface 220c of the first recess RS1 may be formed to be inclined with respect to the bottom surface 220b of the first recess RS1 and the side surface 210b of the first conductive pattern 210. In addition, the thickness of the first insulating film 222 increases toward the outside of the pattern PM1a of the first photomask PM1 (i.e., closer to the second region RG2) due to process variation or an error of the exposure process. The depth of removal may be shallow. Therefore, the first recess RS1 may not extend through the first insulating film 222. In some embodiments, the first recess RS1 may have the shape shown in fig. 7.

As described above, the first wiring layer 200 having the first insulating layer 220 and the first conductive pattern 210 may be formed on the lower protective layer 100.

In an example embodiment, an exposure process may be performed on the entire surface of the first insulating film 222. That is, an exposure process may be performed on the first insulating film 222 on the first, second, and third regions RG1, RG2, and RG 3. The first conductive pattern 210 may be exposed on the first region RG1 through an exposure process, and an upper surface of the first insulating film 222 formed on the second and third regions RG2 and RG3 may be lower than the upper surface 210a of the conductive pattern 210. In this case, a redistribution substrate according to the embodiment of fig. 5A to 5C may be formed.

When the first insulating film 222 is removed only from the first region RG1, the protruding portion of the first insulating film 222 may remain. As shown in fig. 8, a portion 222a ' of the first insulating film 222' on the first region RG1 may be removed using a first photo mask PM1' to expose the first conductive pattern 210. For example, the etching process may be performed on the first region RG1, and the etching process may not be performed on the second region RG2 and the third region RG 3.

Therefore, the portion 222b 'of the first insulating film 222' protruding upward on the third region RG3 can be left. The portion 222b 'of the protruding first insulating film 222' may have an uppermost end located at a higher level than the upper surface 210a of the first conductive pattern 210. In addition, the portion 222b ' of the first insulating film 222' may have the uppermost end located at a higher level than the upper surface of the first insulating film 222' on the second region RG 2. Accordingly, the first insulating film 222' may have a large step with the first conductive pattern 210. Accordingly, a cavity such as an air gap may be formed in a deposition process performed later, or impurities may be generated on the first insulating film 222' and the first conductive pattern 210, which may cause defects at the redistribution substrate.

According to example embodiments of the inventive concepts, the portion 222b 'of the first insulating film 222' may be removed. During the patterning process of the first insulating film 222', an exposure process may be performed on both the first region RG1 and the third region RG3, and the height of the upper surface of the first insulating film 222' may be equal to or lower than the first conductive pattern 210. That is, the step between the first conductive pattern 210 and the first insulating layer 220 may be small, and the occurrence of defects may be reduced during a subsequent deposition process described later.

A second wiring layer 300 including a second conductive pattern 310 and a second insulating layer 330 may be formed on the first wiring layer 200. The process of forming the second wiring layer 300 may be the same as or similar to the process of forming the first wiring layer 200.

Referring to fig. 9, the second conductive pattern 310 and the third conductive pattern 320 may be formed on the first wiring layer 200. For example, after forming a seed layer on the first wiring layer 200, a mask exposing a portion of the seed layer formed on the first conductive pattern 210 or the first insulating layer 220 may be formed. Thereafter, the second conductive pattern 310 may be formed by filling a conductive material in the pattern of the mask using a plating process or the like. For example, after a conductive film is formed on the first wiring layer 200, the third conductive pattern 320 may be formed by patterning the conductive film.

In this case, a conductive film may be formed to conformally cover the upper surface of the first insulating layer 220. Accordingly, the third conductive pattern 320 may be formed to extend from the first surface of the first conductive pattern 210 to the upper surface of the first insulating layer 220. In detail, the third conductive pattern 320 may be formed along the bottom surface of the first recess RS1 of the first insulating layer 220 on the third region RG 3. In this case, since the step difference between the first conductive pattern 210 and the first insulating layer 220 is small, when the conductive film is formed, for example, an air gap or an impurity may not be formed under the third conductive pattern 320 adjacent to the interface between the first conductive pattern 210 and the first insulating layer 220. The thickness of the third conductive pattern 320 may be less than that of the second conductive pattern 310. In some embodiments, the third conductive pattern 320 may directly contact surfaces of the first insulating layer 220 and the first recess RS1 and may have a uniform thickness along the surfaces of the first insulating layer 220 and the first recess RS1, as shown in fig. 9. As used herein, "step difference between element a and element B" (or similar language) may refer to a height difference between element a and element B.

The second insulating film 332 may be formed on the first wiring layer 200. For example, the second insulating film 332 may be formed by coating or depositing an insulating material on the first wiring layer 200. The coating process of the insulating material may include a spin coating process or a roll coating process. The insulating material may include a photosensitive insulating material. For example, the insulating material may include a Dry Film Resist (DFR) and/or a photoimageable dielectric (PID). In this case, the insulating material may fill the first recess RS1 of the first insulating layer 220. That is, the second insulating film 332 may be in contact with the top surface of the first insulating layer 220, the bottom surface and the side surfaces of the first recess RS 1.

At this time, since the step difference between the first conductive pattern 210 and the first insulating layer 220 is small, when an insulating material is applied, for example, an air gap or an impurity may not be formed under the second insulating film 332 adjacent to the interface between the first conductive pattern 210 and the first insulating layer 220. The second insulating film 332 may cover the second conductive pattern 310 and the third conductive pattern 320. The second insulating film 332 coated on the first wiring layer 200 and the second conductive pattern 310 may be elevated in a region adjacent to the second conductive pattern 310 due to the thickness of the second conductive pattern 310 located on the upper surface of the first wiring layer 200. The second insulating film 332 may protrude upward from the second conductive pattern 310.

Referring to fig. 10, a portion of the second insulating film 332 may be removed to form a second insulating layer 330. The process of forming the second insulating layer 330 may be the same as or similar to the process of forming the first insulating layer 220. For example, a second photomask PM2 may be provided over the second insulating film 332. The pattern PM2a of the second photomask PM2 may expose the second conductive pattern 310 and a portion of the second insulating film 332 adjacent to the second conductive pattern 310.

An exposure process may be performed on the second insulating film 332 using the second photomask PM 2. In detail, a portion 332a of the second insulating film 332 protruding upward on the second conductive pattern 310 may be removed. A portion 332a of the second insulating film 332 may be removed through an exposure process to expose the second conductive pattern 310. Further, a portion 332b of the second insulating film 332 adjacent to the second conductive pattern 310 may be removed through an exposure process to form the second recess RS2 on the second insulating film 332.

According to example embodiments of the inventive concepts, the protruding portion of the second insulating film 332 may be removed. During the patterning process of the second insulating film 332, an exposure process may be performed on both the second conductive pattern 310 and a region adjacent to the second conductive pattern 310, and the height of the upper surface of the second insulating film 332 may be equal to or lower than the top surface of the second conductive pattern 310. That is, the step difference between the second conductive pattern 310 and the second insulating layer 330 may be small, and the occurrence of defects may be reduced in a deposition process described later. As described above, the second wiring layer 300 including the second insulating layer 330, the second conductive pattern 310, and the third conductive pattern 320 may be formed on the first wiring layer 200.

Referring to fig. 11, an upper protection layer 400 may be formed on the second wiring layer 300. For example, the upper protective layer 400 may be formed by depositing or coating an insulating material on the second wiring layer 300. For example, the insulating material may include, but is not limited to, inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and/or polyamide-based polymer materials. In this case, the insulating material may fill the second recess RS2 of the second insulating layer 330. That is, the upper protection layer 400 may contact the upper surface of the second insulation layer 330, the bottom surface and the side surfaces of the second recess RS 2. In this case, since the step difference between the second conductive pattern 310 and the second insulating layer 330 is small, when the insulating material is applied, for example, an air gap or an impurity may not be formed under the upper protective layer 400 adjacent to the interface between the second conductive pattern 310 and the second insulating layer 330.

Referring back to fig. 1, 2A and 2B, the terminal pads 410 and the connection terminals 420 may be formed on the redistribution substrate 10. The terminal pad 410 may be formed on the upper protective layer 400. For example, the via hole may be formed by performing an etching process on the upper protection layer 400. The via hole may expose a top surface of the second conductive pattern 310. Thereafter, the terminal pad 410 may be formed by filling a conductive material in the via hole.

The connection terminal 420 may be provided on the terminal pad 410. The connection terminals 420 may include solder balls, solder bumps, and the like.

The semiconductor chip 20 may be mounted on the redistribution substrate 10. The semiconductor chip 20 may be mounted, for example, in a flip chip manner. For example, the semiconductor chip 20 may be mounted on the redistribution substrate 10 through the connection terminals 420.

The molding layer 30 may be formed on the redistribution substrate 10. For example, after a molding material is coated on the redistribution substrate 10 to cover the semiconductor chip 20, the molding material may be cured to form the molding layer 30.

In the method of manufacturing the semiconductor package according to the embodiment of the inventive concept, a step difference or a height difference between the first conductive pattern and the first insulating layer may be small, and the occurrence of defects may be reduced during a subsequent deposition process. Accordingly, the method of manufacturing a semiconductor package may manufacture a semiconductor package that is more reliable and includes fewer defects.

Various advantageous advantages and effects of the inventive concept are not limited to the above description. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, as would be apparent to one of ordinary skill in the art at the time of filing the present application, unless otherwise specifically noted. It will therefore be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the inventive concept as set forth in the appended claims.

This application claims priority to korean patent application No. 10-2019-0115311, filed by the korean patent office at 19.9.2019, the entire contents of which are incorporated herein by reference.