Semiconductor element and method for manufacturing the same
阅读说明:本技术 半导体元件及其制备方法 (Semiconductor element and method for manufacturing the same ) 是由 施江林 吴珮甄 张庆弘 丘世仰 于 2019-10-11 设计创作,主要内容包括:本公开提供一种半导体元件及其制备方法。该半导体元件具有一第一晶粒、一第二晶粒、一第一重新分布层、一第二重新分布层、一第一互连结构以及一第二互连结构。该第二晶粒叠置在该第一晶粒上,该第一重新分布层配置在该第一晶粒的一第一基底与该第二晶粒的一第二层间介电层之间,且该第二重新分布层配置在该第二晶粒的一第二基底上。该第一互连结构将该第一重新分布层连接到该第一晶粒的多个第一金属线的其中一个,且该第二互连结构将该第二重新分布层连接到在该第二层间介电层中的多个第二金属线的其中一个。(The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device has a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second interlayer dielectric layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of the first plurality of metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second plurality of metal lines in the second interlevel dielectric layer.)
1. A semiconductor component, comprising:
a first die including a first substrate, a first interlayer dielectric layer disposed on a front surface of the first substrate, and a plurality of first metal lines disposed in the first interlayer dielectric layer;
a second die overlying the first die and including a second substrate, a second interlayer dielectric layer disposed on a second front surface of the second substrate, and a plurality of second metal lines disposed in the second interlayer dielectric layer;
a first redistribution layer between the first substrate and the second interlayer dielectric layer;
a second redistribution layer disposed on the second substrate;
a first interconnect structure extending through the first substrate and through the first interlevel dielectric layer to connect the first redistribution layer to one of the first metal lines; and
a second interconnect structure extending through the second substrate and into the second interlevel dielectric layer to connect the second redistribution layer to one of the second metal lines.
2. The semiconductor device of claim 1, wherein the first redistribution layer is aligned with the first interconnect structure and offset from the second metal line when viewed in cross-section.
3. The semiconductor device of claim 1, wherein the second metal line fully connected to the first redistribution layer exposes the second interlayer dielectric layer.
4. The semiconductor device of claim 1, further comprising at least one solder bump electrically connected to the second redistribution layer.
5. The semiconductor device of claim 4, further comprising at least one under bump metallization layer interposed between the solder bumps and the second redistribution layer.
6. The semiconductor device of claim 1, further comprising a carrier bonded to the first die by a bonding layer.
7. The semiconductor device of claim 6, wherein the bonding layer comprises a native dielectric film grown on the carrier and a deposited dielectric layer on the first interlayer dielectric layer.
8. The semiconductor device of claim 6, wherein the first redistribution layer has a first thickness and the second redistribution layer has a second thickness, the second thickness being less than the first thickness.
9. A method for fabricating a semiconductor device comprises
Providing a first die comprising a first substrate, a first interlayer dielectric layer disposed on a first front surface of the first substrate, and a plurality of first metal lines disposed in the interlayer dielectric layer;
forming a first interconnect structure through the first substrate, through the first interlayer dielectric layer, and contacting one of the first metal lines;
forming a first redistribution layer completely connecting the first interconnect structure;
providing a second die comprising a second substrate, a second interlayer dielectric layer disposed on a second front surface of the second substrate, and a plurality of second metal lines in the second interlayer dielectric layer;
forming a second redistribution layer to completely connect one of the second metal lines;
stacking the second die on the first die and completely connecting the first redistribution layer to the second redistribution layer;
forming a second interconnect structure through the second substrate, through the second interlayer dielectric layer, and contacting one of the second conductive lines; and
a second redistribution layer is formed on the second substrate and completely connects the second interconnect structure.
10. The method of claim 9, wherein the first redistribution layer and the second redistribution layer have an identical pattern.
11. The method of claim 9, further comprising:
a dielectric layer is formed surrounding the first redistribution layer and the second redistribution layer.
12. The method of claim 9, further comprising:
providing a carrier;
forming a dielectric film on the first interlayer dielectric layer; and
bonding the first crystal grain and the carrier through the dielectric film.
13. The method of claim 12, further comprising performing a grinding process to thin the carrier after the second redistribution layer is formed.
14. The method of claim 9, wherein the forming of the first interconnect structure comprises:
forming at least one first opening to expose the first metal line; and
depositing a first conductive material in the first opening;
wherein the forming of the second interconnect structure comprises:
forming at least one second opening to expose the second metal line; and
depositing a second conductive material in the second opening.
15. The method of claim 14, further comprising:
depositing a first barrier layer on the first substrate and in the first opening prior to depositing the first conductive material;
performing a first planarization process after the first conductive material is deposited to remove portions of the first barrier layer and the first conductive material, thereby exposing the first substrate;
depositing a second barrier layer on the second substrate and in the second opening prior to depositing the second conductive material; and
after the second conductive material is deposited, a second planarization process is performed to remove portions of the second barrier layer and the second conductive material, thereby exposing the second substrate.
16. The method of claim 9, further comprising:
performing a first thinning process to thin the first substrate before the first interconnect structure is formed; and
a second thinning process is performed to thin the second substrate before the second interconnect structure is formed.
Technical Field
The present application claims priority and benefits of U.S. official application No. 16/401,587 of the 2019/05/02 application, the contents of which are incorporated herein by reference in their entirety.
The present disclosure relates to a semiconductor device and a method for manufacturing the same. In particular to a stacked die device and a method of making the same.
Background
As integrated circuit technology continues to advance, there is a continuing effort to improve performance and density, improve form factor (form factor), and reduce cost. One approach to achieving such advantages, which has been explored by many designers, is implemented by stacked three-dimensional (3D) integrated circuits. It is desirable to consider regions of a three-dimensional integrated circuit that have a stack of two or more wafers that are fabricated using different fabrication processes (fabrication processes) or that are electrically stacked using the same fabrication process to reduce the footprint of the integrated circuit device (footprint).
The above description of "prior art" is merely provided as background, and is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is prior art to the present disclosure.
Disclosure of Invention
An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first die (first die), a second die, a first redistribution layer (first redistribution layer), a second redistribution layer, a first interconnect structure (first interconnect structure), and a second interconnect structure. The first die includes a first substrate, a first interlayer dielectric (ILD) layer disposed on a front surface of the first substrate, and a plurality of first metal lines disposed in the first ILD layer. The second die is stacked on the first die and includes a second substrate, a second interlayer dielectric layer disposed on a second front surface of the second substrate, and a plurality of second metal lines disposed in the second interlayer dielectric layer. The first redistribution layer is between the first substrate and the second interlayer dielectric layer. The second redistribution layer is disposed on the second substrate. The first interconnect structure penetrates through the first substrate and penetrates through the first interlayer dielectric layer to connect the first redistribution layer to one of the first metal lines. The second interconnect structure penetrates through the second substrate and into the second interlayer dielectric layer to connect the second redistribution layer to one of the second metal lines.
According to some embodiments of the present disclosure, the first redistribution layer is aligned with the first interconnect structure and offset from the second metal line when viewed in a cross-sectional view.
According to some embodiments of the present disclosure, the second metal line completely connected to the first redistribution layer exposes the second interlayer dielectric layer.
According to some embodiments of the present disclosure, the semiconductor device further includes at least one solder bump (solder bump) electrically connected to the second redistribution layer.
According to some embodiments of the present disclosure, the semiconductor device further includes at least one Under Bump Metallization (UBM) interposed between the solder bumps and the second redistribution layer.
According to some embodiments of the present disclosure, the semiconductor device further includes a carrier (carrier) bonded to the first die by a bonding layer.
According to some embodiments of the present disclosure, the bonding layer includes a native dielectric film (native dielectric film) grown on the support and a deposited dielectric layer (deposited dielectric layer) on the first interlayer dielectric layer.
According to some embodiments of the disclosure, the first redistribution layer has a first thickness and the second redistribution layer has a second thickness, the second thickness being less than the first thickness.
Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method comprises the following steps: providing a first die comprising a first substrate, a first interlayer dielectric layer disposed on a first front surface of the first substrate, and a plurality of first metal lines disposed in the interlayer dielectric layer; forming a first interconnect structure through the first substrate, through the first interlayer dielectric layer, and contacting one of the first metal lines; forming a first re-routing layer (re-routing layer) completely connecting the first interconnect structure; providing a second die comprising a second substrate, a second interlayer dielectric layer disposed on a second front surface of the second substrate, and a plurality of second metal lines in the second interlayer dielectric layer; forming a second redistribution layer to completely connect one of the second metal lines; stacking the second die on the first die and completely connecting the first redistribution layer to the second redistribution layer; forming a second interconnect structure through the second substrate, through the second interlayer dielectric layer, and contacting one of the second conductive lines; and forming a second redistribution layer on the second substrate and fully connecting the second interconnect structure.
According to some embodiments of the present disclosure, the first redistribution layer. The second redistribution layer has a pattern identical to that of the first redistribution layer.
According to some embodiments of the present disclosure, the method further includes forming a dielectric layer surrounding the first redistribution layer and the second redistribution layer.
According to some embodiments of the disclosure, the method of preparing further comprises: providing a carrier; forming a dielectric film (dielectric film) on the first interlayer dielectric layer; and bonding the first crystal grain and the carrier through the dielectric film.
According to some embodiments of the present disclosure, the manufacturing method further includes performing a grinding process after the second redistribution layer is formed to thin the carrier.
According to some embodiments of the present disclosure, the forming of the first interconnect structure includes: forming at least one first opening to expose the first metal line; and depositing a first conductive material in the first opening; wherein the forming of the second interconnect structure comprises: forming at least one second opening to expose the second metal line; and depositing a second conductive material in the second opening.
According to some embodiments of the disclosure, the method of preparing further comprises: depositing a first barrier layer (first barrier layer) on the first substrate and in the first opening prior to depositing the first conductive material; performing a first planarization process after the first conductive material is deposited to remove portions of the first barrier layer and the first conductive material, thereby exposing the first substrate; depositing a second barrier layer on the second substrate and in the second opening prior to depositing the second conductive material; and performing a second planarization process after the second conductive material is deposited to remove portions of the second barrier layer and the second conductive material, thereby exposing the second substrate.
According to some embodiments of the disclosure, the method of preparing further comprises: performing a first thinning process (first thinning process) to thin the first substrate before the first interconnect structure is formed; and performing a second thinning process to thin the second substrate before the second interconnect structure is formed.
The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
Drawings
The disclosure may be more completely understood in consideration of the following detailed description and the appended claims, in connection with the accompanying drawings, in which like reference numerals refer to like elements.
Fig. 1 is a schematic cross-sectional view of a semiconductor system according to some embodiments of the present disclosure.
Fig. 2 is a schematic cross-sectional view of a semiconductor system according to some embodiments of the present disclosure.
Fig. 3 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure.
Fig. 4-25 are schematic cross-sectional views of intermediate stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.
Wherein the reference numerals are as follows:
10 semiconductor system
10A semiconductor system
12 mainboard
14 semiconductor element
14A semiconductor element
20a first die
20b second die
20c third grain
20d fourth crystal grain
30 vector
32 bonding layer
34 first redistribution layer
36 second redistribution layer
38 dielectric material
40 solder bump
42 underbump metallization layer
50 preparation method
122 support assembly
124 wiring pad
142 depositing a dielectric film
210a first substrate
210b second substrate
210c third substrate
210d fourth substrate
212a front surface
212b second front surface
214a first rear surface
214b second rear surface
220a first interlayer dielectric layer
220b second interlayer dielectric layer
220c third interlayer dielectric layer
220d fourth interlayer dielectric layer
222b top surface
230a first metal line
230b second metal line
230c third metal line
230d fourth Metal line
232b top surface
240a first interconnect structure
240b second interconnect structure
240c third interconnect Structure
250a first barrier layer
250b second barrier layer
260a first opening
270a first conductive material
270b second conductive material
280a first precursor layer
280b second precursor layer
282a first rewiring layer
282b second rewiring layer
284a first dielectric layer
284b second dielectric layer
290b second opening
300 third precursor layer
301 surface
302 native dielectric film
362 Top surface
382 top surface
502 step
504 step
Step 506
508 step
Step 510
512 step
514 step
516 step
518 step
520 step
522 step
Step 524
526 step
528 step
530 step
532 step
534 step
536 step
538 step
540 step
542 step
544 step
546 step
548 step
610 first photoresist pattern
620 first mask
630 second photoresist pattern
640 second mask
1222 surface of
2822a top surface
2822b Top surface
2842a top surface
2842b Top surface
C center shaft
T1 first thickness
T2 second thickness
T3 thickness
T4 thickness
T5 thickness
T6 thickness
T7 thickness
T8 thickness
Detailed Description
The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.
References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The present disclosure is directed to a semiconductor device and a method of fabricating the same. The following description is provided to provide detailed steps and structures for a thorough understanding of the present disclosure. It is apparent that the implementation of the disclosure does not limit the specific details known to a person with ordinary skill in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be practiced in other embodiments, which depart from the specific details. The scope of the present disclosure is not limited by the detailed description but is defined by the claims.
Fig. 1 is a schematic cross-sectional view of a semiconductor system 10 in accordance with some embodiments of the present disclosure. Referring to fig. 1, a semiconductor system 10 includes a main board (main board)12 and a semiconductor device 14, the semiconductor device 14 is mounted on and electrically connected to the main board 12, wherein the semiconductor device 14 includes a
In some embodiments, the motherboard 12 may be a circuit board (circuit board) or a motherboard (thermal board) of an electronic system (electronic system), such as a computer system (computer). In some embodiments, the motherboard 12 has a support member (support member)122 and a plurality of wiring pads (wiring pads)124, the wiring pads 124 being disposed on a surface 1222 of the support member 122. In some embodiments, the support member 122 may be made of a dielectric material, such as bismaleimide-triazine (BT) resin or FR4 (composed of woven fiberglass cloth and fire-retardant epoxy resin adhesive)/glass; the wiring pads 123 may be gold-plated conductors, copper-plated conductors, or aluminum-plated conductors.
In some embodiments, the semiconductor device 14 further includes a
In some embodiments, the
The
In some embodiments, a first
In some embodiments, the
In some embodiments, the semiconductor device 14 further includes at least one first interconnection structure (first interconnection structure)240a, and the
In some embodiments, the semiconductor device 14 may further include a
The
In some embodiments, the semiconductor component 14 further includes at least one
A
In some embodiments, the semiconductor element 14 may further include a second redistribution layer 36, the second redistribution layer 36 being connected to the
In some embodiments, the semiconductor device 14 may further include a
The semiconductor device 14 may further include at least one solder bump (solder bump)40, wherein the solder bump 40 is electrically connected to the second redistribution layer 36. In some embodiments, the solder bumps 40 fully connected to the wiring pads 124 are used as input/output (I/O) connections to electrically connect the semiconductor device 14 to the motherboard 12. In some embodiments, the solder bump 40 is located at a position corresponding to the wire pad 124 so as to be completely and electrically connected. In some embodiments, the semiconductor device 14 may further include at least one Under Bump Metallization (UBM)42, the UBM 42 being interposed between the second redistribution layer 36 and the solder bumps 40. In some embodiments, the underbump metallization layer 42 comprises aluminum.
Fig. 2 is a schematic cross-sectional view of a semiconductor system 10A in accordance with some embodiments of the present disclosure. Referring to fig. 2, a semiconductor system 10A has a motherboard 12 and a semiconductor device 14A, the semiconductor device 14A is mounted on the motherboard 12 and has first to fourth dies 20A-20 d vertically stacked in a front-to-back configuration. Specifically, the third die 20c is stacked on the fourth die 20d, the
In some embodiments, the semiconductor device 14A further includes a plurality of first redistribution layers 34, and the first redistribution layers 34 are disposed between two
In some embodiments, the semiconductor device 14A further includes a second redistribution layer 36, the second redistribution layer 36 completely connecting the at least one fourth metal line 230d of the fourth die 240d to the one or more Under Bump Metallization (UBM) 42. In some embodiments, the semiconductor device 14A further includes one or more solder bumps 40, the solder bumps 40 being disposed on an Under Bump Metallization (UBM)42 connected to the second redistribution layer 36. In some embodiments, a
Fig. 3 is a flow chart illustrating a method of fabricating a semiconductor device 14 according to some embodiments of the present disclosure. Fig. 4-25 are schematic cross-sectional views of intermediate stages of a method 50 of fabricating a semiconductor device 14 according to some embodiments of the present disclosure. The stages shown in fig. 4-25 are also drawn schematically in the flow chart of fig. 3. In the following discussion, the stages of fabrication illustrated in fig. 4-25 are discussed with reference to the process steps illustrated in fig. 3.
Referring to fig. 4, a
In some embodiments, a
Referring to fig. 5, in some embodiments,
Referring to fig. 6, in some embodiments, a first thinning process is performed to thin the
Referring to fig. 7 and 8, in some embodiments, one or more first openings 260a are formed to expose at least one of the
In some embodiments, portions of the first
Referring to fig. 9, in some embodiments, a first barrier layer (first barrier layer)250a is selectively deposited on the
Referring to fig. 10, in some embodiments, a first conductive material 270a is deposited on the
Referring to fig. 11, in some embodiments, a first planarization process is performed to expose the
Referring to fig. 12, in some embodiments, according to a step 516 in fig. 3, a first precursor layer (first precursor layer)280a is deposited to cover the
Next, a
Referring to fig. 13, in some embodiments, according to a step 518 in fig. 3, a first patterning process is performed to etch the
Referring to fig. 14, in some embodiments, according to a step 520 in fig. 3, a
Referring to fig. 15, in some embodiments, a
Next, a
Further, a
Referring to fig. 16, in some embodiments, a second patterning process is performed to etch the
Referring again to fig. 16, in some embodiments, a
Referring to fig. 17, in some embodiments, the
Referring to fig. 18, in some embodiments, a second thinning process is performed to thin the
Referring to fig. 19, in some embodiments, one or more
Referring to fig. 20, in some embodiments, a
Next, according to step 536 of fig. 3, a second
Referring to fig. 21, in some embodiments, a second planarization process is performed to expose the
Referring to fig. 22, in some embodiments, a third precursor layer 300 is deposited on the
Next, as shown in fig. 23, a
Referring again to fig. 23, in some embodiments, a third patterning process is performed to etch the third precursor layer 300 through the
Next, according to a step 544 in fig. 3, a
Referring to fig. 24, in some embodiments, one or more Under Bump Metallization (UBM)42 are formed on second redistribution layer 36 and one or more solder bumps 40 are disposed on Under Bump Metallization (UBM)42, in accordance with a step 546 in fig. 3. In some embodiments, the solder bumps 40 are mounted by initially placing a solder flux (not shown) on the Under Bump Metallization (UBM) 42. Soldering fluxes generally have an acidic component (acid component) that removes oxide barriers (oxide barriers) and an adhesion (adhesive quality) that helps prevent movement during processing. Once the solder bumps 40 contact the solder flux, a reflow (reflow) is performed to reflow the solder bumps 40 with the material of the solder flux to fully bond the solder bumps 40 to the Under Bump Metallization (UBM) 42.
Referring to fig. 25, in some embodiments, a grinding process is performed to thin the
An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The first die includes a first substrate, a first interlayer dielectric layer disposed on a front surface of the first substrate, and a plurality of first metal lines disposed in the first interlayer dielectric layer. The second die is stacked on the first die and includes a second substrate, a second interlayer dielectric layer disposed on a second front surface of the second substrate, and a plurality of second metal lines disposed in the second interlayer dielectric layer. The first redistribution layer is between the first substrate and the second interlayer dielectric layer. The second redistribution layer is disposed on the second substrate. The first interconnect structure penetrates through the first substrate and penetrates through the first interlayer dielectric layer to connect the first redistribution layer to one of the first metal lines. The second interconnect structure penetrates through the second substrate and into the second interlayer dielectric layer to connect the second redistribution layer to one of the second metal lines.
Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method comprises the following steps: providing a first die comprising a first substrate, a first interlayer dielectric layer disposed on a first front surface of the first substrate, and a plurality of first metal lines disposed in the interlayer dielectric layer; forming a first interconnect structure through the first substrate, through the first interlayer dielectric layer, and contacting one of the first metal lines; forming a first re-routing layer (re-routing layer) completely connecting the first interconnect structure; providing a second die comprising a second substrate, a second interlayer dielectric layer disposed on a second front surface of the second substrate, and a plurality of second metal lines in the second interlayer dielectric layer; forming a second redistribution layer to completely connect one of the second metal lines; stacking the second die on the first die and completely connecting the first redistribution layer to the second redistribution layer; forming a second interconnect structure through the second substrate, through the second interlayer dielectric layer, and contacting one of the second conductive lines; and forming a second redistribution layer on the second substrate and fully connecting the second interconnect structure.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included within the scope of the present application.
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