阅读说明：本技术 覆晶封装基板及其制法 (Flip chip package substrate and method for fabricating the same ) 是由 陈文彰 许诗滨 胡竹青 于 2020-04-24 设计创作，主要内容包括：本发明公开了一种覆晶封装基板及一种制作覆晶封装基板的方法,覆晶封装基板包括：一第一导电线路及一第一导电通道,设于一第一介电材料层内,其中该第一导电通道呈柱状设于该第一导电线路上,且该第一导电通道的顶面及底面皆未被该第一介电材料层覆盖,且一保护层设于该第一导电线路的底面；一第二介电材料层,设于该第一介电材料层上；一第二导电线路、一第二导电通道及一导电垫片,设于该第二介电材料层内,其中该第二导电线路设于该第一导电通道的顶面上,该第二导电通道呈柱状设于该第二导电线路上,该导电垫片设于该第二导电通道上,且该导电垫片的顶面未被该第二介电材料层覆盖；以及一镍钯金层,电镀形成设于该导电垫片的顶面上。(The invention discloses a flip chip package substrate and a method for manufacturing the same, the flip chip package substrate comprises: a first conductive circuit and a first conductive channel disposed in a first dielectric material layer, wherein the first conductive channel is disposed on the first conductive circuit in a columnar shape, and the top and bottom surfaces of the first conductive channel are not covered by the first dielectric material layer, and a protective layer is disposed on the bottom surface of the first conductive circuit; a second dielectric material layer disposed on the first dielectric material layer; a second conductive trace, a second conductive channel and a conductive pad disposed in the second dielectric material layer, wherein the second conductive trace is disposed on the top surface of the first conductive channel, the second conductive channel is disposed on the second conductive trace in a columnar shape, the conductive pad is disposed on the second conductive channel, and the top surface of the conductive pad is not covered by the second dielectric material layer; and a nickel-palladium gold layer formed on the top surface of the conductive pad by electroplating.)

1. A flip chip package substrate, comprising:

a first conductive circuit and a first conductive channel disposed in a first dielectric material layer, wherein the first conductive channel is disposed on the first conductive circuit in a columnar shape, the top surface of the first conductive channel and the bottom surface of the first conductive circuit are both not covered by the first dielectric material layer, and a protective layer is disposed on the bottom surface of the first conductive circuit;

a second dielectric material layer disposed on the first dielectric material layer;

a second conductive trace, a second conductive channel and a conductive pad disposed in the second dielectric material layer, wherein the second conductive trace is disposed on the top surface of the first conductive channel and electrically connected to each other, the second conductive channel is disposed on the second conductive trace in a columnar shape, the conductive pad is disposed on the second conductive channel, and the top surface of the conductive pad is not covered by the second dielectric material layer; and

and a nickel-palladium gold layer formed on the top surface of the conductive pad by electroplating.

2. The substrate for flip chip package of claim 1, wherein the protective layer is formed without sulfide, and the protective layer is formed by performing an oxidation resistant treatment on the bottom surface of the first conductive traces.

3. The substrate for flip chip package of claim 2, wherein the thickness of the passivation layer is not greater than 60 nm.

4. The substrate according to claim 1, wherein the thickness of the NiPd layer is no greater than 20 nm.

5. The substrate for flip chip package of claim 1, wherein the passivation layer on the bottom surface of the first conductive traces is removed, a circuit chip is flip chip mounted on a portion of the bottom surface of the first conductive traces, and a third dielectric material layer covers the circuit chip and the bottom surfaces of the other first conductive traces.

6. A method for fabricating a flip chip package substrate, comprising:

(A) providing a bearing plate;

(B) forming a first conductive circuit, a first conductive channel and a first dielectric material layer on the bearing plate, wherein the first conductive circuit is formed on the bearing plate, the first conductive channel is formed on the first conductive circuit in a columnar shape, the first dielectric material layer covers the first conductive circuit and the first conductive channel, and then the first dielectric material layer is partially removed to expose the top surface of the first conductive channel;

(C) forming a second conductive circuit, a second conductive channel, a conductive pad and a second dielectric material layer on the first dielectric material layer, wherein the second conductive circuit is formed on the top surface of the first conductive channel and is directly and electrically connected with each other, the second conductive channel is formed on the second conductive circuit in a columnar shape, the conductive pad is formed on the second conductive channel, the second dielectric material layer covers the second conductive circuit, the second conductive channel and the conductive pad, and then the second dielectric material layer is partially removed to expose the top surface of the conductive pad;

(D) forming a nickel-palladium gold layer on the top surface of the conductive gasket by using an electroplating technology; and

(E) and removing the bearing plate, and forming a protective layer on the bottom surface of the first conductive circuit through anti-oxidation treatment.

7. The method of claim 6, wherein the passivation layer is free of sulfides.

8. The method of claim 7, wherein the passivation layer has a thickness of no more than 60 nm.

9. The method of claim 6, wherein the thickness of the NiPd layer is no greater than 20 nm.

10. The method of fabricating a flip chip package substrate of claim 6, further comprising:

(F1) baking to remove the protective layer on the bottom surface of the first conductive circuit;

(F2) flip-chip mounting a circuit chip on the bottom surface of part of the first conductive circuit; and

(F3) a third dielectric material layer is formed to cover the circuit chip and the bottom surfaces of the other first conductive traces.

11. The method of fabricating a flip chip package substrate of claim 6, further comprising:

(G) forming a solder ball on the Ni-Pd layer on the top surface of the conductive pad.

Technical Field

The present invention relates to a flip chip package substrate and a method for fabricating the same, and more particularly, to a flip chip package substrate suitable for an integrated circuit with high speed operation and a method for fabricating the same.

Background

The new generation of electronic products not only pursues light, thin, short and small high density, but also has a trend towards high-speed operation development; therefore, Integrated Circuit (IC) technology and back-end chip packaging technology have been developed to meet the requirements of high-speed operation IC for heat dissipation capability and Circuit impedance.

Due to poor matching of the interlayer material (mis-match), the conventional flip chip package substrate often suffers from severe Warpage (warp). In order to prevent or improve the warpage problem, the prior art uses either a Carrier plate (Carrier) or a package substrate with a thicker structure, or a package substrate 10 with multiple layers of wires 12 as shown in fig. 1, wherein the upper and lower surfaces of the multiple layers of wires 12 are surface-treated by chemical deposition of metal layers, and the outermost layer of the package substrate 10 is covered and protected by a solder mask 14 (also known as "green paint"); however, the above methods all cause the quality problems of the package substrate, such as extra manufacturing cost and poor heat dissipation effect. In addition, there are also the defects that the prior art adopts an Expanded polypropylene (EPP) structure with glass fiber (glass fiber) and polypropylene (PP) and uses a double-sided symmetrical solder mask to prevent the warpage of the board, but the polypropylene (PP) causes the packaging substrate process to need expensive laser drilling processing, which is likely to bring about particle impurities to reduce the qualification rate of the packaging substrate finished product, and the solder mask layer is likely to absorb water, increase the cost, reduce the reliability, and be prone to peeling off after packaging. Therefore, there is a need to develop new package substrate technologies to solve and improve the above problems.

Disclosure of Invention

An embodiment of the invention provides a flip chip package substrate, which includes: a first conductive circuit and a first conductive channel disposed in a first dielectric material layer, wherein the first conductive channel is disposed on the first conductive circuit in a columnar shape, and the top and bottom surfaces of the first conductive channel are not covered by the first dielectric material layer, and a protective layer is disposed on the bottom surface of the first conductive circuit; a second dielectric material layer disposed on the first dielectric material layer; a second conductive trace, a second conductive channel and a conductive pad disposed in the second dielectric material layer, wherein the second conductive trace is disposed on the top surface of the first conductive channel, the second conductive channel is disposed on the second conductive trace in a columnar shape, the conductive pad is disposed on the second conductive channel, and the top surface of the conductive pad is not covered by the second dielectric material layer; and a nickel-palladium gold layer formed on the top surface of the conductive pad by electroplating.

In one embodiment, the passivation layer is formed without sulfide, and the bottom surface of the first conductive line is treated with an Anti-oxidation (Anti-Tarnish) process.

In one embodiment, the thickness of the protective layer is not greater than 60 nm.

In one embodiment, the thickness of the nickel palladium gold layer is not greater than 20 nm.

In one embodiment, the passivation layer on the bottom surface of the first conductive trace is removed, a circuit chip is flip-chip mounted on a portion of the bottom surface of the first conductive trace, and a third dielectric material layer covers the circuit chip and the bottom surfaces of the other first conductive traces.

Another embodiment of the present invention provides a method for fabricating a flip chip package substrate, which includes: providing a bearing plate; forming a first conductive circuit, a first conductive channel and a first dielectric material layer on the bearing plate, wherein the first conductive circuit is formed on the bearing plate, the first conductive channel is formed on the first conductive circuit in a columnar shape, the first dielectric material layer covers the first conductive circuit and the first conductive channel, and then the first dielectric material layer is partially removed to expose the top surface of the first conductive channel; forming a second conductive circuit, a second conductive channel, a conductive pad and a second dielectric material layer on the first dielectric material layer, wherein the second conductive circuit is formed on the top surface of the first conductive channel, the second conductive channel is formed on the second conductive circuit in a columnar shape, the conductive pad is formed on the second conductive channel, the second dielectric material layer covers the second conductive circuit, the second conductive channel and the conductive pad, and then the second dielectric material layer is partially removed to expose the top surface of the conductive pad; forming a nickel-palladium gold layer on the top surface of the conductive gasket by using an electroplating technology; and removing the bearing plate, and forming a protective layer on the bottom surface of the first conductive circuit through Anti-oxidation (Anti-Tarnish) treatment.

In one embodiment, the protective layer is formed by applying an oxidation resistant treatment to the bottom surface of the first conductive line.

In one embodiment, the thickness of the protective layer is not greater than 60 nm.

In one embodiment, the thickness of the nickel palladium gold layer is not greater than 20 nm.

In one embodiment, the method further comprises: and baking at high temperature to remove the protective layer, placing a circuit chip under the first dielectric material layer in a flip-chip manner, so that the pins of the circuit chip are directly connected with the exposed bottom surface of the first conductive circuit, and forming a third dielectric material layer under the first dielectric layer to coat the circuit chip.

In one embodiment, the method further comprises: forming a solder ball on the Ni-Pd layer on the top surface of the conductive pad.

Drawings

Fig. 1 is a cross-sectional view of a package substrate according to the related art.

Fig. 2 is a cross-sectional structure diagram of a flip chip package substrate according to a first embodiment of the invention.

Fig. 3 is a cross-sectional view of a semiconductor flip-chip package according to a second embodiment of the invention.

Fig. 4 to 7 are cross-sectional views of the flip chip package substrate according to the first embodiment.

Description of reference numerals: 10-a package substrate; 12-a multilayer wire; 14-a solder mask layer; 100-flip chip package substrate; 110-a carrier plate; 115-protective adhesive film; 120-a first layer of dielectric material; 122-first conductive traces; 124-a first conductive path; 130-a second layer of dielectric material; 132-a second conductive trace; 134-a second conductive path; 136-a conductive gasket; 140-nickel palladium gold layer; 150-a protective layer; 160-circuit chip; 162-pin; 200-semiconductor flip chip package.

Detailed Description

In order to further understand and appreciate the features, objects, and functions of the present invention, embodiments of the present invention are described in detail below with reference to the drawings. The same element numbers will be used throughout the description and drawings to refer to the same or like elements.

In the description of the various embodiments, when an element is described as being "above/on" or "below/under" another element, it is referred to the case where it is directly or indirectly on or under the other element, which may include the other element disposed therebetween; by "directly" is meant that no other intervening elements are disposed therebetween. The description of "above/up" or "below/under" etc. is described with reference to the drawings, but also includes other possible directional transitions. The terms first, second, and third are used to describe various elements, which are not limited by such terms. For convenience and clarity of illustration, the thickness or size of each element in the drawings is exaggerated, omitted, or schematically shown, and the size of each element is not completely the actual size thereof.

Fig. 2 is a cross-sectional structure diagram of a flip-chip package substrate 100 according to a first embodiment of the invention, the flip-chip package substrate 100 includes a first dielectric material layer 120, a second dielectric material layer 130, a nickel-palladium-gold layer 140 and a protection layer 150. Wherein the first dielectric material layer 120 includes a first conductive trace 122 and a first conductive via 124 disposed therein, the first conductive via 124 is disposed on the first conductive trace 122, and a top surface of the first conductive via 124 and a bottom surface of the first conductive trace 120 are both uncovered by the first dielectric material layer 120; the second dielectric material layer 130 is disposed on the first dielectric material layer 120, and includes a second conductive trace 132, a second conductive via 134 and a conductive pad 136 disposed therein, wherein the second conductive trace 132 is disposed on the first conductive via 124 and directly electrically connected thereto, the second conductive via 134 is disposed on the second conductive trace 132, the conductive pad 136 is disposed on the second conductive via 134, and a top surface of the conductive pad 136 is not covered by the second dielectric material layer 130; the ni-pd layer 140 is formed on the top surface of the conductive pad 136 by electroplating and is not covered by the second dielectric material layer 130; the passivation layer 150 is disposed under the bottom surface of the first conductive traces 122 and is not covered by the first dielectric material layer 120.

Fig. 3 is a cross-sectional view of a semiconductor flip-chip package 200 according to a second embodiment of the invention. The semiconductor flip chip package 200 is based on the flip chip package substrate 100 of the first embodiment, the flip chip package substrate 100 is baked at a high temperature to remove the passivation layer 150 on the bottom surface of the first conductive trace 122, a circuit chip 160 is mounted on the bottom surface of the first conductive trace 122 in a flip chip manner, so that the leads 162 of the circuit chip 160 are directly connected to the first conductive trace 122, and the circuit chip 160 and the flip chip package substrate 100 are entirely packaged into the semiconductor flip chip package 200 by a third dielectric material layer 170, as shown in fig. 3. The above-mentioned "direct connection" is advantageous for the circuit chip 160 to dissipate heat through the flip chip package substrate 100 and reduce the line impedance of the external connection of the circuit chip 160.

The flip chip package substrate 100 and the flip chip semiconductor package 200 of the above embodiments are mainly applied to the packaging of high speed computing integrated circuits, and therefore it is necessary to satisfy the requirements of the high speed computing integrated circuits for heat dissipation capability and circuit impedance. To improve the heat dissipation capability and reduce the line impedance of the flip chip package substrate 100, first, the first conductive vias 124 and the second conductive vias 134 may be metal pillars, such as copper pillars, and the cross-sectional shape thereof may be circular or any other shape, and the cross-sectional area thereof is increased as much as possible within a reasonable range.

Second, the first conductive traces 122 and the second conductive traces 132 can be increased in thickness as much as possible within a reasonable range, such as not less than 30 μm, which can be achieved by using a high current electroplating technique to avoid the disadvantage of poor uniformity caused by too long electroplating time required by a common electroplating technique.

Third, the passivation layer 150 is a thin layer formed on the bottom surface of the first conductive traces 122 by an Anti-Tarnish (e.g., immersion) process, and has a thickness of no greater than 60nm, and the composition thereof does not include sulfide. The thickness of the passivation layer 150 is very thin, and before the subsequent circuit chip 160 is disposed on the first conductive trace 122, the flip chip package substrate 100 is baked at a high temperature, so that the passivation layer 150 is removed, and the pins 162 of the circuit chip 160 are directly connected to the first conductive trace 122, as shown in fig. 3, so that the "direct connection" is beneficial to dissipating heat of the circuit chip 160 through the flip chip package substrate 100, and reducing the line impedance of the circuit chip 160 connected to the outside. In addition, the passivation layer 150 that can be removed by baking replaces the Solder mask 14 (or so-called "green paint", as shown in fig. 1) used in the prior art, such a structure characteristic makes the first dielectric material layer 120 and the third dielectric material layer 170 not isolated by the Solder mask 14, so that the heat can be conducted and dissipated quickly, and the problems of Warpage (warp) and poor heat dissipation effect caused by the conventional Solder mask 14 can be effectively improved.

In addition, through the conductive path formed by the carrier plate 110, the first conductive trace 122, the first conductive trace 124, the second conductive trace 132, the second conductive trace 134 and the conductive pad 136, the ni-pd layer 140 with a thickness not greater than 20nm can be formed on the top surface of the conductive pad 136 by electroplating through a low-cost electroplating process, and the surface roughness of the ni-pd layer 140 can also be controlled by electroplating to protect the top surface of the conductive pad 136 and strengthen the subsequent bonding interface with the solder ball, so that the ni-pd layer 140 is not required to be formed by using a Non-Plating Line (NPL) with poor reliability and high cost, and the manufacturing cost can be greatly reduced in addition to greatly improving the quality of the ni-pd layer 140.

The method and process for fabricating the flip chip package substrate 100 according to the first embodiment of the invention will be described. Referring to fig. 4-7, fig. 2 and fig. 3, cross-sectional views of the structure corresponding to the processing steps of the flip-chip package substrate 100 according to the first embodiment and the flip-chip semiconductor package 200 according to the second embodiment are shown.

First, as shown in fig. 4, a carrier plate 110 is provided, which is a metal substrate or a dielectric substrate plated with a metal layer on the surface thereof, for carrying or supporting the subsequent processes of the flip chip package substrate 100, such as the fabrication of the conductive traces of the flip chip package substrate 100. The metal component of the substrate includes iron (Fe), copper (Cu), nickel (Ni), tin (Sn), aluminum (Al), nickel/gold (Ni/Au), and a combination or alloy thereof, but the present invention is not limited thereto. Then, a Build-up Process (e.g., Semi-additive) is performed to fabricate the first conductive traces 122 and the first conductive vias 124 on the carrier substrate 110 by an electroplating technique; the first conductive via 124 is a metal pillar (e.g., a copper pillar) having a cross-sectional shape of a circle or any other shape, and the first conductive line 122 is formed by high current plating to have a thickness of not less than 30 μm. Then, a molding technique is used to encapsulate the carrier plate 110, the first conductive traces 122 and the first conductive vias 124 with the first dielectric material layer 120, and a polishing technique is used to remove a portion of the first dielectric material layer 120 to expose the top surfaces of the first conductive vias 124.

Next, as shown in fig. 5, a Build-up Process (e.g., Semi-additive) is performed to fabricate a second conductive trace 132, a second conductive via 134 and a conductive pad 136 on the first dielectric material layer 120 by electroplating; the second conductive traces 132 and the conductive pads 136 can be formed by high current plating techniques to have a thickness not less than 30 μm, and the second conductive traces 132 are connected to the top surface of the first conductive vias 124. The second dielectric material layer 130 is then used to cover the first dielectric material layer 120, the second conductive traces 132, the second conductive vias 134 and the conductive pads 136 by molding, and a portion of the second dielectric material layer 130 is removed by polishing to expose the top surfaces of the conductive pads 136.

Next, as shown in fig. 6, a passivation film 115 is adhered to the bottom surface of the carrier 110, and then a metal etching process is performed on the entire package substrate semi-finished product, so that the conductive pad 136 is partially removed and the top surface thereof is recessed below the top surface of the second dielectric material layer 130.

Next, as shown in fig. 7, the conductive path composed of the carrier plate 110, the first conductive trace 122, the first conductive via 124, the second conductive trace 132, the second conductive via 134 and the conductive pad 136 can form a plated metal layer on the top surface of the conductive pad 136 by using a low-cost electroplating process, and effectively control the surface roughness of the plated metal layer, i.e., a suitable power can be applied to the carrier plate 110, so as to perform the electroplating of the noble metal thin layer on the top surface of the conductive pad 136. In this embodiment, the noble metal is nickel-palladium-gold (Ni — Pb-Au); thus, a nickel palladium gold layer 140 having a thickness of no greater than 20nm is formed on the top surface of the conductive pad 136.

Next, the passivation film 115 and the carrier 110 are removed together, and an Anti-oxidation (Anti-Tarnish) process is performed on the bottom surface of the first conductive traces 122, such as soaking in a chemical solution, so as to form a passivation layer 150 with a thickness not greater than 60nm thereon, as shown in fig. 2. The thickness of the passivation layer 150 is very thin, before the subsequent circuit chip 160 is disposed on the first conductive trace 122, the flip chip package substrate 100 is baked at a high temperature, so that the passivation layer 150 is removed, and the pins 162 of the circuit chip 160 can be directly connected to the first conductive trace 122, and then the third dielectric material layer 170 is used to package the circuit chip 160 and the flip chip package substrate 100 into the semiconductor flip chip package 200 (i.e., there is no barrier between the third dielectric material layer 170 and the first dielectric material layer 120 for conductive heat dissipation), as shown in fig. 3. The above-mentioned "direct connection" is advantageous for the circuit chip 160 to dissipate heat through the flip chip package substrate 100 and reduce the line impedance of the external connection of the circuit chip 160. In addition, solder balls can be further formed on the ni-pd layer 140 on the top surface of the conductive pad 136, so that the flip chip package substrate 100 becomes a more complete package product.

Furthermore, the first dielectric material layer 120, the second dielectric material layer 130, and the third dielectric material layer 170 may be the same or different and are composed of an organic dielectric material (specifically, the type of the organic dielectric material further includes a mold compound, an Epoxy Molding Compound (EMC) or a primer) containing no glass fiber, or an inorganic dielectric material (such as an insulating oxide) containing no glass fiber and containing a filler (such as silicon dioxide or aluminum oxide).

The above description is only a preferred embodiment of the present invention, and the scope of the present invention should not be limited thereby. All changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced as further aspects of the invention.