阅读说明：本技术 一种晶体管管座及晶体管气密封装结构 (Transistor tube seat and transistor airtight packaging structure ) 是由 张迪 于 2020-07-28 设计创作，主要内容包括：本发明涉及晶体管封装技术领域,公开了一种晶体管管座及晶体管气密封装结构。所述晶体管管座包括绝缘底座和环向封闭金属底座,其中,所述绝缘底座的顶面用于放置晶体管芯片；所述绝缘底座的内部设有至少一个导电通道,所述绝缘底座的外周面与所述环向封闭金属底座的内环面通过填料密封连接。通过该晶体管管座,可以在解决TO管座高速率、高散热和低成本的同时,使TO管座及晶体管的尺寸可以继续变小,实现尺寸小型化目的。此外,通过所述晶体管气密封装结构,可以实现多晶体管芯片的立体式封装,进一步利于缩小晶体管封装结构的尺寸。(The invention relates to the technical field of transistor packaging, and discloses a transistor tube seat and a transistor airtight packaging structure. The transistor tube seat comprises an insulating base and a circumferential closed metal base, wherein the top surface of the insulating base is used for placing a transistor chip; at least one conductive channel is arranged in the insulating base, and the outer peripheral surface of the insulating base is connected with the inner annular surface of the annular closed metal base in a sealing mode through a filler. Through the transistor tube seat, the TO tube seat and the transistor can be continuously reduced in size while the high speed, high heat dissipation and low cost of the TO tube seat are achieved, and the purpose of size miniaturization is achieved. In addition, the transistor airtight packaging structure can realize the three-dimensional packaging of the polycrystalline chip, and is further favorable for reducing the size of the transistor packaging structure.)

1. A transistor header, comprising: the transistor chip packaging structure comprises an insulating base (1) and a circumferential closed metal base (2), wherein the top surface of the insulating base (1) is used for placing a transistor chip (300);

the transistor chip sealing structure is characterized in that at least one conductive channel (3) is arranged inside the insulating base (1), the peripheral surface of the insulating base (1) is hermetically connected with the inner annular surface of the annular closed metal base (2) through a filler (4), wherein the top ends of the conductive channels (3) are used for being electrically connected with chip pins of the transistor chips (300) in a one-to-one correspondence manner, and the bottom ends of the conductive channels (3) are used for being electrically connected with external wiring pieces of the transistors in a one-to-one correspondence manner.

2. The transistor socket of claim 1, wherein: at least one first conductive pad (51) is arranged on the top surface of the insulating base (1), wherein the first conductive pads (51) correspond to the conductive channels (3) one by one, so that the top ends of the conductive channels (3) are electrically connected with the chip pins of the transistor chip (300) through the corresponding first conductive pads (51).

3. The transistor socket of claim 2, wherein: the first conductive pad (51) is arranged at the top of the conductive channel (3), the transistor external wiring piece is connected with the bottom of the conductive channel (3) and is of an integrated structure, and the conductive channel (3) and the insulating base (1) are sealed through solder.

4. The transistor socket of claim 1, wherein: at least one second conductive pad (52) is arranged on the bottom surface of the insulating base (1), wherein the second conductive pads (52) correspond to the conductive channels (3) one by one, so that the bottom ends of the conductive channels (3) are electrically connected with the transistor external wiring piece through the corresponding second conductive pads (52) or the second conductive pads (52) are used as the transistor external wiring piece corresponding to the conductive channels (3).

5. The transistor socket of claim 1, wherein: the insulating base (1) is made of ceramic materials, glass materials or plastic materials.

6. The transistor socket of claim 1, wherein: the filler (4) is silver-copper solder, glass material or viscous material.

7. The transistor socket of claim 1, wherein: the insulating base (1) is made of glass materials, and the filler (4) is made of glass materials identical to the glass materials.

8. A transistor hermetic package structure is characterized in that: the transistor base comprises the transistor base according to any one of claims 1 to 6, and further comprises a metal cap (100), an optical window body (200) and a transistor chip (300), wherein the metal cap (100) is of a hollow structure;

the upper end of the metal pipe cap (100) is sealed through the light window body (200), and the lower end of the pipe cap (100) is welded and sealed with the peripheral surface of the annular closed metal base (2) in the transistor pipe seat;

the transistor chip (300) is placed on the top surface of an insulating base (1) in the transistor base and is positioned in a sealed space surrounded by the insulating base (1), the annular closed metal base (2), the metal tube cap (100) and the optical window body (200), and chip pins of the transistor chip (300) are electrically connected with corresponding conductive channels (3) in the transistor base.

9. The hermetic transistor package of claim 7, wherein: when the number of the transistor chips (300) is at least two, the top surface of the insulation base (1) is provided with at least one groove (13) capable of accommodating part of the transistor chips (300);

the chip pins of the part of the transistor chip (300) are electrically connected to the top ends of the corresponding conductive paths (3) by means of groove conductive pads (53) located on the groove bottom and/or groove side of the groove (13).

10. The hermetic transistor package of claim 7, wherein: the circuit also comprises at least one transistor pin (400), wherein the transistor pin (400) protrudes out of the bottom surface of the insulating base (1) and is used as a transistor external wiring piece to be electrically connected with the bottom end of the corresponding conductive channel (3).

Technical Field

The invention relates to the technical field of transistor packaging, in particular to a transistor tube seat and a transistor airtight packaging structure.

Background

TO sockets (TO is an english abbreviation of TRANSISTOR housing output) are widely used in the field of optoelectronic communication. In order TO meet the increasing requirements of high transmission rate, low cost, high heat dissipation, small size and the like, the TO glass metal packaging tube shell adopted by the current market becomes the mainstream design, and the specific preparation methods include the following two methods: (1) packaging by adopting a KOVAR (KOVAR alloy, also called iron-nickel-cobalt alloy) base, a radio frequency lead and low dielectric constant glass matched with a thermal expansion coefficient; (2) and packaging by adopting a stainless steel base, a radio frequency lead and high dielectric constant glass matched with the thermal expansion coefficient. However, for the TO package using the KOVAR alloy base, the poor heat dissipation capability cannot meet the requirement of the high-speed package for heat dissipation due TO the low thermal conductivity of the KOVAR alloy. For the TO tube shell adopting the stainless steel base, the glass dielectric constant is in direct proportion TO the thermal expansion coefficient, and the thermal expansion coefficient of the stainless steel is large, so that the thermal expansion coefficient of the required packaging glass is required TO be correspondingly increased, and the corresponding glass dielectric constant is large, so that the requirement of the high-speed tube shell on the single-channel high impedance is difficult TO meet.

In view of the above technical problems, chinese patent (CN109887888A-TO glass metal package tube case and manufacturing method) proposes a solution for using glass dielectric constant and thermal expansion coefficient and different metal materials in the TO glass metal package, but like the existing solution and the improved solution, the glass material is used TO fill the gap between different metals, so as TO balance the electrical insulation between different metals and the thermal expansion between different metals. However, the glass insulation structure must have enough volume TO play a role in balancing electrical insulation and thermal expansion, which makes the space occupied by the glass insulation filler large, and is not favorable for the miniaturization design of the TO header and the transistor. Especially in recent years, in the process of miniaturization of the TO header, the size of the TO header cannot be made smaller because the ratio of the glass filling material TO the entire package space is increasing. In view of the above, there is a need in the market TO provide a new TO socket that is advantageous for miniaturization design TO solve all the above problems thoroughly.

Disclosure of Invention

In order TO solve the problem that the size of the existing TO tube seat and the existing transistor can not be further reduced due TO the design of a glass-metal packaging tube shell, the invention aims TO provide a novel transistor tube seat and a novel transistor airtight packaging structure, which can continuously reduce the sizes of the TO tube seat and the transistor and realize the purpose of size miniaturization while solving the problems of high speed, high heat dissipation and low cost of the TO tube seat.

The technical scheme adopted by the invention is as follows:

a transistor tube seat comprises an insulating base and a circumferential closed metal base, wherein the top surface of the insulating base is used for placing a transistor chip;

the transistor chip comprises a circumferential closed metal base, at least one conductive channel is arranged in the insulating base, the outer circumferential surface of the insulating base is hermetically connected with the inner circumferential surface of the circumferential closed metal base through a filler, the top ends of the conductive channels are used for being electrically connected with chip pins of the transistor chip in a one-to-one correspondence mode, and the bottom ends of the conductive channels are used for being electrically connected with external wiring pieces of the transistor in a one-to-one correspondence mode.

Based on the above invention, a novel transistor base structure beneficial to miniaturization design is provided, namely, on one hand, the purposes of high speed, high heat dissipation, low cost and the like of the TO tube seat can be realized through the structural matching of the insulating base, the annular closed metal base, the conductive channel, the filler and the like, particularly, the difference of the thermal expansion coefficients of the insulating base and the annular closed metal base can be balanced by using the filler as a buffer body, so that the thermal expansion coefficient and the dielectric constant of the insulating base do not need to be correspondingly increased along with the characteristic of high thermal expansion coefficient of the annular closed metal base, the requirement of a high-speed tube shell on single-channel high impedance is met, on the other hand, the heat radiator and all the conductors share the same insulator to realize electrical insulation, the space proportion occupied by the insulator can be reduced, and the purpose of reducing the sizes of the tube seat and the transistor is realized.

Preferably, at least one first conductive pad is arranged on the top surface of the insulating base, wherein the first conductive pads are in one-to-one correspondence with the conductive channels, so that the top ends of the conductive channels are electrically connected with the chip pins of the transistor chip through the corresponding first conductive pads.

Specifically, the first conductive pad is arranged at the top of the conductive channel, the transistor external wiring piece is connected with the bottom of the conductive channel and is of an integrated structure, and the conductive channel and the insulating base are sealed through solder.

Preferably, at least one second conductive pad is arranged on the bottom surface of the insulating base, wherein the second conductive pad corresponds to the conductive channel one by one, so that the bottom end of the conductive channel is electrically connected with the transistor external wiring piece through the corresponding second conductive pad or the second conductive pad is used as the transistor external wiring piece corresponding to the conductive channel.

Preferably, the insulating base is made of ceramic materials, glass materials or plastic materials.

Preferably, the filler is silver-copper solder, glass material or viscous material.

Preferably, the insulating base is made of glass, and the filler is made of glass material the same as the glass material.

The other technical scheme adopted by the invention is as follows:

a transistor airtight packaging structure comprises the transistor base, a metal pipe cap, a light window body and a transistor chip, wherein the metal pipe cap is of a hollow structure;

the upper end of the metal pipe cap is sealed through the optical window body, and the lower end of the pipe cap is welded and sealed with the peripheral surface of the annular closed metal base in the transistor base;

the transistor chip is arranged on the top surface of an insulating base in the transistor tube seat and is positioned in a sealed space defined by the insulating base, the annular closed metal base, the metal tube cap and the light window body, and chip pins of the transistor chip are electrically connected with corresponding conductive channels in the transistor tube seat.

Preferably, when the number of the transistor chips is at least two, the top surface of the insulating base is provided with at least one groove capable of accommodating part of the transistor chips;

and chip pins of the partial transistor chips are electrically connected with the top ends of the corresponding conductive channels through groove conductive bonding pads on the groove bottom surface and/or the groove side surface of the groove.

Preferably, the device further comprises at least one transistor pin, wherein the transistor pin protrudes out of the bottom surface of the insulating base and is used as the transistor external wiring piece to be electrically connected with the bottom end of the corresponding conductive channel.

The invention has the beneficial effects that:

(1) the invention provides a novel transistor base structure beneficial to miniaturization design, namely, on one hand, the purposes of high speed, high heat dissipation, low cost and the like of the TO tube seat can be realized through the structural matching of the insulating base, the annular closed metal base, the conductive channel, the filler and the like, particularly, the difference of the thermal expansion coefficients of the insulating base and the annular closed metal base can be balanced by using the filler as a buffer body, so that the thermal expansion coefficient and the dielectric constant of the insulating base do not need to be correspondingly increased along with the characteristic of high thermal expansion coefficient of the annular closed metal base, the requirement of a high-speed tube shell on single-channel high impedance is met, on the other hand, the heat radiator and all the conductors share the same insulator to realize electrical insulation, the space proportion occupied by the insulator can be reduced, and the purpose of reducing the sizes of the tube seat and the transistor is realized;

(2) the transistor tube seat also has the advantages of convenience in chip packaging, stable packaging structure, strong practicability, simple structure and the like, and is convenient for practical popularization and application;

(3) the invention also provides a novel transistor airtight packaging structure, which can realize the three-dimensional packaging of the polycrystalline chip and is further beneficial to reducing the size of the transistor packaging structure.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is an assembled perspective view of a first transistor socket according to the present invention.

Fig. 2 is an assembled cross-sectional structural diagram of a first transistor socket provided in the present invention.

Fig. 3 is a schematic bottom view of an insulating base in a first transistor socket according to the present invention.

Fig. 4 is a schematic diagram of a disassembled three-dimensional structure of a second transistor socket provided by the present invention.

FIG. 5 is an assembled cross-sectional structural view of a second transistor socket according to the present invention.

FIG. 6 is a schematic bottom view of an insulating base in a second transistor socket according to the present invention.

Fig. 7 is a schematic disassembled three-dimensional structure of a third transistor socket provided by the invention.

Fig. 8 is a schematic diagram of a disassembled three-dimensional structure of a first transistor hermetic package structure provided in the present invention.

Fig. 9 is an assembled cross-sectional structural diagram of a first transistor hermetic package structure provided in the present invention.

Fig. 10 is a schematic diagram of a disassembled three-dimensional structure of a second airtight transistor package structure provided in the present invention.

Fig. 11 is an assembled cross-sectional structural diagram of a second airtight transistor package structure provided in the present invention.

Fig. 12 is a schematic diagram of a split three-dimensional structure of a third airtight transistor package structure provided by the present invention.

Fig. 13 is an assembled cross-sectional structural diagram of a third airtight transistor package structure provided by the present invention.

Fig. 14 is a schematic diagram of a split three-dimensional structure of a fourth airtight transistor package structure provided by the present invention.

Fig. 15 is an assembled cross-sectional structural diagram of a fourth transistor hermetic package structure provided by the present invention.

In the above drawings: 1-an insulating base; 11-lower seat body; 12-an upper seat body; 13-a groove; 2-annularly sealing the metal base; 3-a conductive channel; 4-a filler; 51-a first conductive pad; 52-second conductive pad; 53-recessed conductive pads; 100-metal pipe caps; 200-a light window; 300-a transistor chip; 400-transistor pins.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.

It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time; for the term "/and" as may appear herein, which describes another associative object relationship, it means that two relationships may exist, e.g., a/and B, may mean: a exists independently, and A and B exist independently; in addition, for the character "/" that may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.

It will be understood that when an element is referred to herein as being "connected," "connected," or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, if a unit is referred to herein as being "directly connected" or "directly coupled" to another unit, it is intended that no intervening units are present. In addition, other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between … …" versus "directly between … …", "adjacent" versus "directly adjacent", etc.).

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.

It should also be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

It should be understood that specific details are provided in the following description to facilitate a thorough understanding of example embodiments. However, it will be understood by those of ordinary skill in the art that the example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams in order not to obscure the examples in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.

It should be understood that the optical paths of the input and output ends in the description of the present invention are reversible. Under certain conditions, the input terminal can be used as the output terminal, and the output terminal can be used as the input terminal at the same time.