Chip packaging structure and manufacturing method thereof
阅读说明:本技术 芯片封装结构及其制造方法 (Chip packaging structure and manufacturing method thereof ) 是由 张简上煜 徐宏欣 林南君 于 2019-06-14 设计创作,主要内容包括:本发明提供一种芯片封装结构,其包括第一芯片、第二芯片、第一模封体、多个第一穿模导孔、多个第二穿模导孔以及第一线路层。第二芯片堆叠于第一芯片上。第一模封体覆盖第一芯片及第二芯片。第一穿模导孔位于第一模封体内且电性连接于第一芯片。第二穿模导孔位于第一模封体内且电性连接于第二芯片。第一线路层于第一模封体上且电性连接于第一穿模导孔及第二穿模导孔。多个第一穿模导孔之间具有第一间距。多个第二穿模导孔之间具有第二间距。第一间距大于第二间距。一种芯片封装结构的制造方法亦被提供。(The invention provides a chip packaging structure which comprises a first chip, a second chip, a first mold packaging body, a plurality of first through mold guide holes, a plurality of second through mold guide holes and a first circuit layer. The second chip is stacked on the first chip. The first mold package covers the first chip and the second chip. The first through mold via is located in the first mold package and electrically connected to the first chip. The second die through guide hole is positioned in the first die seal body and is electrically connected to the second chip. The first circuit layer is arranged on the first mold sealing body and is electrically connected with the first mold through guide hole and the second mold through guide hole. A first interval is formed among the first die penetrating guide holes. And a second interval is formed among the second die penetrating guide holes. The first pitch is greater than the second pitch. A method for manufacturing the chip package structure is also provided.)
1. A chip package structure, comprising:
a first chip;
a second chip stacked on the first chip;
a first mold sealing body covering the first chip and the second chip;
a plurality of first die through vias in the first die package and electrically connected to the first chip;
a plurality of second die through vias located in the first die encapsulation and electrically connected to the second chip; and
a first circuit layer on the first mold sealing body and electrically connected to the first through mold vias and the second through mold vias, wherein:
a first interval is formed among the first die penetrating guide holes;
a second interval is formed among the second die penetrating guide holes; and is
The first pitch is greater than the second pitch.
2. The chip packaging structure according to claim 1, wherein:
each first die-penetrating guide hole is provided with a first top end and a first bottom end which are opposite to each other;
the first top end is far away from the first chip than the first bottom end;
the first tip has a first aperture;
each second die penetrating guide hole is provided with a second top end and a second bottom end which are opposite to each other;
the second top end is far away from the second chip than the second bottom end;
the second tip has a second aperture; and is
The first aperture is larger than the second aperture.
3. The chip packaging structure according to claim 1, wherein:
the first mold sealing body covers the active surface and the side wall of the first chip; and is
The first mold package covers the active surface and the side wall of the second chip.
4. The chip packaging structure according to claim 1, wherein the first mold package exposes a back surface of the first chip.
5. The chip package structure of claim 1, wherein an aspect ratio of the plurality of first through mold vias is greater than 2.
6. The chip packaging structure of claim 1, further comprising:
the second mold sealing body is positioned on the first mold sealing body and covers the first circuit layer;
a plurality of third through mold vias located in the second mold package and electrically connected to the first circuit layer; and
a second circuit layer located on the second mold sealing body and electrically connected to the third through mold guide holes, wherein:
the material of the second mold sealing body comprises organic polymer.
7. A manufacturing method of a chip packaging structure comprises the following steps:
providing a carrier plate;
configuring a first chip on the carrier plate;
configuring a second chip on the first chip;
forming a first mold package body on the carrier plate, wherein the first mold package body covers the first chip and the second chip;
forming a plurality of first die through vias in the first die encapsulation, wherein the plurality of first die through vias are electrically connected to the first chip;
forming a plurality of second die through vias in the first die encapsulation, wherein the plurality of second die through vias are electrically connected to the second chip;
forming a first circuit layer on the first mold sealing body, wherein the first circuit layer is electrically connected to the first mold through vias and the second mold through vias; and
and removing the carrier plate after the first circuit layer is formed.
8. The method of claim 7, wherein the first encapsulant body comprises an organic polymer, and the step of forming the first and second through mold vias comprises:
forming a plurality of first die through openings in the first die encapsulation in a drilling mode, wherein the first die through openings expose the first chip;
forming a plurality of second die through openings in the first die package in a drilling mode, wherein the second die through openings expose the second chip;
performing plasma treatment on the first die penetrating openings and the second die penetrating openings;
forming a plurality of first die penetrating guide holes in the plurality of first die penetrating openings; and
and forming a plurality of second die penetrating guide holes in the plurality of second die penetrating openings.
9. The method of manufacturing a chip package structure according to claim 7, further comprising:
forming a second mold package on the first mold package, wherein the second mold package covers the first circuit layer;
forming a plurality of third die through guide holes in the second die encapsulation body, wherein the plurality of third die through guide holes are electrically connected to the first circuit layer; and
forming a second circuit layer on the second mold sealing body, and electrically connecting the second circuit layer to the third through mold vias, wherein:
the step of removing the carrier plate is after the second circuit layer is formed.
10. The method for manufacturing a chip package structure according to claim 9, wherein the material of the second mold package body comprises an organic polymer, and the step of forming the plurality of third through mold vias comprises:
forming a plurality of third die through openings in the second die seal body in a drilling mode, wherein the first circuit layer is exposed out of the third die through openings;
performing plasma treatment on the third through-mold openings; and
and forming a plurality of third die penetrating guide holes in the plurality of third die penetrating openings.
Technical Field
The present disclosure relates to electronic devices, and particularly to a chip package structure and a method for manufacturing the same.
Background
In the fabrication of electronic devices such as Panel Level Packaging (PLP) or Wafer Level Packaging (WLP), the masks used for photolithography are expensive.
Disclosure of Invention
The invention provides a chip packaging structure and a manufacturing method thereof, wherein the manufacturing method is simple and low in cost.
The chip packaging structure comprises a first chip, a second chip, a first mold packaging body, a plurality of first mold through guide holes, a plurality of second mold through guide holes and a first circuit layer. The second chip is stacked on the first chip. The first mold package covers the first chip and the second chip. The first through mold via is located in the first mold package and electrically connected to the first chip. The second die through guide hole is positioned in the first die seal body and is electrically connected to the second chip. The first circuit layer is arranged on the first mold sealing body and is electrically connected with the first mold through guide hole and the second mold through guide hole. A first interval is formed among the first die penetrating guide holes. And a second interval is formed among the second die penetrating guide holes. The first pitch is greater than the second pitch.
The manufacturing method of the chip packaging structure comprises the following steps. A carrier plate is provided. A first chip is disposed on the carrier. The second chip is configured on the first chip. And forming a first mold sealing body on the carrier plate, wherein the first mold sealing body covers the first chip and the second chip. A plurality of first through mold vias are formed in the first mold package and electrically connected to the first chip. And forming a plurality of second die through guide holes in the first die encapsulation body, wherein the plurality of second die through guide holes are electrically connected to the second chip. And forming a first circuit layer on the first mold sealing body, wherein the first circuit layer is electrically connected to the first mold through holes and the second mold through holes. After the first circuit layer is formed, the carrier plate is removed.
In view of the above, in the chip package structure, the chip and the circuit layer are separated from each other by the mold package body, and the chip and the circuit layer are electrically connected to each other by the through-mold via. Therefore, the manufacturing method of the chip packaging structure is simple and low in cost.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1J are schematic side views illustrating a method for manufacturing a portion of a chip package structure according to an embodiment of the invention.
Fig. 2A and 2B are schematic partial top views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention.
[ notation ] to show
100: chip packaging structure
110: first chip
111: first connecting pad
112: protective layer
110 a: a first active surface
110 b: first back surface
110 s: first side wall
120: second chip
121: second connecting pad
122: protective layer
120 a: second active surface
120 b: second back surface
120 s: second side wall
130: first mold package
130 a: the top surface
131: first die penetration opening
131 s: first inner wall
132: second die opening
132 s: second inner wall
141: first die-through guide hole
141 a: first top end
141 b: first bottom end
141 d: first aperture
141 h: first height
142: second die-through guide hole
142 a: second top end
142 b: second bottom end
142 d: second aperture
142 h: second height
145: first circuit layer
150: second mold package
150 a: the top surface
151: third die opening
151 s: third inner wall
161: third die-through guide hole
165: second circuit layer
170: third mold package
181: fourth die-through guide hole
185: third circuit layer
190: conductive terminal
10: support plate
11: release layer
12: adhesive layer
13. 14: ion plasma
P1: first interval
P2: second pitch
Detailed Description
Directional phrases used herein (e.g., upper, lower, right, left, front, rear, top, bottom) are used only as referring to the drawings and are not intended to imply absolute orientation.
Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.
The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness, dimensions, or dimensions of layers, elements, or regions in the figures may be exaggerated for clarity. The same or similar reference symbols denote the same or similar layers, elements or regions, and the following paragraphs will not be repeated.
Fig. 1A to 1J are schematic side views illustrating a method for manufacturing a portion of a chip package structure according to an embodiment of the invention. Fig. 2A and 2B are schematic partial top views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention. Fig. 2A may be a partial top view schematic diagram of the structure of fig. 1A. Fig. 2B may be a partial top view schematic diagram of the structure of fig. 1E. For clarity, some of the layers or members are not shown in fig. 1A to 1J and fig. 2A and 2B. For example, the
Referring to fig. 1A and fig. 2A, a
In this embodiment, the
Referring to fig. 1A and fig. 2A, the
With reference to fig. 1A and fig. 2A, the
In the present embodiment, the size of the
The
In the embodiment, the first pitch P1 is between the adjacent
In the present embodiment, the
It should be noted that the sequence of disposing the
Referring to fig. 1B, a
For example, the first
In the present embodiment, the
Referring to fig. 1C, a plurality of first mold through openings 131 and a plurality of second mold through openings 132 are formed in the first
In the embodiment, the first through mold openings 131 expose the corresponding
Referring to fig. 1D, in the present embodiment, a plasma treatment (plasma) may be performed on the first
Referring to fig. 1E, a first through mold via 141 is formed in the first through mold opening 131, a second through mold via 142 is formed in the second through mold opening 132, and a
For example, the conductive material may be formed on the first
Referring to fig. 1E and fig. 2B, in a top view, the first through via 141 may be disposed in a manner similar to that of the
With continued reference to fig. 1E and fig. 2B, the shape (shape) of the first through-mold via 141 may substantially correspond to the first through-mold opening 131, and the shape of the second through-mold via 142 may substantially correspond to the second through-mold opening 132. That is, the first through mold via 141 has a first top end 141a far from the
Referring to fig. 1F, in the present embodiment, after the
In an embodiment, the
Referring to fig. 1G, in the present embodiment, a plurality of third through
Referring to fig. 1G, in the present embodiment, the surface of the second mold sealing body 150 (e.g., the
Referring to fig. 1H, in the present embodiment, a plurality of third through mold vias 161 are formed in the plurality of third through
The third tsv 161 may be formed in the same or similar manner as the
In an embodiment not shown, the steps of forming the second
Referring to fig. 1I, in the present embodiment, after the second circuit layer 165 is formed, a third mold package 170 may be formed on the
Referring to fig. 1I, in the present embodiment, a plurality of fourth through mold vias 181 may be formed in the third mold package 170, a third circuit layer 185 is formed on the third mold package 170, the plurality of fourth through mold vias 181 are electrically connected to the second circuit layer 165, and the third circuit layer 185 is electrically connected to the plurality of fourth through mold vias 181. The fourth tsv 181 may be formed in the same or similar manner as the third tsv 161, and the third circuit layer 185 may be formed in the same or similar manner as the second circuit layer 165, which is not described herein again.
Referring to fig. 1J, after the above steps are completed (e.g., after the
Referring to fig. 1J, in the present embodiment, a plurality of conductive terminals 190 may be disposed on the third through via 161 and the third circuit. The conductive terminal 190 may be a conductive pillar (conductive pillar), a solder ball (solder ball), a conductive bump (conductive bump), or a conductive structure with other forms or shapes. Conductive terminals 190 may be formed by electroplating, deposition, ball placement, reflow, and/or other suitable processes.
In one embodiment, the fourth through mold via 181 and the third circuit layer 185 located between the conductive terminal 190 and the third mold package 170 may be referred to as under-bump-metallurgy (UBM).
Referring to fig. 1J, in the present embodiment, a dicing process or a singulation process may be performed to cut through the
It should be noted that the present invention does not limit the sequence of removing the
The fabrication of the chip package structure 100 of the present embodiment can be substantially completed through the above steps.
Referring to fig. 1J, the chip package structure 100 includes a
In the present embodiment, the
In the present embodiment, the
In this embodiment, the first through via 141 can be formed by drilling the
In the present embodiment, the first height 141h of the
In this embodiment, the chip package structure 100 may further include a second
In summary, in the chip package structure of the present invention, the chip and the circuit layer are separated from each other by the mold package body, and the chip and the circuit layer are electrically connected to each other by the through-mold via. Therefore, the manufacturing method of the chip packaging structure is simple and low in cost.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.