阅读说明：本技术 线路结构及芯片封装件 (Circuit structure and chip packaging piece ) 是由 林元鸿 杨昇帆 孙宇程 于 2019-05-08 设计创作，主要内容包括：本发明提供一种线路结构,其包括第一信号线以及第二信号线。第一信号线包括第一线段、第一球栅阵列焊垫以及位于第一线段与第一球栅阵列焊垫之间的第一通孔。第二信号线包括第二线段、第二球栅阵列焊垫以及位于第二线段与第二球栅阵列焊垫之间的第二通孔。以俯视观之,第一球栅阵列焊垫的中心与第二球栅阵列焊垫的中心之间的连线具有第一距离,第一通孔的中心与第二通孔的中心之间的连线具有第二距离,且第一距离小于第二距离。一种芯片封装件亦被提出。(The invention provides a circuit structure which comprises a first signal line and a second signal line. The first signal line comprises a first line segment, a first ball grid array pad and a first through hole positioned between the first line segment and the first ball grid array pad. The second signal line comprises a second line segment, a second ball grid array pad and a second through hole positioned between the second line segment and the second ball grid array pad. In a top view, a connection line between the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a connection line between the center of the first via and the center of the second via has a second distance, and the first distance is smaller than the second distance. A chip package is also provided.)

1. A wiring structure comprising:

a first signal line including a first line segment, a first ball grid array pad, and a first via between the first line segment and the first ball grid array pad; and

a second signal line including a second line segment, a second ball grid array pad, and a second via between the second line segment and the second ball grid array pad,

wherein in a top view:

a connecting line between the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance;

a line between the center of the first through hole and the center of the second through hole has a second distance; and is

The first distance is less than the second distance.

2. The circuit structure of claim 1, wherein said first ball grid array pad, said second ball grid array pad, said first via and said second via are located between said first wire segment and said second wire segment.

3. The circuit structure of claim 1, wherein a center of said first ball grid array pad and a center of said first via do not overlap and a center of said second ball grid array pad and a center of said second via do not overlap in a top view.

4. The wiring structure according to claim 1, further comprising:

and the grounding through hole is configured between the first signal line and the second signal line.

5. The circuit structure according to claim 4, wherein the ground via is disposed on a line connecting a center of the first via and a center of the second via in a top view.

6. The wiring structure according to claim 1, further comprising:

the third signal wire and the first signal wire form a first differential routing pair; and

and the fourth signal wire and the second signal wire form a second differential routing wire pair.

7. The wiring structure of claim 6, wherein the first differential pair of traces has a signal transmission frequency between 1 GHz and 30 GHz and the second differential pair of traces has a signal transmission frequency between 1 GHz and 30 GHz.

8. The wiring structure according to claim 1, further comprising:

a core layer, wherein the first and second vias penetrate the core layer.

9. The circuit structure of claim 1, wherein the first signal line further comprises a conductive via between the first via and the first line segment, and a thickness of the first via is greater than a thickness of the conductive via.

10. The circuit structure of claim 1, wherein said first signal line further comprises a conductive via between said first via and said first ball grid array pad, and a thickness of said first via is greater than a thickness of said conductive via.

11. A chip package, comprising:

a chip having an active surface;

the circuit structure according to any one of claims 1 to 10, located on the active surface of the chip and electrically connected to the chip; and

and the conductive terminals are positioned on the first ball grid array welding pad and the second ball grid array welding pad of the circuit structure.

Technical Field

The present disclosure relates to electronic devices, and particularly to a circuit structure and a chip package.

Background

In high-speed and high-frequency signal transmission, a conductor for transmitting signals needs to be designed with good impedance matching (impedance matching) to reduce reflection caused by impedance mismatching, that is, to reduce insertion loss (insertion loss) during signal transmission, and to relatively increase return loss (return loss) during signal transmission, so as to improve the quality of signal transmission.

Disclosure of Invention

The invention provides a circuit structure and a chip packaging piece, which have better signal transmission quality.

The circuit structure of the invention comprises a first signal line and a second signal line. The first signal line comprises a first line segment, a first ball grid array pad and a first through hole. The first through hole is positioned between the first line segment and the first ball grid array welding pad. The second signal line comprises a second line segment, a second ball grid array pad and a second through hole. The second through hole is positioned between the second line segment and the second ball grid array welding pad. In a top view, a connection line between the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a connection line between the center of the first via and the center of the second via has a second distance, and the first distance is smaller than the second distance.

In an embodiment of the invention, the first ball grid array pad, the second ball grid array pad, the first via and the second via are located between the first line segment and the second line segment.

In an embodiment of the invention, the center of the first ball grid array pad and the center of the first via do not overlap, and the center of the second ball grid array pad and the center of the second via do not overlap in a top view.

In an embodiment of the invention, the circuit structure further includes a ground via. The grounding through hole is configured between the first signal line and the second signal line.

In an embodiment of the invention, the ground via is disposed on a connecting line between a center of the first via and a center of the second via in a top view.

In an embodiment of the invention, the circuit structure further includes a third signal line and a fourth signal line. The third signal line and the first signal line form a first differential routing line pair. The fourth signal line and the second signal line form a second differential routing pair.

In an embodiment of the invention, a signal transmission frequency of the first differential trace pair is between 1 ghz and 30 ghz, and a signal transmission frequency of the second differential trace pair is between 1 ghz and 30 ghz.

In an embodiment of the invention, the circuit structure further includes a core layer. The first through hole and the second through hole penetrate through the core layer.

In an embodiment of the invention, the first signal line further includes a conductive via. The conductive through hole is positioned between the first through hole and the first line section, and the thickness of the first through hole is larger than that of the conductive through hole.

In an embodiment of the invention, the first signal line further includes a conductive via. The conductive through hole is positioned between the first through hole and the first ball grid array welding pad, and the thickness of the first through hole is larger than that of the conductive through hole.

The chip package of the invention comprises a chip, the circuit structure and a plurality of conductive terminals. The chip has an active surface. The circuit structure is located on the active surface of the chip. The circuit structure is electrically connected to the chip. The conductive terminals are located on the first ball grid array pad and the second ball grid array pad of the circuit structure.

Based on the above, the circuit structure and the chip package having the same of the present invention can have better signal transmission quality.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 illustrates a partial top view schematic diagram of a chip package according to an embodiment of the invention.

Fig. 2 shows a schematic top view of a part of a line structure according to a first embodiment of the invention.

Fig. 3 shows a partially schematic perspective view of a wiring structure of a first embodiment of the present invention.

Fig. 4 shows a schematic partial cross-sectional view of a wiring structure of a first embodiment of the present invention.

Fig. 5 shows a schematic top view of a part of a wiring structure according to a second embodiment of the present invention.

Fig. 6 shows a schematic top view of a portion of a circuit structure of a comparative example.

Fig. 7 is a graph showing signal isolation simulation curves of the circuit structure of the comparative example and the circuit structure of the test example at different transmission frequencies.

Fig. 8 is a signal loss simulation graph of the line structure of the comparative example and the line structure of the test example at different transmission frequencies.

[ notation ] to show

100. 200 and 600: circuit structure

900: chip package

DP 1: first differential routing pair

110. 610: first signal line

111. 611: first line segment

112. 612: first through hole

112C, 612C: center of a ship

113: first ball grid array pad

113C: center of a ship

120. 620: second signal line

121. 621: second line segment

122. 622: second through hole

122C, 622C: center of a ship

123: second ball grid array pad

123C: center of a ship

DP 2: second differential wiring pair

130: third signal line

131: third line segment

132: third through hole

132C: center of a ship

133: third ball grid array pad

133C: center of a ship

140: fourth signal line

141: the fourth line segment

142: fourth through hole

142C: center of a ship

143: fourth ball grid array pad

143C: center of a ship

250: ground via

160: core layer

160 a: first surface

160 b: second surface

160 h: thickness of

171. 181: insulating layer

172. 182: conductive layer

173. 183: conductive vias

191: chip and method for manufacturing the same

191 a: active surface

192: conductive terminal

L1: first distance

L2: second distance

L3: third distance

L4: a fourth distance

L5: a fifth distance

L6: a sixth distance

L7: a seventh distance

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference signs denote the same or similar elements, and the following paragraphs will not be repeated. In addition, directional terms mentioned in the embodiments, for example: up, down, left, right, front or rear, etc., are directions with reference to the attached drawings only. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.

Fig. 1 illustrates a partial top view schematic diagram of a chip package according to an embodiment of the invention.

Referring to fig. 1, the chip package 900 includes a chip 191, a circuit structure 100, a molding compound (not shown), and a plurality of conductive terminals 192. The chip 191 has an active surface 191 a. The chip 191 is disposed on the wiring structure 100 such that the active surface 191a faces the wiring structure 100. The circuit structure 100 is electrically connected to the chip 191. The molding compound may be disposed on the circuit structure 100 and cover the chip 191. The conductive terminals 192 are located on the circuit structure 100 and electrically connected to the circuit structure 100. The circuit structure 100 is located between the chip 191 and the conductive terminals 192.

In the present embodiment, the conductive terminals 192 may be conductive metal balls (e.g., solder balls), and the conductive terminals 192 may be arranged in an array. That is, the Chip package may be a Flip Chip Ball grid array package (FCBGA). Generally, in the flip-chip BGA package, the positions of the metal conductive balls (e.g., the conductive terminals 192) can be configured according to the specifications of the product.

In this embodiment, the line structure 100 may include a plurality of differential pair wires (differential pair). In terms of structural design, the differential trace may include two signal lines, and the aforementioned routing (layout) of the two signal lines is substantially the same or similar. That is to say, the lengths of the two signal lines are substantially similar, and the routing directions of the two signal lines are substantially similar. In signal transmission, the differential traces may transmit complementary signals (complementary signals) by means of differential signals (differential signaling). The complementary signal is composed of a negative signal (negative signal) and a positive signal (positive signal).

With the above-described configuration, the wiring structure (e.g., the wiring structure 100 or a wiring structure similar to the wiring structure 100) can be adapted to the transmission of high-frequency signals. It should be noted that the present invention is not limited to the above-mentioned circuit structure only suitable for the transmission of high frequency signals.

It is noted that, in the chip package 900 of the present embodiment, the circuit structure is exemplified by the circuit structure 100. While in other embodiments not shown, the circuit structure of the chip package may be a circuit structure similar to circuit structure 100 (e.g., circuit structure 200 shown in fig. 5).

A line structure 100 or a line structure 200 of an embodiment of the present invention is described in detail below.

Fig. 2 shows a schematic top view of a part of a line structure according to a first embodiment of the invention. Fig. 3 shows a partially schematic perspective view of a wiring structure of a first embodiment of the present invention. Fig. 4 shows a schematic partial cross-sectional view of a wiring structure of a first embodiment of the present invention. Specifically, fig. 2 may be an enlarged schematic view of a partial line structure of the region R in fig. 1, fig. 3 may be a perspective schematic view of fig. 2, and fig. 4 may be a cross-sectional schematic view along a line connecting points a-B-C-D-E in fig. 2. For clarity, the film layer and members are not shown in fig. 2, 3, and 4. For example, in fig. 2 and 3, the insulating film and the components are not shown. Also for example, in FIG. 4, a portion of the film layer on the first surface 160a of the core layer 160 is omitted from the partially cross-sectional view of the B-C-D-E point connection, and a portion of the film layer on the second surface 160B of the core layer 160 (below the second surface 160B in FIG. 4) is omitted from the partially cross-sectional view of the A-B-C-D point connection.

In the present embodiment, the first signal line 110 includes a first line segment 111, a first via 112 and a first ball grid array pad 113. The first via 112 is located between the first segment 111 and the first ball grid array pad 113, and the first via 112 is electrically connected to the first segment 111 and the first ball grid array pad 113. The second signal line 120 includes a second line segment 121, a second via 122, and a second ball grid array pad 123. The second via 122 is located between the second segment 121 and the second ball grid array pad 123, and the second via 122 is electrically connected to the second segment 121 and the second ball grid array pad 123. The third signal line 130 includes a third line segment 131, a third via 132, and a third ball grid array pad 133. The third via 132 is located between the third segment 131 and the third ball grid array pad 133, and the third via 132 is electrically connected to the third segment 131 and the third ball grid array pad 133. The fourth signal line 140 includes a fourth line segment 141, a fourth via 142, and a fourth ball grid array pad 143. The fourth through hole 142 is located between the fourth line segment 141 and the fourth ball grid array pad 143, and the fourth through hole 142 is electrically connected to the fourth line segment 141 and the fourth ball grid array pad 143.

In the present embodiment, in a top view (as shown in fig. 2, or in a direction from the first surface 160a to the second surface 160b of the core layer 160), a connection line between the center 113C of the first ball grid array pad 113 and the center 123C of the second ball grid array pad 123 has a first distance L1, a connection line between the center 112C of the first via 112 and the center 122C of the second via 122 has a second distance L2, and the first distance L1 is smaller than the second distance L2. As a result, when the circuit structure 100 is used for high-frequency signal transmission, the signal interference between the first signal line 110 and the second signal line 120 can be reduced.

In the present embodiment, the first ball grid array pad 113, the second ball grid array pad 123, the first via 112 and the second via 122 are located between the first line segment 111 and the second line segment 121 in a top view.

In the present embodiment, the center 113C of the first ball grid array pad 113 does not overlap the center 112C of the first via 112, and the center 123C of the second ball grid array pad 123 does not overlap the center 122C of the second via 122 in a top view.

In this embodiment, the circuit structure 100 may further include a core layer 160, an insulating layer 171, an insulating layer 181, a conductive layer 172, and a conductive layer 182, and the first via 112 and the second via 122 penetrate through the core layer 160. The core layer 160 has a first surface 160a and a second surface 160b opposite to each other. The conductive layer 172 and the insulating layer 171 are located on the first surface 160a of the core layer 160. The conductive layer 182 and the insulating layer 181 are located on the second surface 160b of the core layer 160. Conductive layer 172 can be one or more conductive layers and/or conductive layer 182 can be one or more conductive layers, as the invention is not limited in this respect.

In the embodiment, if the conductive layers 172 are multiple conductive layers, the multiple conductive layers 172 may be separated from each other by the insulating layer 171, and the different conductive layers 172 may be electrically connected to each other by corresponding conductive vias (conductive vias) 173. For example, the first via 112 and the first line segment 111 may be electrically connected to each other through the corresponding conductive via 173 between the first via 112 and the first line segment 111.

In this embodiment, if the conductive layers 182 are multiple conductive layers, the multiple conductive layers 182 can be separated from each other by the insulating layer 181, and different conductive layers 182 can be electrically connected to each other through the corresponding conductive vias 183. For example, the first via 112 and the first ball grid array pad 113 may be electrically connected to each other through a corresponding conductive via 183 between the first via 112 and the first ball grid array pad 113.

In the present embodiment, the conductive Via 173 and/or the conductive Via 183 are, for example, Buried Vias (BVH), but the present invention is not limited thereto.

In the present embodiment, the first segment 111 of the first signal line 110, the second segment 121 of the second signal line 120, the third segment 131 of the third signal line 130, and the fourth segment 141 of the fourth signal line 140 may be the same film layer.

In the present embodiment, the first segment 111 of the first signal line 110, the second segment 121 of the second signal line 120, the third segment 131 of the third signal line 130, and the fourth segment 141 of the fourth signal line 140 may be a portion of the conductive layer 172 farthest from the first surface 160a on the first surface 160a of the core layer 160.

In the present embodiment, the first ball grid array pad 113 of the first signal line 110, the second ball grid array pad 123 of the second signal line 120, the third ball grid array pad 133 of the third signal line 130, and the fourth ball grid array pad 143 of the fourth signal line 140 may be the same film layer.

In the present embodiment, the first ball grid array pad 113 of the first signal line 110, the second ball grid array pad 123 of the second signal line 120, the third ball grid array pad 133 of the third signal line 130, and the fourth ball grid array pad 143 of the fourth signal line 140 may be a portion of the conductive layer 182 on the second surface 160b of the core layer 160 farthest from the second surface 160 b.

In the embodiment, the core layer 160 may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulating silicon substrate, a Polyimide (PI) glass fiber composite substrate, or the like, but the invention is not limited thereto. The vias (e.g., the first via 112 and the second via 122) penetrating the core layer 160 may be referred to as core vias (core vias).

In the present embodiment, the first via 112 of the first signal line 110, the second via 122 of the second signal line 120, the third via 132 of the third signal line 130, and the fourth via 142 of the fourth signal line 140 may be solid conductive pillars, but the invention is not limited thereto. In one embodiment, the first through hole 112 of the first signal line 110, the second through hole 122 of the second signal line 120, the third through hole 132 of the third signal line 130, and the fourth through hole 142 of the fourth signal line 140 may be hollow Plated Through Holes (PTH); alternatively, the through holes may be filled with a resin material or a polymer glass-ceramic mixture, and the invention is not limited thereto. In one embodiment, the conductive material in the vias (e.g., the first via 112 and the second via 122) and the conductive layer 172 contacting the first surface 160a and/or the conductive layer 182 contacting the second surface 160b can be formed in the same step.

In the present embodiment, the thickness of the first via 112 and the thickness of the second via 122 are greater than the thickness of the conductive via 173 and the thickness of the conductive via 183.

In one embodiment, the thickness 160h of the core layer 160 may be on the order of hundreds of micrometers (μm), and the thickness of the conductive layer 172, the thickness of the conductive layer 182, the thickness of the conductive via 173, and the thickness of the conductive via 183 may be on the order of tens to thousands of nanometers (nm). That is, the thickness of the conductive layer 172, the thickness of the conductive layer 182, the thickness of the conductive via 173, and the thickness of the conductive via 183 may be very thin compared to the thickness 160h of the core layer 160.

In this embodiment, the impedance matching (impedance matching) between the conductors of the two signal lines of the differential trace pair can be achieved through structural design. Therefore, when high-frequency signals are transmitted through the differential wiring pairs, the reflection phenomenon of the signals in the transmission process can be reduced.

For example, a connection line between the center 113C of the first ball grid array pad 113 and the center 133C of the third ball grid array pad 133 has a third distance L3, a connection line between the center 112C of the first via 112 and the center 132C of the third via 132 has a fourth distance L4, and the fourth distance L4 is smaller than the third distance L3. In the current path (currentpath) of the first signal line 110, the first via hole 112 may be a conductor having the largest thickness. In the current path of the third signal line 130, the third via 132 may be a conductor having the largest thickness. Therefore, the impedance between the vertical current paths (e.g., the current path between the first segment 111 and the first ball grid array pad 113 and the current path between the third segment 131 and the third ball grid array pad 133) of the first differential wire pair DP1 can be close to the impedance between the horizontal current paths (e.g., the current path of the first segment 111 and the current path of the third segment 131) by adjusting the fourth distance L4 so that the parasitic capacitance between the first via 112 and the third via 132 can be increased.

In the embodiment, the center 113C of the first ball grid array pad 113 and the center 112C of the first via 112 do not overlap in a top view, and the center 133C of the third ball grid array pad 133 and the center 132C of the third via 132 do not overlap in a top view, but the invention is not limited thereto.

Also for example, a connection line between the center 123C of the second ball grid array pad 123 and the center 143C of the fourth ball grid array pad 143 has a fifth distance L5, a connection line between the center 122C of the second via 122 and the center 142C of the fourth via 142 has a sixth distance L6, and the sixth distance L6 is less than the fifth distance L5. The second via 122 may be a conductor having a maximum thickness in a current path of the second signal line 120. In the current path of the fourth signal line 140, the fourth via 142 may be a conductor having the largest thickness. Therefore, the impedance between the vertical current paths (e.g., the current path between the second line segment 121 and the second ball grid array pad 123 and the current path between the fourth line segment 141 and the fourth ball grid array pad 143) of the second differential trace pair DP2 can be close to the impedance between the horizontal current paths (e.g., the current path of the second line segment 121 and the current path of the fourth line segment 141) by adjusting the sixth distance L6, so that the parasitic capacitance between the second via 122 and the fourth via 142 can be increased.

In the present embodiment, the center 123C of the second ball grid array pad 123 and the center 122C of the second via 122 do not overlap, and the center 143C of the fourth ball grid array pad 143 and the center 142C of the fourth via 142 do not overlap, but the invention is not limited thereto.

Fig. 5 shows a schematic top view of a part of a wiring structure according to a second embodiment of the present invention. The circuit structure 200 of the present embodiment is similar to the circuit structure 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or forming manners, and descriptions thereof are omitted.

The circuit structure 200 of the present embodiment is similar to the circuit structure 100 of the first embodiment, with the difference that: the line structure 200 may further include a ground via 250.

The ground via 250 is disposed between the first signal line 110 and the second signal line 120. The ground vias 250 may be shield ground (shield ground) or electrically connected to ground. The ground vias 250 penetrate the core layer 160. The ground vias 250 may be solid conductive pillars or hollow plated vias, but the invention is not limited thereto.

In the present embodiment, the ground via 250 is disposed on a connecting line between the center 112C of the first via 112 and the center 122C of the second via 122 in a top view. As a result, when the circuit structure 200 is used for high-frequency signal transmission, the signal interference between the first signal line 110 and the second signal line 120 can be further reduced.

In this embodiment, the ground vias 250 may not have conductive terminals thereon (not shown because they are not).

Comparative example and test example

In order to prove that the circuit structure of the present invention can improve the signal transmission quality of high frequency signals, a description will be given of a comparative example and a test example in a software simulation manner. However, these test examples are not to be construed in any way as limiting the scope of the present invention.

Test example 1a simulation was performed with the circuit structure 100 of the first embodiment. Test example 2 a simulation was performed with the circuit structure 200 of the second embodiment.

The circuit structure 600 of the comparative example includes a first signal line 610 and a second signal line 620. The first signal line 610 includes a first line segment 611, a first via 612, and a first ball grid array pad 113. The first through hole 612 is located between the first segment 611 and the first ball grid array pad 113, and the first through hole 612 is electrically connected to the first segment 611 and the first ball grid array pad 113. The second signal line 620 includes a second line segment 621, a second via 622, and a second ball grid array pad 123. The second via 622 is located between the second segment 621 and the second ball grid array pad 123, and the second via 622 is electrically connected to the second segment 621 and the second ball grid array pad 123. In a top view (as shown in fig. 6), a connection line between the center 113C of the first ball grid array pad 113 and the center 123C of the second ball grid array pad 123 has a first distance L1, a connection line between the center 612C of the first via 612 and the center 622C of the second via 622 has a seventh distance L7, and the first distance L1 is equal to the seventh distance L7. The first signal line 610 and the second signal line 620 do not have a ground via (e.g., a ground via similar to the ground via 250) therebetween.

Generally, the quality of signal transmission of two adjacent conductors can be described by the isolation of the signals they transmit. In terms of numerical description, the isolation may be expressed in decibels (dB). That is, in the description of the numerical values, the larger the absolute value (absolute value) of the isolation, the better the transmission quality of the signal.

In fig. 7, a broken line (dash line) may be an isolation of signals of different frequencies in a differential mode (differential mode) of at least one of the first signal line 610 or the second signal line 620 of the comparative example; the dash-dot line (dash-dot line) may be an isolation of signals of different frequencies in the differential mode in at least one of the first signal line 110 or the second signal line 120 of test example 1; the solid line (solid line) may be the isolation of signals of different frequencies in the differential mode in at least one of the first signal line 110 and the second signal line 120 of test example 2.

As shown in fig. 7, the circuit structure 100 of test example 1 and the circuit structure 200 of test example 2 can have better transmission quality in signal transmission compared to the circuit structure 600 of the comparative example.

Generally, the signal transmission performance of a conductor can be described by the insertion loss (insertionloss) and return loss (return loss) of the signal transmitted by the conductor. In terms of numerical description, the insertion loss and the return loss can be expressed in decibels. That is, in the description of the numerical values, the smaller the absolute value of the insertion loss, the better the transmission quality of the signal, and the larger the absolute value of the return loss, the better the transmission quality of the signal.

In fig. 8, a dashed line (dash line) may be return loss of a signal of a different frequency in a differential mode (differential mode) of at least one of the first signal line 610 or the second signal line 620 of the comparative example; the solid line (solidline) may be at least one of the first signal line 110 or the second signal line 120 of test example 2, and return loss of signals of different frequencies in the differential mode; the dotted line (dot line) may be insertion loss of a signal of a different frequency in the differential mode of at least one of the first signal line 610 or the second signal line 620 of the comparative example; the dash-dot line (dash-dot line) may be insertion loss of signals of different frequencies in the differential mode in at least one of the first signal line 110 and the second signal line 120 of test example 2.

As shown in fig. 8, the circuit structure 200 of test example 2 may have better transmission quality in signal transmission than the circuit structure 600 of the comparative example.

In summary, the circuit structure and the chip package having the same of the present invention can have better signal transmission quality.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.