阅读说明：本技术 Dfn5×6双基岛芯片封装结构 (DFN5 x 6 double-base island chip packaging structure ) 是由 胡斌 吴建国 吴兵 胡宇辰 于 2020-07-01 设计创作，主要内容包括：本发明公开了DFN5×6双基岛芯片封装结构,包括封装框架,封装框架的上表面固定设置有基岛A,封装框架的下表面固定设置有基岛B,封装框架一侧的左边固定设置有P1端口,P1端口的一侧固定开设有P2端口,P2端口的一侧固定开设有P3端口,P3端口的一侧固定开设有P4端口,P4端口的一侧固定设置有P5端口,封装框架另一侧的右边固定开设有P6端口,P6端口的一侧固定设置有P7端口,P7端口的一侧固定开设有P8端口,P8端口的一侧固定连接有P9端口,该DFN5×6双基岛芯片封装结构,实现高压输出,可以获取更低的导通电阻,保证了爬电距离的安全距离,具有良好的电气性能、良好的散热效果,以及采用双基岛结构无需叠封,可省去DAF膜,增加可靠性,降低成本。(The invention discloses a DFN5 multiplied by 6 double-base-island chip packaging structure, which comprises a packaging frame, wherein a base island A is fixedly arranged on the upper surface of the packaging frame, a base island B is fixedly arranged on the lower surface of the packaging frame, a P1 port is fixedly arranged on the left side of one side of the packaging frame, a P2 port is fixedly arranged on one side of a P1 port, a P3 port is fixedly arranged on one side of a P2 port, a P4 port is fixedly arranged on one side of a P3 port, a P5 port is fixedly arranged on one side of a P4 port, a P6 port is fixedly arranged on the right side of the other side of the packaging frame, a P7 port is fixedly arranged on one side of a P6 port, a P8 port is fixedly arranged on one side of a P7 port, a P9 port is fixedly connected to one side of a P8 port, and the DFN5 multiplied by 6 double-base-island chip packaging structure realizes high-voltage output, The heat dissipation effect is good, the double-base-island structure is adopted, overlapping sealing is not needed, a DAF film can be omitted, the reliability is improved, and the cost is reduced.)

The DFN5 × 6 double-base-island chip packaging structure comprises a packaging frame (1), and is characterized in that: the packaging structure is characterized in that a base island A (2) is fixedly arranged on the upper surface of the packaging frame (1), a base island B (3) is fixedly arranged on the lower surface of the packaging frame (1), four second pins (9) are symmetrically arranged on one side of the base island A (2), and five first pins (8) are symmetrically arranged on one side of the base island B (3).

2. The DFN5 x 6 dual base island chip package structure of claim 1, wherein: the fixed P1 port (11) that is provided with in the left side of encapsulation frame (1) one side, P2 port (12) have been seted up to one side of P1 port (11) is fixed, P3 port (13) have been seted up to one side of P2 port (12), P4 port (14) have been fixed seted up to one side of P3 port (13), one side of P4 port (14) is fixed and is provided with P5 port (15), P1 port (11) and P5 port (15) all present the L form, P2 port (12) and P4 port (14) are located the bottom of base island B (3).

3. The DFN5 x 6 dual base island chip package structure of claim 1, wherein: the right side of the other side of the packaging frame (1) is fixedly provided with a P6 port (16), one side of the P6 port (16) is fixedly provided with a P7 port (17), one side of the P7 port (17) is fixedly provided with a P8 port (18), and one side of the P8 port (18) is fixedly connected with a P9 port (19).

4. The DFN5 x 6 dual base island chip package structure of claim 1, wherein: silver-plated regions (4) are fixedly arranged on the surfaces of the base island A (2) and the base island B (3), and half-etched regions (5) are fixedly arranged on the four sides of the base island A (2) and the other surface of the base island B (3).

5. The DFN5 x 6 dual base island chip package structure of claim 4, wherein: the right side of the silver plating area (4) is fixedly provided with an MOSFET (metal oxide semiconductor field effect transistor) (6), and the surface of the base island B (3) is fixedly provided with a main control chip (7).

6. The DFN5 x 6 dual base island chip package structure of claim 4, wherein: the distance between the base island A (2) and the base island B (3) is not less than 0.25mm, the minimum distance between a non-half etching area on the other surface of the base island A (2) and non-half etching areas of the P1 port (11), the P2 port (12), the P3 port (13), the P4 port (14) and the P5 port (15) is not less than 1.8mm, and the base island B (3) and the P3 port (13) are integrated.

Technical Field

The invention relates to the technical field of electronic information automatic component manufacturing, in particular to a DFN5 multiplied by 6 double-base-island chip packaging structure.

Background

The DFN package is a surface mount package technology, a large-area exposed bonding pad is positioned at the center of the bottom of the package, and has an excellent heat conduction effect, a conductive bonding pad for realizing electrical connection is arranged at the periphery of the large-area package, the conductive path between the inner pin and the bonding pad is short, the self-inductance and the wiring resistance in the package are very low, so that the DFN package can provide excellent electrical performance, and in addition, the DFN package also provides excellent heat dissipation performance through the exposed bonding pad of the lead frame, and the bonding pad has a direct heat dissipation channel for releasing heat in the package.

However, the existing DFN package has the following problems that the main control chip and the high-voltage power device cannot be sealed due to insufficient creepage distance, high-voltage output cannot be realized, the distance between the ports also causes interference between electrical properties, and no good electrical performance and good heat dissipation effect exist. However, in the conventional DFN, the dual chip package is realized by using the stack package technology, which increases the cost and reduces the reliability.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a DFN5 multiplied by 6 double-base island chip packaging structure, which solves the problems that a main control chip and a high-voltage power device cannot be sealed and cannot realize high-voltage output due to insufficient creepage distance, the distance between ports can also cause electric interference, no good electric performance exists, and a good heat dissipation effect is achieved. And the common DFN adopts the overlapping packaging technology to realize the double-chip packaging, which increases the cost and reduces the reliability.

In order to achieve the purpose, the invention is realized by the following technical scheme: the DFN5 multiplied by 6 double-base-island chip packaging structure comprises a packaging frame, wherein a base island A is fixedly arranged on the upper surface of the packaging frame, a base island B is fixedly arranged on the lower surface of the packaging frame, four second pins are symmetrically arranged on one side of the base island A, and five first pins are symmetrically arranged on one side of the base island B.

Preferably, a P1 port is fixedly disposed on the left side of one side of the package frame, a P2 port is fixedly disposed on one side of the P1 port, a P3 port is fixedly disposed on one side of the P2 port, a P4 port is fixedly disposed on one side of the P3 port, and a P5 port is fixedly disposed on one side of the P4 port.

Preferably, a P6 port is fixedly formed on the right of the other side of the package frame, a P7 port is fixedly formed on one side of the P6 port, a P8 port is fixedly formed on one side of the P7 port, and a P9 port is fixedly connected to one side of the P8 port.

Preferably, silver-plated regions are fixedly arranged on the surfaces of the base island a and the base island B, and half-etched regions are fixedly arranged on the four sides of the base island a and the other surfaces of the base island B and the five ports P1 to P5.

Preferably, the MOSFET is fixedly arranged on the right side of the silver plating area, and the main control chip is fixedly arranged on the surface of the base island B.

Preferably, the distance between the base island A and the base island B is not less than 0.25mm, the minimum distance between the non-half etching area on the other surface of the base island A and the non-half etching area of the P1 port, the P2 port, the P3 port, the P4 port and the P5 port is not less than 1.8mm, the P1 port and the P5 port are L-shaped, the P2 port and the P4 port are located at the bottom of the base island B, and the base island B and the P3 port are integrated.

Advantageous effects

The invention provides a DFN5 multiplied by 6 double-base island chip packaging structure. Compared with the prior art, the method has the following beneficial effects:

1. according to the DFN5 multiplied by 6 double-base-island chip packaging structure, the distance between the base island A and the base island B is not less than 0.25mm, the minimum distance between the non-half etching area on the other surface of the base island A and the non-half etching areas of the P1 port, the P2 port, the P3 port, the P4 port and the P5 port is not less than 1.8mm, and the safety distance of the creepage distance is ensured and the output of high voltage is realized through the distance between the base island A and the base island B and the distance between the exposed part of the base island A and the pins.

2. According to the DFN5 multiplied by 6 double-base-island chip packaging structure, the P1 port and the P5 port are both L-shaped, the leading-out of a plurality of leads from an MOSFET on a base island A to the P1 port or the P5 port pin can be facilitated through the L-shaped design of the P1 port and the P5 port, so that lower on-resistance is obtained, the double-base-island structure is adopted, overlapping sealing is not needed, a DAF (digital optical filter) film can be omitted, reliability is improved, and cost is reduced

3. According to the DFN5 multiplied by 6 double-base-island chip packaging structure, the lower surface of a packaging frame is fixedly provided with a base island B, one side of a P2 port is fixedly provided with a P3 port, and the base island B and a middle lead P3 port are connected into a whole, so that the advantage that wire bonding from a main control chip on the base island B to each first pin and a power device on the base island B is short, and good electrical performance is convenient to obtain.

4. According to the DFN5 × 6 double-base-island chip packaging structure, the P2 port and the P4 port are located at the bottom of the base island B, and the P2 port and the P4 port are located below the base island B through pins, so that the base island B can be wider in width, and a larger main control chip can be compatible.

5. The DFN 5X 6 double-base island chip packaging structure is characterized in that a P1 port is fixedly arranged on the left side of one side of a packaging frame, a P2 port is fixedly arranged on one side of a P1 port, a P3 port is fixedly arranged on one side of the P2 port, a P4 port is fixedly arranged on one side of a P3 port, a P5 port is fixedly arranged on one side of a P4 port, a P6 port is fixedly arranged on the right side of the other side of the packaging frame, a P7 port is fixedly arranged on one side of a P6 port, a P8 port is fixedly arranged on one side of a P7 port, a P9 port is fixedly connected to one side of the P8 port, and the P1 port, the P2 port, the P3 port, the P4 port and the P5 port of the other side of the same side can provide more functions, the P6 port, the P7 port, the P8 port and the P9 port of the other side of the high-voltage pin are connected with a base, and a good creepage distance with all low-voltage pins is ensured.

6. According to the DFN5 multiplied by 6 double-base-island chip packaging structure, the base island A is fixedly arranged on the upper surface of a packaging frame, the base island B is fixedly arranged on the lower surface of the packaging frame, the double-base-island packaging structure has the advantages that the DFN packaging structure is thinner, a main control chip and a MOSFET are respectively arranged on different base islands, the reliability is high, in addition, DAF films are not needed in the packaging process, and the cost is lower.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic view of a silver-plating area of the structure of the present invention;

FIG. 3 is a schematic view of a structural half-etch region of the present invention;

FIG. 4 is a schematic diagram of a MOSFET and a main control chip according to the present invention.

In the figure: 1. a package frame; 11. a P1 port; 12. a P2 port; 13. a P3 port; 14. A P4 port; 15. a P5 port; 16. a P6 port; 17. a P7 port; 18. a P8 port; 19. a P9 port; 2. a base island A; 3. a base island B; 4. a silver plating region; 5. a half-etching region; 6. a MOSFET; 7. a main control chip; 8. a first pin; 9. a second pin.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-4, the present invention provides a technical solution: the DFN5 × 6 dual-base-island chip packaging structure comprises a packaging frame 1, wherein a base island A2 is fixedly arranged on the upper surface of the packaging frame 1, a base island B3 is fixedly arranged on the lower surface of the packaging frame 1, four second pins 9 are symmetrically arranged on one side of the base island A2, five first pins 8 are symmetrically arranged on one side of a base island B3, a P1 port 11 is fixedly arranged on the left side of one side of the packaging frame 1, a P2 port 12 is fixedly arranged on one side of the P1 port 11, a P3 port 13 is fixedly arranged on one side of the P2 port 12, a P4 port 14 is fixedly arranged on one side of the P3 port 13, a P5 port 15 is fixedly arranged on one side of the P4 port 14, a P6 port 16 is fixedly arranged on the right side of the other side of the packaging frame 1, a P7 port 17 is fixedly arranged on one side of the P6 port 16, a P7 port 18 is fixedly arranged on one side of the P8 port 17, and, the surfaces of the base island A2 and the base island B3 are fixedly provided with silver-plated regions 4, four sides of the base island A2 and the other surface of the base island B3 are fixedly provided with half-etched regions 5, the right side of each silver-plated region 4 is fixedly provided with a MOSFET 6, a main control chip 7 is placed on the surface of the base island B3, the distance between the base island A2 and the base island B3 is not less than 0.25mm, the minimum distance between a non-half-etched region on the other surface of the base island A2 and non-half-etched regions of a P1 port 11, a P2 port 12, a P3 port 13, a P4 port 14 and a P5 port 15 is not less than 1.8mm, the P1 port 11 and the P5 port 15 are L-shaped, and the P2 port 12 and the P4 port 14 are positioned at the bottom of the base island B3.

Firstly, through the L design presented by the P1 port 11 and the P5 port 15, leading-out of a plurality of leads from the MOSFET 6 on the surface of the base island a2 to the P1 port 11 and the P5 port 15 pins can be facilitated, the purpose is to obtain lower on-resistance, then through the mutual connection between the base island B3 and the middle P3 port 13, the distance from the main control chip 7 on the base island B3 to the first pin 8 and the connecting line between the power devices on the surface of the base island B3 are relatively disconnected, the purpose is to obtain good electrical performance, the P2 port 12 and the P4 port 14 are positioned below the base island B3, the width of the base island B3 can be made wider, the larger main control chip 7 can be compatible, the P1 port 11, the P2 port 12, the P3 port 13, the P4 port 14 and the P5 port 15 opened on one side of the package frame 1 can provide more functions, and the P6 port 16 and the P7 port 15 on the other side of the package frame 1, The electrical connection of the P8 port 18 and the P9 port 19 with the base island a2 and the connection of the second pin 9 with the base island a2, which aims to achieve good heat dissipation effect, and the P1 port 11, the P2 port 12, the P3 port 13, the P4 port 14, the P5 port 15, the P6 port 16, the P7 port 17, the P8 port 18, and the P9 port 19 are separately arranged on both sides of the package frame 1, so as to ensure that all the P1 port 11, the P2 port 12, the P3 port 13, the P4 port 14, and the P5 port 15 have good creepage distances, and in the installation separated by the base island a2 and the base island B3, which aims to make the package frame 1 for installing the DFN package thinner and lower cost.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation. The use of the phrase "comprising one of the elements does not exclude the presence of other like elements in the process, method, article, or apparatus that comprises the element.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.