阅读说明：本技术 半导体封装及其制造方法 (Semiconductor package and method of manufacturing the same ) 是由 陈政远 李基铭 陈俊辰 余远灏 于 2019-10-28 设计创作，主要内容包括：一种半导体封装包含衬底、预制馈电元件、预制屏蔽元件和封装体。所述预制馈电元件设置在所述衬底上,并且所述预制馈电元件设置在所述衬底上并与所述预制馈电元件相邻。所述封装体封装所述预制馈电元件和所述预制屏蔽元件。(A semiconductor package includes a substrate, a prefabricated feed element, a prefabricated shield element, and a package body. The pre-formed feeding element is disposed on the substrate and disposed on and adjacent to the substrate. The package encapsulates the pre-formed feeding element and the pre-formed shielding element.)

1. A semiconductor package, comprising:

a substrate;

a pre-formed feeding element disposed on the substrate;

a pre-formed shielding element disposed on the substrate and adjacent to the pre-formed feeding element; and

an encapsulation encapsulating the pre-formed feeding element and the pre-formed shielding element.

2. A semiconductor package as claimed in claim 1, wherein the package includes a first space housing the pre-formed feeding element and a second space housing the pre-formed shielding element, the first space being bounded by the pre-formed feeding element and the second space being bounded by the pre-formed shielding element.

3. The semiconductor package of claim 1, wherein the package contains a filler and the filler adjacent to the preformed feed element and the preformed shield element is intact.

4. The semiconductor package of claim 1, wherein the pre-formed shielding element surrounds the pre-formed feeding element.

5. The semiconductor package of claim 4, wherein the pre-fabricated shielding element includes at least one opening.

6. The semiconductor package of claim 4, wherein the prefabricated shielding element includes a plurality of nubs spaced apart from one another.

7. The semiconductor package of claim 1, further comprising an antenna layer disposed adjacent to and electrically connected to the pre-formed feeding element and the pre-formed shielding element.

8. The semiconductor package of claim 7, further comprising a connector disposed on the pre-formed feeding element and the pre-formed shielding element to connect the pre-formed feeding element and the pre-formed shielding element to the antenna layer.

9. The semiconductor package of claim 1, further comprising a semiconductor component and a compartment disposed on the substrate, the semiconductor component and the pre-formed feed element being separated by the compartment.

10. The semiconductor package of claim 9, further comprising a shielding layer disposed on the package body to electrically connect to the compartment.

11. A semiconductor package, comprising:

a substrate; and

an RF structure disposed on the substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element;

wherein a spacing from the feeding element to the shielding element is about 1000 μm to about 1500 μm, wherein an insertion loss ≧ 0.5dB at about 0.5GHz to about 70 GHz.

12. The semiconductor package of claim 11, wherein the pitch is about 1000 μ ι η to about 1200 μ ι η.

13. The semiconductor package of claim 11, wherein the pitch is about 1300 μm to about 1500 μm, wherein the insertion loss is ≧ 0.5dB at about 0.5GHz to about 60 GHz.

14. The semiconductor package of claim 11, wherein the shielding element surrounds the feeding element.

15. A semiconductor package, comprising:

a substrate; and

an RF structure disposed on the substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element;

wherein the spacing from the feeding element to the shielding element is about 1000 μm to about 1500 μm, wherein the return loss is ≦ -10dB at about 0.5MHz to about 80 MHz.

16. The semiconductor package of claim 15, wherein the spacing from the feeding element to the shielding element is about 1300 μm to 1500 μm, wherein the return loss ≦ -10dB at about 0.5MHz to about 60 MHz.

17. The semiconductor package of claim 15, wherein the shielding element surrounds the feeding element.

18. A semiconductor package, comprising:

a substrate; and

an RF structure disposed on the substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element;

wherein a pitch from the feeding element to the shielding element is about 0 μm < pitch ≦ 800 μm, wherein an insertion loss ≧ 0.5dB at about 60GHz to about 75 GHz.

19. The semiconductor package of claim 18, wherein the shielding element surrounds the feeding element.

20. A semiconductor package, comprising:

a substrate; and

an RF structure disposed on the substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element;

wherein the spacing from the feeding element to the shielding element is about 0 μm < spacing ≦ 800 μm, wherein the return loss is ≦ -10dB from about 0.5MHz to about 80 MHz.

21. The semiconductor package of claim 20, wherein the shielding element surrounds the feeding element.

22. A method of manufacturing a semiconductor package, comprising:

forming an RF structure on a substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element; and

molding the substrate, the feeding element and the shielding element to form a package.

23. The method of claim 22, further comprising:

exposing the RF structure from the package; and

an antenna layer is provided on the RF structure.

24. The method of claim 22, further comprising:

a connector is disposed on the RF structure to connect the RF structure to the antenna layer.

25. The method of claim 22, wherein the package contains a filler and encapsulates the substrate, the feeding element, and the shielding element.

Technical Field

The present disclosure relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including at least two semiconductor components and a method of manufacturing the same.

Background

It has been desirable to incorporate more than one semiconductor component into a single semiconductor package to reduce the size of the package. A semiconductor package incorporating a plurality of semiconductor components may be referred to as a System In Package (SiP). Because the semiconductor devices in a semiconductor package require electrical connections to the external environment, such electrical connections and their fabrication processes are important in determining whether the semiconductor devices are functioning properly or achieving desired performance.

Disclosure of Invention

In one embodiment, a semiconductor package includes a substrate; prefabricating a feed element; prefabricating a shielding element; and a package body. The pre-formed feeding element is disposed on the substrate and the pre-formed feeding element is disposed on the substrate adjacent the pre-formed feeding element. An encapsulant encapsulates the preformed feed element and the preformed shield element.

In one embodiment, a semiconductor package includes a substrate and an RF structure. The RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a spacing from the feeding element to the shielding element is about 1000 μm to about 1500 μm, and wherein an insertion loss ≧ 0.5dB at about 0.5GHz to about 70 GHz.

In one embodiment, a semiconductor package includes a substrate and an RF structure. An RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a spacing from the feeding element to the shielding element is about 1000 μm to about 1500 μm, and wherein a return loss ≦ -10dB at about 0.5MHz to about 80 MHz.

In one embodiment, a semiconductor package includes a substrate and an RF structure. The RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a spacing from the feeding element to the shielding element is about 0 μm < the spacing ≦ about 800 μm, and an insertion loss ≧ 0.5dB at about 60GHz to about 75 GHz.

In one embodiment, a semiconductor package includes a substrate and an RF structure. An RF structure is disposed on the substrate and includes a feeding element and a shielding element adjacent to the feeding element, wherein a spacing from the feeding element to the shielding element is about 0 μm < spacing ≦ about 800 μm, and wherein a return loss of ≦ -10dB at about 0.5MHz to about 80 MHz.

In one embodiment, a method of manufacture includes (a) forming an RF structure on a substrate, the RF structure including a feeding element and a shielding element adjacent to the feeding element; and (b) a molded substrate, a feeding element, and a shielding element.

Drawings

Fig. 1(a) illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 1(b) illustrates a top view of the second semiconductor component of fig. 1(a) along line a-a according to one embodiment of the present disclosure.

Fig. 1(c) illustrates an enlarged view of region B of the embodiment of the second semiconductor assembly shown in fig. 1 (a).

Fig. 2 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 3(a) illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 3(b) illustrates an enlarged view of region C of the conductive via of the embodiment of the third semiconductor component shown in fig. 3 (a).

Fig. 3(c) illustrates an enlarged view of region D of the embodiment of the second semiconductor assembly shown in fig. 3 (a).

Fig. 4 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 5 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 6 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 7 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 8 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 9 illustrates a cross-sectional view of a semiconductor package according to one embodiment of the present disclosure.

Fig. 10(a) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 10(b) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 11(a) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 11(b) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 11(c) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 11(d) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 11(e) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure.

Fig. 12(a) -12(b) illustrate a method for manufacturing a semiconductor package, such as the semiconductor package of fig. 1 (a).

Fig. 12(a) -12(c) illustrate a method for manufacturing a semiconductor package, such as the semiconductor package of fig. 3 (a).

Fig. 12(a) -12(d) illustrate a method for manufacturing a semiconductor package, such as the semiconductor package of fig. 4.

Fig. 12(a) -12(e) illustrate a method for manufacturing a semiconductor package, such as the semiconductor package of fig. 5.

Fig. 12(a) -12(f) illustrate a method for manufacturing a semiconductor package (e.g., the semiconductor package of fig. 7).

Detailed Description

Unless otherwise specified, spatial descriptions are indicated with respect to the orientations shown in the figures, such as "top," "side," "above … …," and the like. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner so long as the advantages of the embodiments of the present disclosure are not detracted from the arrangement.

Fig. 1(a) illustrates a cross-sectional view of a semiconductor package 100 according to one embodiment of the present disclosure. The semiconductor package 100 includes a substrate 101, a first semiconductor component 102, a second semiconductor component 104, and a package 106.

The substrate 101 has a first surface 101a, a second surface 101b, and a side surface 101 c. The first surface 101a is opposite to the second surface 101 b. The side surface 101c extends between the first surface 101a and the second surface 101 b. In the embodiment shown in fig. 1(a), the substrate 101 comprises at least one bond pad 114 disposed adjacent to the first surface 101a of the substrate 101. The bond pads 114 may be contact pads such as traces. In the embodiment of fig. 1(a), the first surface 101a is an active surface, the bond pads 114 are contact pads, and the bond pads 114 are disposed directly on (e.g., in physical contact with) the first surface 101a of the substrate 101. Bond pad 114 can comprise, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, other metals, metal alloys, or combinations of two or more thereof.

The first semiconductor component 102 is disposed on the first surface 101a of the substrate 101. The first semiconductor component 102 may be any semiconductor component including, for example, a chip, a package, an interposer, or a combination thereof. In the embodiment shown in fig. 1(a), the first semiconductor component 102 is a chip that includes at least one electrically conductive connector 112. The first conductive connector 112 contacts the bonding pad 114. The conductive connectors 112 may be, for example, pillar structures, which may include an Under Bump Metallization (UBM) layer, a pillar, a barrier layer, a solder layer, or a combination of two or more thereof, or a solder/pillar bump.

The second semiconductor component 104 is disposed on the first surface 101a of the substrate 101. The second semiconductor device 104 may be any semiconductor device including, for example, an RF structure. The RF structure may comprise at least one feeding element and at least one shielding element. In accordance with the present disclosure, the feeding element and the shielding element are preformed such that their properties may be predetermined and formed into any desired shape, including, for example, a square-like shape, a triangular-like shape, a circular-like shape, a rectangular-like shape, a pentagonal-like shape, a hexagonal-like shape, a heptagonal-like shape, an octagonal-like shape, a trapezoidal-like shape, an elliptical-like shape, a rhomboid shape, or a parallelogram-like shape cylinder. Unlike feed or shield or ground vias formed by photolithography in combination with etching (or drilling) and plating on a substrate, where the shape of the via is entirely dependent on the drilling or etching technique and the nature of the via is entirely dependent on the plating technique, feed and shield elements according to embodiments of the present disclosure are prefabricated, for example by molding, where their shape and nature can be controlled. Therefore, voids in the feed or shield or ground vias caused by plating can be avoided, which can reduce signal loss.

In the embodiment shown in fig. 1(a), the second semiconductor component 104 comprises at least one pre-formed feeding element 104b disposed on the first surface 101a of the substrate 101 and at least one pre-formed shielding element 104a, 104c disposed on the first surface 101a of the substrate 101 and adjacent to the pre-formed feeding element 104 b. The pre-formed feeding element 104b and the pre-formed shielding elements 104a, 104c are spaced apart from each other by a distance. The shield elements 104a, 104c may comprise a plurality of small pieces 104a, 104c spaced apart from each other. The feeding element 104b and the shielding elements 104a, 104c may be disposed on the substrate 101 by Surface Mount Technology (SMT). In the embodiment shown in fig. 1, the feeding element 104b and the shielding elements 104a, 104c are provided on the substrate 101 with solder paste 110 by Surface Mount Technology (SMT).

The package 106 is disposed between the first semiconductor component 102 and the second semiconductor component 104. An encapsulation 106 encapsulates the prefabricated feeding element 104b and the prefabricated shielding elements 104a, 104 c. In the embodiment shown in fig. 1(a), the pre-formed feeding element 104b defines a first space in the package 106 and the pre-formed shielding elements 104a, 104c define a second space in the package 106, wherein the package 106 surrounds them and accommodates the first space and the second space. The encapsulation 106 may extend from the prefabricated shielding element 104a to the first semiconductor assembly 102. The package 106 may cover the first semiconductor assembly 102, the prefabricated feeding element 104b, the prefabricated shielding elements 104a, 104c and the first surface 101a of the substrate 101, but not the side surface 101c of the substrate 101. The package 106 may be, for example, a solder mask (whose material is, for example, Polyimide (PI)), a passivation layer (whose material is, for example, metal oxide), or an underfill. The package body 106 may contain a filler, the material of which is, for example, silicon dioxide and/or carbon, for reducing stress on the die and warpage of the resulting semiconductor package.

Fig. 1(b) illustrates a top view of the second semiconductor component 104 of fig. 1(a) along the a-a line, according to one embodiment of the present disclosure. The second semiconductor component 104 comprises a feeding element 104b and a shielding element 104a, 104 c. The shielding elements 104a, 104c surround the feeding element 104 b. The shielding elements 104a, 104c comprise two small pieces 104a, 104c spaced apart from each other and containing at least one opening between them. The shielding elements 104a, 104c are disposed adjacent to the feeding element 104b and on opposite sides of each other. The distance X (pitch) from the center of the shielding elements 104a, 104c to the center of the feeding element 104b is determined according to the desired properties of the second semiconductor component 104.

In one embodiment of the present disclosure, for an RF structure, the spacing X may be about 1000 μm to about 1500 μm, with an insertion loss ≧ 0.5dB at about 0.5GHz to about 70 GHz.

In one embodiment of the present disclosure, for an RF structure, the spacing X may be about 1000 μm to about 1200 μm, with an insertion loss ≧ 0.5dB at about 0.5GHz to about 70 GHz.

In one embodiment of the present disclosure, for an RF structure, the spacing X may be about 1300 μm to about 1500 μm, with an insertion loss ≧ 0.5dB at about 0.5GHz to about 70 GHz.

In one embodiment of the present disclosure, for RF configurations, the spacing X can be about 1000 μm to about 1500 μm, with a return loss ≦ -10dB at about 0.5MHz to about 80 MHz.

In one embodiment of the present disclosure, the spacing X can be about 1300 μm to 1500 μm, with a return loss ≦ -10dB at about 0.5MHz to about 60 MHz.

In one embodiment of the present disclosure, the pitch X may be about 0 μm < pitch ≦ 800 μm, where the insertion loss ≧ 0.5dB at about 60GHz to about 75 GHz.

In one embodiment of the present disclosure, the pitch X may be about 0 μm < pitch ≦ 800 μm, with return loss ≦ -10dB at about 60MHz to about 80 MHz.

The feeding element 104b and the shielding elements 104a, 104c are all surrounded by a package 106. The feeding element 104b and the shielding elements 104a, 104c may have different shapes depending on the molding technique or techniques used to form them. In the embodiment shown in fig. 1(b), the outer boundary of the feeding element 104b is similar to the outer boundary of the shielding element 104a, and the outer boundary of the shielding element 104a may be similar to the outer boundary of the opposing shielding element 104 c. In the embodiment shown in fig. 1(b), the feeding element 104b and the shielding elements 104a, 104c have a circular-like cylindrical shape.

Fig. 1(c) illustrates an enlarged view of region B of the embodiment of the second semiconductor component 104 shown in fig. 1 (a). In the embodiment shown in fig. 1(c), the package 106 contains a filler 122. The filler 122 is adjacent to the feeding element 104b and the shielding elements 104a, 104 c. The filler 122 may be of regular or irregular shape. In the embodiment shown in fig. 1(c), the shape of the filler 122 remains intact because the feeding element 104b and the shielding elements 104a, 104c are pre-fabricated according to embodiments of the present disclosure, rather than being formed by photolithography in combination with etching (or drilling) and plating. Therefore, the filler 122 in the package body 106 is not damaged by etching or drilling, and the shape thereof may be maintained intact. Thus, the effects of the filler 122, such as reducing stress on the die and warpage of the resulting semiconductor package, will not be affected and may be preserved.

Fig. 2 illustrates a cross-sectional view of a semiconductor package 200 according to one embodiment of the present disclosure. The semiconductor package 200 in fig. 2 is similar to the semiconductor package 100 in fig. 1, except that the semiconductor package 200 includes a first package 216 and a second package 206. The first package 216 is adjacent to the second package 206. The first package body 216 encapsulates the second semiconductor element 204. In particular, the first encapsulation 216 covers the prefabricated feeding element 204b, the prefabricated shielding elements 204a, 204c and the first surface 201a of the substrate 201, but does not cover the side surface 201c of the substrate 201. The second package body 206 covers the first semiconductor assembly 202 and the first surface 201a of the substrate 201, but does not cover the side surface 201c of the substrate 201. The first package 216 and the second package 206 are composed of different materials. The first package body 216 and the second package body 206 may contain fillers, the materials of which are, for example, silicon dioxide and/or carbon, for reducing stress on the die and warpage of the resulting semiconductor package.

Fig. 3(a) illustrates a cross-sectional view of a semiconductor package 300 according to one embodiment of the present disclosure. The semiconductor package 300 in fig. 3 is similar to the semiconductor package 100 in fig. 1, except that the semiconductor package 300 further includes a third semiconductor component 318 disposed in the package body 306. The third semiconductor assembly 318 is disposed between the first semiconductor assembly 302 and the second semiconductor assembly 304. The third semiconductor component 318 may be, for example, a compartment separating the first semiconductor component 302 from the second semiconductor component 304, or a conductive via. In the embodiment shown in fig. 3(a), the third semiconductor component 318 is a conductive via that extends through the package 306 from the substrate 308 to the surface of the package 306 and is formed by drilling (or etching) and plating.

Fig. 3(b) illustrates an enlarged view of region C of the conductive via 318 of the embodiment of the third semiconductor component 318 shown in fig. 3 (a). Fig. 3(c) illustrates an enlarged view of region D of the embodiment of the second semiconductor component 304 shown in fig. 3 (a). Package 306 contains filler 320 adjacent conductive via 318 and filler 322 adjacent feeding element 304b and shielding elements 304a, 304 c. As described above with respect to fig. 1(c), the shape of the filler 322 adjacent to the feeding element 304b and the shielding elements 304a, 304c remains intact, and so do their effects. In contrast to those fillers 322 adjacent to the feeding element 304b and the shielding elements 304a, 304c, the fillers 320 adjacent to the conductive via 318 may not remain intact in shape because they are damaged by the drilling or etching process used to form the conductive via. Thus, the effect of the filler 320 adjacent to the via hole formed by the drilling or etching process will be reduced, for example, in reducing stress or warpage of the resulting semiconductor package. Thus, comparing the prefabricated semiconductor assemblies with the semiconductor assemblies formed by drilling (or etching) and plating, it is apparent that the packages adjacent thereto will differ in efficacy and deteriorate.

Fig. 4 illustrates a cross-sectional view of a semiconductor package 400 according to one embodiment of the present disclosure. The semiconductor package 400 in fig. 4 is similar to the semiconductor package 300 in fig. 3(a), except that the semiconductor package 400 includes a conductive layer 424 disposed on the package body 406. The conductive layer 424 covers the top surface 406a of the package 406, the side surfaces 406b, 406c of the package 406, the exposed surfaces of the second semiconductor component 404 (including the feeding element 404b and the shielding elements 404a, 404c), and the exposed surfaces of the third semiconductor component 418. Conductive layer 424 may be, for example, a shielding layer or a conformal shielding layer.

Fig. 5 illustrates a cross-sectional view of a semiconductor package 500 according to one embodiment of the present disclosure. The semiconductor package 500 in fig. 5 is similar to the semiconductor package 400 in fig. 4, except that a conductive layer 524 disposed on the package body 506 covers the top surface 506a of the package body 506, only one of the side surfaces 506b, 506c of the package body 506, the exposed surface of the third semiconductor component 518, but does not cover the exposed surface of the second semiconductor component 504 (including the feeding element 504b and the shielding elements 504a, 504 c).

Fig. 6 illustrates a cross-sectional view of a semiconductor package 600 according to one embodiment of the present disclosure. The semiconductor package 600 in fig. 6 is similar to the semiconductor package 300 in fig. 3(a), except that the semiconductor package 600 includes a connector 628 disposed on the package body 606. The connector 628 is disposed adjacent to the second semiconductor device 604. In the embodiment shown in fig. 6, the connector 628 is disposed over the feeding element 604b and the shielding elements 604a, 604 c. The connector 628 may be, for example, a connector for connecting to an antenna layer.

Fig. 7 illustrates a cross-sectional view of a semiconductor package 700 according to one embodiment of the present disclosure. The semiconductor package 700 in fig. 7 is similar to the semiconductor package 500 in fig. 5, except that the semiconductor package 700 includes a connector 728 disposed on the package body 706. The connector 728 is disposed adjacent to the second semiconductor assembly 704. In the embodiment shown in fig. 7, the connector 728 is disposed over the feeding element 704b and the shielding elements 704a, 704 c. The connector 728 may be, for example, a connector for connecting to an antenna layer.

Fig. 8 illustrates a cross-sectional view of a semiconductor package 800 according to one embodiment of the present disclosure. The semiconductor package 800 in fig. 8 is similar to the semiconductor package 700 in fig. 7, except that the semiconductor package 800 includes an antenna layer 830 disposed adjacent to and electrically connected to the feeding element 804b and the shielding elements 804a, 804 c. In the embodiment shown in fig. 8, the antenna layer 830 includes a second connector 832 connected to a first connector 828 disposed on the feeding element 804b and the shielding elements 804a, 804 c.

Fig. 9 illustrates a cross-sectional view of a semiconductor package 900 according to one embodiment of the present disclosure. The semiconductor package 900 in fig. 9 is similar to the semiconductor package 100 in fig. 1(a), except that the semiconductor package 900 includes a third semiconductor component 934 disposed on a substrate 908, and an encapsulation body 906 exposes the second semiconductor component 904 and the third semiconductor component 934. The third semiconductor component 934 is disposed on the first surface 901a of the substrate 901, and may be located on the same side or an opposite side of the second semiconductor component 904. The third semiconductor component 934 may be any semiconductor component including, for example, an RF structure, a chip, a package, an interposer, or a combination thereof. The third semiconductor component 934 may be the same as or different from the second semiconductor component 904. In the embodiment shown in fig. 9, the third semiconductor assembly 934 is an RF structure comprising at least one prefabricated feeding element 934b and at least one prefabricated shielding element 934a, 934c and is disposed on opposite sides of the second semiconductor assembly 904.

Fig. 10(a) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. The second semiconductor component 1004 includes one feeding element 1004b and four shielding elements 1004a, 1004c, 1004d, 1004 e. Four shielding elements 1004a, 1004c, 1004d, 1004e are disposed adjacent to the feeding element 1004 b. Four shielding elements 1004a, 1004c, 1004d, 1004e surround the feeding element 1004 b. The shield elements 1004a, 1004c, 1004d, 1004e include openings between each of the pieces 1004a, 1004c, 1004d, 1004 e. The four shield elements 1004a, 1004c, 1004d, 1004e are spaced apart from each other by a package 1006. The four shielding elements 1004a, 1004c, 1004d, 1004e may be arranged around the feeding element 1004b in any arrangement, such as square-like, circular-like, rectangular-like, trapezoidal-like, elliptical-like, rhomboid-like, or parallelogram-like. In the embodiment shown in fig. 10(a), four shielding elements 1004a, 1004c, 1004d, 1004e surround the feeding element 1004b in a circular-like arrangement.

Fig. 10(b) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. The second semiconductor component 1005 in fig. 10(b) is similar to the second semiconductor component 1004 in fig. 10(a), except that the second semiconductor component 1005 comprises eight shielding elements 1004a, 1004c, 1004d, 1004e, 1004f, 1004g, 1004h, 1004i disposed adjacent to the feeding element 1004 b. Eight shielding elements 1004a, 1004c, 1004d, 1004e, 1004f, 1004g, 1004h, 1004i are arranged in a circular-like shape around the feeding element 1004 b.

Fig. 11(a) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. The second semiconductor device 1104 in fig. 11(a) is similar to the second semiconductor device 104 in fig. 1(b), except that the shielding elements 1104a, 1104c are preformed into a rectangular-like pillar shape.

Fig. 11(b) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. The second semiconductor assembly 1105 in fig. 11(b) is similar to the second semiconductor assembly 1104 in fig. 11(a), with the difference that the second semiconductor assembly 1105 includes three shielding elements 1105a, 1105c, 1105d disposed adjacent to the feeding element 1105 b. Three shield elements 1105a, 1105c, 1105d surround the feed element 1105 b. Three shield elements 1105a, 1105c, 1105d may surround approximately 3/4 of the circumference of the feeding element 1105 b.

Fig. 11(c) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. Second semiconductor component 1107 in fig. 11(c) is similar to second semiconductor component 1105 in fig. 11(b), except that three shielding elements 1107a, 1107c, 1107d are in contact with each other, and there is no opening between each.

Fig. 11(d) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. The second semiconductor component 1109 in fig. 11(c) is similar to the second semiconductor component 1105 in fig. 11(b), with the difference that there are four shielding elements 1109a, 1109c, 1109d, 1109e surrounding the feeding element 1109 b. The four shielding elements 1109a, 1109c, 1109d, 1109e surround the feeding element 1109b in a square-like arrangement.

Fig. 11(e) illustrates a top view of a second semiconductor assembly in accordance with an embodiment of the present disclosure. The second semiconductor component 1111 in fig. 11(e) is similar to the second semiconductor component 1109 in fig. 11(d), except that four shielding elements 1111a, 1111c, 1111d, 1111e are in contact with each other, and there is no opening between each of them.

Fig. 12(a) -12(b) illustrate a method for manufacturing a semiconductor package, such as the semiconductor package 100 of fig. 1 (a). Fig. 12(a) -12(c) illustrate a method for manufacturing a semiconductor package, such as the semiconductor package 300 of fig. 3 (a). Fig. 12(a) -12(d) illustrate a method for manufacturing a semiconductor package, such as semiconductor package 400 of fig. 4. Fig. 12(a) -12(e) illustrate a method for manufacturing a semiconductor package, such as semiconductor package 500 of fig. 5. Fig. 12(a) -12(f) illustrate a method for manufacturing a semiconductor package, such as semiconductor package 700 of fig. 7.

Referring to fig. 12(a), a first semiconductor component 702 and a second semiconductor component 704 are provided on a substrate 701. The first semiconductor component 702 is a chip that includes at least one conductive connector 712. The second semiconductor component 704 is an RF structure that includes at least one feeding element 704b and at least one shielding element 704a, 704 c. The substrate 701 includes at least one bond pad 714. The shield member includes two small pieces 704a, 704 c. The feeding element 704b and the shielding elements 704a, 704c are pre-formed into a circular-like cylindrical shape by a moulding technique before being provided on the substrate 701. The pre-formed feeding element 704b and the pre-formed shielding element 704c are provided on the substrate 701 by Surface Mount Technology (SMT). The temperature of the SMT process is preferably controlled below about 200 ℃. In the SMT process, the operating temperature of solder paste 710 is preferably below about 200 ℃.

Referring to fig. 12B, a package 706 is disposed between the first semiconductor component 702 and the second semiconductor component 704 by, for example, molding. An encapsulation 706 encapsulates the first semiconductor assembly 702, the prefabricated feeding element 704b and the prefabricated shielding elements 704a, 704 c. An encapsulation 706 covers the first semiconductor assembly 702, the pre-formed feeding element 704b and the pre-formed shielding elements 704a, 704c, surrounds the pre-formed feeding element 704b and the pre-formed shielding elements 704a, 704c, and extends from the pre-formed shielding element 704a to the first semiconductor assembly 702. The package 706 may be, for example, a solder mask (whose material is, for example, Polyimide (PI)) or a passivation layer (whose material is, for example, metal oxide) or an underfill. The package 706 may contain a filler, the material of which is, for example, silicon dioxide and/or carbon.

Referring to fig. 12C, a third semiconductor component 718 is disposed in the package body 706. The third semiconductor assembly 718 is disposed between the first semiconductor assembly 702 and the second semiconductor assembly 704. The third semiconductor assembly 718 may be, for example, a compartment separating the first semiconductor assembly 702 from the second semiconductor assembly 704, or a conductive via. The package 706 defines locations for forming compartments or conductive vias. The compartments or conductive vias may be formed by drilling (or etching) and plating. Thus, as described above for package 706 containing filler adjacent to compartments or conductive vias 718, their shape cannot remain intact because they are damaged by the drilling or etching process and thus their effectiveness as filler in package 706 will be deteriorated.

Referring to fig. 12D, the package 706 is polished to expose the second semiconductor element 704. Subsequently, a separation technique (e.g., sawing) is performed to obtain individual semiconductor packages, such as the semiconductor package 300 of fig. 3 (a). A conductive layer 724 is disposed on the package body 706 by, for example, an electroplating technique, wherein it covers the top surface 706a of the package body 706, the side surfaces 706b, 706c of the package body 706, the exposed surfaces of the second semiconductor component 704 (including the feeding element 704b and the shielding elements 704a, 704c), and the exposed surfaces of the third semiconductor component 718. Conductive layer 724 can be, for example, a shielding layer or a conformal shielding layer.

Referring to fig. 12E, a conductive layer 724 is disposed on the package body 706, wherein it selectively covers only the top surface 706a of the package body 706, one of the side surfaces 706b, 706c of the package body 706, the exposed surface of the third semiconductor component 718, except for the exposed surface of the second semiconductor component 704, the conductive layer 724 may be, for example, a shielding layer or a conformal shielding layer, and may be formed by photolithography in combination with etching and plating or physical vapor deposition.

Referring to fig. 12F, a connector 728 is disposed on the package 706. The connector 728 is disposed adjacent to the second semiconductor assembly 704. In the embodiment shown in fig. 7, the connector 728 is disposed over the feeding element 704b and the shielding elements 704a, 704 c. The connector 728 may be, for example, a connector for connecting to an antenna layer. The connector 728 may be formed by photolithography in combination with etching and plating or physical vapor deposition.

As used herein and unless otherwise limited, the term "about" is used to describe and explain minor variations. When used with an event or circumstance, the term can encompass an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs approximately. For example, when used in conjunction with a numerical value, the term can encompass variations that are less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be construed in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations are not necessarily drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the technical reproduction in the present disclosure and the actual equipment. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation.