阅读说明：本技术 半导体装置封装 (Semiconductor device package ) 是由 皮敦庆 黄晏琪 谢濠至 史晋翰 于 2019-08-15 设计创作，主要内容包括：一种半导体装置封装包含载体和安置在所述载体上的囊封物。所述囊封物的至少一个部分通过空间与所述载体间隔开。(A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least a portion of the encapsulation is spaced apart from the carrier by a space.)

1. A semiconductor device package, comprising:

a carrier; and

an encapsulate disposed on the carrier,

wherein at least a portion of the encapsulation is spaced apart from the carrier by a space.

2. The semiconductor device package of claim 1, wherein

The carrier has a first surface and the encapsulant is disposed on the first surface of the carrier,

the encapsulant has a first surface, a second surface opposite the first surface of the encapsulant, and a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and

the second surface of the encapsulant is attached to the first surface of the carrier and the third surface of the encapsulant is spaced apart from the first surface of the carrier.

3. The semiconductor device package of claim 1, wherein

The carrier has a first surface and a second surface recessed relative to the first surface, and the encapsulation is disposed on the first surface of the carrier, an

The encapsulant has a first surface and a second surface opposite the first surface of the encapsulant, and a first portion of the second surface of the encapsulant is spaced apart from the second surface of the carrier and a second portion of the second surface of the encapsulant is attached to the first surface of the carrier.

4. The semiconductor device package of claim 3, further comprising an electrically conductive layer disposed on the second surface of the carrier.

5. The semiconductor device package of claim 1, wherein

The carrier having a first surface and a second surface recessed relative to the first surface, and the encapsulant being disposed on the first surface of the carrier,

the encapsulant has a first surface, a second surface opposite the first surface of the encapsulant, and a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and

the second surface of the encapsulant is attached to the first surface of the carrier and the third surface of the encapsulant is spaced apart from the second surface of the carrier.

6. The semiconductor device package of claim 5, wherein the encapsulant further has a fourth surface adjacent to the third surface of the encapsulant and spaced apart from the second surface of the carrier.

7. The semiconductor device package of claim 1, wherein

The carrier having a first surface, a second surface recessed relative to the first surface, and a third surface connecting the first surface and the second surface, and the encapsulant being disposed on the first surface of the carrier,

the encapsulant having a first surface, a second surface opposite the first surface of the encapsulant, a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and a fourth surface,

the second surface of the encapsulant is attached to the first surface of the carrier and the third surface of the encapsulant is spaced apart from the first surface of the carrier and the second surface of the carrier,

the fourth surface of the encapsulant is connected to the second surface of the encapsulant and the third surface of the encapsulant, and the fourth surface of the encapsulant is disposed on the first surface of the carrier and is not coplanar with the third surface of the carrier,

and the third surface of the carrier is disposed below the third surface of the encapsulant.

8. The semiconductor device package of claim 7, wherein the encapsulant further has:

a fifth surface adjacent to the third surface of the encapsulant and spaced apart from the second surface of the carrier, an

A sixth surface connecting the first surface of the encapsulant and the fifth surface of the encapsulant.

9. The semiconductor device package of claim 1, wherein

The carrier having a first surface and a second surface projecting relative to the first surface, and the encapsulation being disposed on the first surface of the carrier,

the encapsulant has a first surface, a second surface opposite the first surface of the encapsulant, and a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and

a first portion of the third surface of the encapsulant is spaced apart from the first surface of the carrier and a second portion of the third surface of the encapsulant is attached to the second surface of the carrier.

10. The semiconductor device package of claim 1, wherein

The carrier having a first surface and a second surface projecting relative to the first surface, and the encapsulation being disposed on the first surface of the carrier,

the encapsulant has a first surface, a second surface opposite the first surface of the encapsulant, a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and a fourth surface adjacent to the third surface of the encapsulant and at a height lower than the height of the third surface of the encapsulant, and

the third surface of the encapsulant is attached to the second surface of the carrier and the fourth surface of the encapsulant is spaced apart from the first surface of the carrier.

11. The semiconductor device package of claim 1, wherein

The carrier having a first surface and a second surface projecting relative to the first surface, and the encapsulation being disposed on the first surface of the carrier,

the encapsulant has a first surface, a second surface opposite the first surface of the encapsulant, and a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and

the third surface of the encapsulant is spaced apart from the first surface of the carrier and the second surface of the carrier.

12. The semiconductor device package of claim 11, wherein the encapsulant further has a fourth surface adjacent to the third surface of the encapsulant and spaced apart from the first surface of the carrier and the second surface of the carrier, and at a height lower than the height of the third surface of the encapsulant.

13. The semiconductor device package of claim 1, wherein

The carrier has a first surface and comprises an electrically conductive layer, and the encapsulation is disposed on the first surface of the carrier with a portion of a surface of the electrically conductive layer exposed and recessed relative to the first surface of the carrier, an

The encapsulant has a first surface and a second surface opposite the first surface of the encapsulant, and a first portion of the second surface of the encapsulant is spaced apart from the portion of the surface of the conductive layer and a second portion of the second surface of the encapsulant is attached to the first surface of the carrier.

14. A semiconductor device package, comprising:

a carrier having a first surface and a second surface adjacent to the first surface; and

an encapsulant disposed on the first surface of the carrier;

wherein the roughness of the second surface of the carrier is greater than the roughness of the first surface of the carrier.

15. The semiconductor device package of claim 14, wherein the carrier further has a third surface adjacent to and angled relative to the second surface of the carrier, and the roughness of the second surface of the carrier is greater than the roughness of the third surface of the carrier.

16. The semiconductor device package of claim 14, wherein the carrier further has a fourth surface adjacent to and angled relative to the first surface of the carrier, and the roughness of the second surface of the carrier is greater than the roughness of the fourth surface of the carrier.

17. A method of fabricating a semiconductor device package, comprising:

providing a carrier having a surface;

forming a sacrificial layer on the surface of the carrier;

encapsulating the carrier and the sacrificial layer by an encapsulant;

removing a portion of the encapsulant to expose a portion of the sacrificial layer such that the encapsulant is divided into a first portion and a second portion, wherein the first portion of the encapsulant is attached to the carrier and the second portion of the encapsulant is attached to the sacrificial layer; and

removing the sacrificial layer and the second portion of the encapsulation.

18. The method of claim 17, wherein the surface of the carrier defines a chamber.

19. The method of claim 18, wherein a conductive layer is disposed within the chamber.

20. The method of claim 17, wherein the surface of the carrier comprises protruding portions.

Technical Field

The present invention relates to, among other things, semiconductor device packages and semiconductor device packages having regions or spaces that are free of encapsulation material.

Background

The molding process is a packaging technique for semiconductor packages, which is used to protect a substrate and components on the substrate. However, in some implementations, not the entire area of the substrate should be covered by the encapsulation material (also referred to as molding compound), for example, in an antenna-on-package (AoP) implementation, where impedance matching of the path from the component to the antenna may need to be performed. Accordingly, the semiconductor device package may have a non-molding region or space (a region or space without an encapsulation material), and a user may easily adjust impedance matching by adjusting Surface Mount Technology (SMT) passive components after a molding process.

Disclosure of Invention

According to one example embodiment of the present invention, a semiconductor device package includes a carrier and an encapsulant disposed on the carrier. In addition, at least one portion of the encapsulation is spaced apart from the carrier by a space.

According to another example embodiment of the present invention, a semiconductor device package includes: a carrier comprising a first surface and a second surface adjacent to the first surface; and an encapsulant disposed on the first surface of the carrier. In addition, the roughness of the second surface of the carrier is greater than the roughness of the first surface of the carrier.

According to another example embodiment of the present invention, a method of manufacturing a semiconductor device package includes: a) providing a carrier having a surface; b) forming a sacrificial layer on a surface of a carrier; c) encapsulating the carrier and the sacrificial layer with an encapsulant; d) removing a portion of the encapsulant to expose a portion of the sacrificial layer such that the encapsulant is divided into a first portion and a second portion, wherein the first portion of the encapsulant is attached to the carrier and the second portion of the encapsulant is attached to the sacrificial layer; and e) removing the sacrificial layer and the second portion of the encapsulation.

In order to further understand the present invention, the following examples and illustrations are provided to facilitate an understanding of the present invention; however, the drawings are provided for reference and illustration purposes only and do not limit the scope of the present invention.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device package according to an embodiment of the present invention.

Fig. 2A, 2B, 2C, and 2D illustrate a method of manufacturing a semiconductor device package according to an embodiment of the present invention.

Fig. 3A, 3B, 3C, 3D, and 3E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 4A, 4B, 4C, 4D, and 4E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 5A, 5B, 5C, 5D, and 5E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 6A, 6B, 6C, 6D, and 6E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 7A, 7B, 7C, 7D, and 7E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 8A, 8B, 8C, 8D, and 8E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 9A, 9B, 9C, 9D, and 9E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 10A, 10B, 10C, 10D, and 10E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 11A, 11B, 11C, 11D, and 11E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 12A, 12B, 12C, 12D, 12E, and 12F illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 13A, 13B, 13C, 13D, 13E, and 13F illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Fig. 14A, 14B, 14C, 14D, and 14E illustrate a method of manufacturing a semiconductor device package according to another embodiment of the present invention.

Detailed Description

The foregoing description and the following detailed description are examples for the purpose of illustrating the invention.

Fig. 1 shows a semiconductor device package 1 according to an embodiment of the present invention. Specifically, the semiconductor device package 1 has two asymmetric non-molding regions 13 and 15. As used herein, the term "non-molding region" may refer to a region (e.g., a region of a substrate) or space that is substantially free of molding material. Referring to fig. 1, a semiconductor device package 1 includes a carrier 10. The carrier 10 has an upper surface 11 and a lower surface 12 opposite the upper surface 11. The encapsulating material 20 is arranged on the upper surface 11 of the carrier 10. Die 101 and components 102, 103 (e.g., electronic components, e.g., passive electronic components) are disposed on upper surface 11 of carrier 10 and covered by encapsulation material 20. As shown in fig. 1, one or more regions of the upper surface 11 of the carrier 10 are exposed from the encapsulating material 20 (e.g., substantially free of the encapsulating material 20). The upper surface 11 of the carrier 10 has a non-molding area 13. In the non-molding region 13, there is substantially no encapsulation material 20 disposed on the upper surface 11 of the carrier 10, and the die 104 and the component 105 disposed on the upper surface 11 of the carrier 10 are not covered by the encapsulation material 20 and are therefore exposed. In addition, an encapsulating material 21 is disposed on the lower surface 12 of the carrier 10. The die 106 and the electrical contacts 107 are disposed on the lower surface 12 of the carrier 10 and are covered by the encapsulation material 21. In addition, a substrate 19 is disposed on the encapsulation material 21. In addition, one or more regions of the lower surface 12 of the carrier 10 are exposed from the encapsulating material 21 (e.g., substantially free of the encapsulating material 21). The lower surface 12 of the carrier 10 has a non-molding region 15. In the non-molding region 15, there is substantially no encapsulating material 21 disposed on the lower surface 12 of the carrier 10, and the components 108 and 109 disposed on the lower surface 12 of the carrier 10 are not covered by the encapsulating material 21 and are therefore exposed.

Further, referring to fig. 1, the non-molding regions 13 and 15 are different from each other and their positions do not correspond to each other (e.g., are not disposed relative to each other). The non-molding region 13 on the upper surface 11 of the carrier 10 and the non-molding region 15 on the lower surface 12 of the carrier 10 are not symmetrical to each other.

Fig. 2A, 2B, 2C, and 2D illustrate a method of manufacturing the semiconductor device package 110 according to an embodiment of the present invention. As shown in fig. 2A, at least one electronic component 112 is disposed on an upper surface 1111 of carrier 111. Additionally, in some embodiments, glue is dispensed on the upper surface 1111 of the carrier 111 to form a removable/sacrificial layer 1117 on the upper surface 1111 of the carrier 111. In some embodiments, the removable/sacrificial layer 1117 may comprise tape adhered or affixed to the upper surface 1111 of the carrier 111 or another removable binding material coated or printed on the upper surface 1111 of the carrier 111.

Referring to fig. 2B, an encapsulation material 113 is disposed on the carrier 111 and encapsulates the at least one electronic component 112 and the removable/sacrificial layer 1117. An encapsulation material 113 covers the at least one electronic component 112, the upper surface 111 of the carrier 11 and the removable/sacrificial layer 1117.

Referring to fig. 2C, a portion of the encapsulation material 113 is removed by a laser process and thus a portion of the removable/sacrificial layer 1117 is exposed. As such, the encapsulation material 113 is divided into two portions 1130 and 1139, with the portion of the encapsulation material 1130 attached to the upper surface 1111 of the carrier 111 and the removable/sacrificial layer 1117, and the portion of the encapsulation material 1139 attached to the removable/sacrificial layer 1117.

Referring to fig. 2D, the removable/sacrificial layer 1117 is removed by a physical method or a chemical method, for example, a water cleaning process. In addition, the portion of the encapsulation material 1139 attached to the removable/sacrificial layer 1117 is also removed (e.g., removed when the removable/sacrificial layer 1117 is removed). After removing portions of the removable/sacrificial layer 1117 and the encapsulation material 1139, portions of the encapsulation material 1130 remain on the carrier 111 and a portion of the upper surface 1111 of the carrier 111 is exposed. Portions of the encapsulation material 1130 are disposed on the upper surface 1111 of the carrier. Portions of the encapsulation material 1130 have an upper surface 1131 and a lower surface 1132 opposite the upper surface 1131 and attached to the upper surface 1111 of the carrier 111. Additionally, portions of the encapsulation material 1130 further have a surface 1133 at a height between the height of the upper surface 1131 and the lower surface 1132, wherein the surface 1133 is spaced apart from the upper surface 1111 of the carrier 111. There is a space between surface 1133 and upper surface 1111. Surface 1133 may be substantially parallel to either or each of upper surface 1131 and lower surface 1132.

In addition, portions of the encapsulation material 1130 have side surfaces 1136. Side surfaces 1136 may connect surface 1133 and upper surface 1131. The angle a between the side surface 1136 and the upper surface 1131 ranges from about 90 degrees to about 110 degrees.

Fig. 3A, 3B, 3C, 3D, and 3E illustrate a method of manufacturing a semiconductor device package 120 according to another embodiment of the present invention. As shown in fig. 3A, the carrier 121 has an upper surface 1211 and a recess 1210 formed in the upper surface 1211. The carrier 121 has a recessed surface 1212 (e.g., which defines the bottom of the recess 1210) that is recessed relative to the upper surface 1211. At least one electronic component 122 is disposed on the upper surface 1211 of the carrier 121.

In addition, referring to fig. 3B, glue is dispensed on the upper surface 1211 of the carrier 121, with a portion of the glue flowing into the recess 1210. Thus, a removable/sacrificial layer 1217 is formed on the upper surface 1211 and the recessed surface 1212 of the carrier 121.

Referring to fig. 3C, an encapsulation material 123 is disposed on the carrier 121 and encapsulates the at least one electronic component 122 and the removable/sacrificial layer 1217. Encapsulation material 123 covers at least one electronic component 122, an upper surface 1211 of carrier 121, and removable/sacrificial layer 1217.

Referring to fig. 3D, a portion of the encapsulation material 123 is removed by a laser process and thus a portion of the removable/sacrificial layer 1217 is exposed. As such, the encapsulation material 123 is divided into two portions 1230 and 1239, with the portion of the encapsulation material 1230 attached to the upper surface 1211 of the carrier 121 and the removable/sacrificial layer 1217, and the portion of the encapsulation material 1239 attached to the removable/sacrificial layer 1217.

Referring to fig. 3E, the removable/sacrificial layer 1217 is removed by a physical method or a chemical method, for example, a water washing process. The portion of the encapsulation material 1239 attached to the removable/sacrificial layer 1217 is removed (e.g., when the removable/sacrificial layer 1217 is removed). After removing the removable/sacrificial layer 1217 and portions of the encapsulation material 1239, portions of the encapsulation material 1230 remain on the carrier 121 and a portion of the upper surface 1211 of the carrier 121 and the recessed surface 1212 are exposed. A portion of the encapsulating material 1230 is disposed on the upper surface 1211 of the carrier 121. The portion of the encapsulating material 1230 has an upper surface 1231 and a lower surface 1232 opposite the upper surface 1231. In addition, a portion of lower surface 1232 is spaced apart from recessed surface 1212 of carrier 121 (e.g., spaced apart from recessed surface 1212 of carrier 121 and disposed on recessed surface 1212 of carrier 121) and a portion of lower surface 1232 is attached to upper surface 1211 of carrier 121. There is a space between the lower surface 1232 and the recessed surface 1212.

In addition, portions of the encapsulating material 1230 have side surfaces 1236. The angle B between side surface 1236 and upper surface 1231 ranges from about 90 degrees to about 110 degrees.

Fig. 4A, 4B, 4C, 4D, and 4E illustrate a method of manufacturing a semiconductor device package 130 according to another embodiment of the present invention. As shown in fig. 4A, the carrier 131 has an upper surface 1311 and a recess 1310 formed in the upper surface 1311. The carrier 131 further has a recessed surface 1312 (e.g., which defines the bottom of the recess 1310) that is recessed relative to the upper surface 1311. At least one electronic component 132 is disposed on an upper surface 1311 of carrier 131.

Additionally, referring to fig. 4B, glue is dispensed on the upper surface 1311 of the carrier 131, with a portion of the glue flowing into the recess 1310. Thus, a removable/sacrificial layer 1317 is formed on the upper surface 1311 and the recess surface 1312 of the carrier 131. The removable/sacrificial layer 1317 has an upper surface 1318 that is higher than the upper surface 1311 of the carrier 131. Furthermore, removable/sacrificial layer 1317 has side surfaces 1319 that are substantially coplanar with side surfaces 1315 of recess 1310.

Referring to fig. 4C, an encapsulation material 133 is disposed on the carrier 131 and encapsulates the at least one electronic component 132 and the removable/sacrificial layer 1317. An encapsulation material 133 covers at least one electronic component 132, an upper surface 1311 of carrier 131, and a removable/sacrificial layer 1317.

Referring to fig. 4D, a portion of the encapsulation material 133 is removed by a laser process and thus a portion of the removable/sacrificial layer 1317 is exposed. As such, the encapsulation material 133 is divided into two portions 1330 and 1339, with portions of the encapsulation material 1330 attached to the upper surface 1311 of the carrier 131 and the removable/sacrificial layer 1317, and portions of the encapsulation material 1339 attached to the removable/sacrificial layer 1317.

Referring to fig. 4E, the removable/sacrificial layer 1317 is removed by a physical method or a chemical method, for example, a water washing process. In addition, portions of the encapsulation material 1339 attached to the removable/sacrificial layer 1317 are removed (e.g., when the removable/sacrificial layer 1317 is removed). After removing portions of removable/sacrificial layer 1317 and encapsulation material 1339, portions of encapsulation material 1330 remain on carrier 131 and a portion of upper surface 1311 of carrier 131 and recessed surface 1312 are exposed. Portions of encapsulation material 1330 are disposed on an upper surface 1311 of carrier 131. Portions of the encapsulation material 1330 have an upper surface 1331 and a lower surface 1332 opposite the upper surface 1331. Additionally, portions of encapsulation material 1330 further have a surface 1333 at a height between the heights of upper surface 1331 and lower surface 1332, where surface 1333 is spaced apart from recessed surface 1312 of carrier 131 and rests on recessed surface 1312 of carrier 131. There is a space between surface 1333 and recessed surface 1312. In addition, portions of the encapsulation material 1330 have side surfaces 1335 that connect to the lower surface 1332 and the surface 1333. Side surface 1335 is substantially coplanar with side surface 1313 of recess 1310.

In addition, portions of the encapsulation material 1330 have side surfaces 1336. The angle C between the side surface 1336 and the upper surface 1331 ranges from about 90 degrees to about 110 degrees.

Fig. 5A, 5B, 5C, 5D, and 5E illustrate a method of manufacturing a semiconductor device package 140 according to another embodiment of the present invention. As shown in fig. 5A, carrier 141 has an upper surface 1411 and a recess 1410 formed in upper surface 1411. Carrier 141 further has a recessed surface 1412 (e.g., which defines the bottom of recess 1410) that is recessed relative to upper surface 1411. At least one electronic component 142 is disposed on an upper surface 1411 of carrier 141.

Additionally, referring to fig. 5B, glue is dispensed on upper surface 1411 of carrier 141, with a portion of the glue flowing into recess 1410. Accordingly, removable/sacrificial layer 1417 is formed on upper surface 1411 and recessed surface 1412 of carrier 141. Removable/sacrificial layer 1417 has an upper surface 1418 that is higher than upper surface 1411 of carrier 141. Furthermore, because the glue overflows recess 1410, removable/sacrificial layer 1417 extends across recess 1410 and has side surfaces 1419 on upper surface 1411 of carrier 141.

Referring to fig. 5C, an encapsulation material 143 is disposed on carrier 141 and encapsulates at least one electronic component 142 and removable/sacrificial layer 1417. Encapsulation material 143 covers at least one electronic component 142, an upper surface 1411 of carrier 141, and a removable/sacrificial layer 1417.

Referring to fig. 5D, a portion of the encapsulation material 143 is removed by a laser process and thus a portion of the removable/sacrificial layer 1417 is exposed. As such, encapsulation material 143 is divided into two portions 1430 and 1439, with portions of encapsulation material 1430 attached to upper surface 1411 of carrier 141 and removable/sacrificial layer 1417, and portions of encapsulation material 1439 attached to removable/sacrificial layer 1417.

Referring to fig. 5E, the removable/sacrificial layer 1417 is removed by a physical method or a chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 1439 attached to the removable/sacrificial layer 1417 is removed (e.g., when the removable/sacrificial layer 1417 is removed). After removing removable/sacrificial layer 1417 and portions of encapsulation material 1439, portions of encapsulation material 1430 remain on carrier 141 and a portion of upper surface 1411 of carrier 141 and recessed surfaces 1412 are exposed. Portions of encapsulation material 1430 are disposed on upper surface 1411 of carrier 141. Portions of the encapsulation material 1430 have an upper surface 1431 and a lower surface 1432 opposite the upper surface 1431. In addition, portions of encapsulation material 1430 further have a surface 1433 at an elevation between the elevations of upper surface 1431 and lower surface 1432, wherein surface 1433 is spaced apart from upper surface 1411 and recessed surface 1412 of carrier 141. A space exists between surface 1433 and upper surface 1411, recessed surface 1412. In addition, portions of encapsulation material 1430 further have side surfaces 1434 that are connected to lower surface 1432 and surface 1433. Side surface 1434 is disposed on upper surface 1411 of carrier 141 and is not coplanar with side surface 1415 of recess 1410. The side surface of the recess 1410 may be disposed below the surface 1433.

Further, portions of the encapsulation material 1430 have side surfaces 1436. The angle D between the side surface 1436 and the top surface 1431 ranges from about 90 degrees to about 110 degrees.

Fig. 6A, 6B, 6C, 6D, and 6E illustrate a method of manufacturing a semiconductor device package 150 according to another embodiment of the present invention. As shown in fig. 6A, the carrier 151 has an upper surface 1511 and a recess 1510 formed in the upper surface 1511. The carrier 151 further has a recessed surface 1512 (e.g., which defines the bottom of the recess 1510) that is recessed relative to the upper surface 1511. At least one electronic component 152 is disposed on the upper surface 1511 of the carrier 151.

Additionally, referring to fig. 6B, glue is dispensed on the upper surface 1511 of the carrier 151, with a portion of the glue flowing into the recess 1510. Thus, a removable/sacrificial layer 1517 is formed on the upper surface 1511 and the recessed surface 1512 of the carrier 151. The removable/sacrificial layer 1517 has an upper surface 1518 higher than the upper surface 1511 of the carrier 151. Furthermore, because the glue overflows the recess 1510, the removable/sacrificial layer 157 has an overhanging portion 1515 that overhangs the upper surface 1518 of the removable/sacrificial layer 1517. The protrusion 1515 has a side surface 1516 substantially coplanar with a side surface 1519 of the recess 1510.

Referring to fig. 6C, an encapsulation material 153 is disposed on the carrier 151 and encapsulates the at least one electronic component 152 and the removable/sacrificial layer 1517. Encapsulation material 153 covers at least one electronic component 152, an upper surface 1511 of carrier 151, and removable/sacrificial layer 1517.

Referring to fig. 6D, a portion of the encapsulation material 153 is removed by a laser process and thus a portion of the removable/sacrificial layer 1517 is exposed. As such, encapsulation material 153 is divided into two portions 1530 and 1539, with portions of encapsulation material 1530 attached to upper surface 1511 of carrier 151 and removable/sacrificial layer 1517, and portions of encapsulation material 1539 attached to removable/sacrificial layer 1517.

Referring to fig. 6E, the removable/sacrificial layer 1517 is removed by a physical method or a chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 1539 attached to the removable/sacrificial layer 1517 is removed (e.g., when the removable/sacrificial layer 1517 is removed). After removing portions of removable/sacrificial layer 1517 and encapsulation material 1539, portions of encapsulation material 1530 remain on carrier 151 and a portion of upper surface 1511 of carrier 151 and recessed surfaces 1512 are exposed. Portions of encapsulation material 1530 are disposed on upper surface 1511 of carrier 151. Portions of the encapsulation material 1530 have an upper surface 1531 and a lower surface 1532 opposite the upper surface 1131. Portions of encapsulation material 1530 further have a surface 1533 at a height between the height of upper surface 1531 and lower surface 1532, where surface 1533 is spaced from upper surface 1511 and recessed surface 1512 of carrier 151. The surface 1533 is disposed on the recessed surface 1512 of the carrier 151. In addition, portions of the encapsulation material 1530 further have a surface 1534 adjacent to the surface 1533 and below the surface 1533. The surface 1534 is spaced apart from (and, e.g., disposed on) the recessed surface 1512 of the carrier 151. Surface 1534 may be substantially parallel to surface 1533. There is a space between the surfaces 1533, 1534 and the recessed surface 1512. In addition, portions of the encapsulation material 1530 further have side surfaces 1535 that connect to the lower surface 1532 and the surface 1533. Side surface 1535 is substantially coplanar with side surface 1519 of recess 1510.

In addition, portions of the encapsulation material 1530 have side surfaces 1536. The angle E between the side surface 1536 and the upper surface 1531 ranges from about 90 degrees to about 110 degrees.

Fig. 7A, 7B, 7C, 7D, and 7E illustrate a method of manufacturing a semiconductor device package 160 according to another embodiment of the present invention. As shown in fig. 7A, the carrier 161 has an upper surface 1611 and a recess 1610 formed in the upper surface 1611. Carrier 161 further has a recessed surface 1612 (e.g., which defines the bottom of recess 1610) that is recessed relative to upper surface 1611. At least one electronic component 162 is disposed on an upper surface 1611 of carrier 161.

Additionally, referring to fig. 7B, glue is dispensed on the upper surface 1611 of the carrier 161, with a portion of the glue flowing into the recesses 1610. Accordingly, a removable/sacrificial layer 1617 is formed on upper surface 1611 and recessed surface 1612 of carrier 161. The removable/sacrificial layer 1617 has an upper surface 1618 that is higher than the upper surface 1611 of the carrier 161. Furthermore, because the glue overflows the recess 1610, the removable/sacrificial layer 1617 has an overhang 1615 that overhangs from the upper surface 1618 of the removable/sacrificial layer 1617 and extends to the upper surface 1611 of the carrier 161. The overhang 1615 has a side surface 1616 that rests on the upper surface 1611 of the carrier 161.

Referring to fig. 7C, an encapsulation material 163 is disposed on the carrier 161 and encapsulates the at least one electronic component 162 and the removable/sacrificial layer 1617. Encapsulation material 163 covers at least one electronic component 162, an upper surface 1611 of carrier 161, and removable/sacrificial layer 1617.

Referring to fig. 7D, a portion of the encapsulation material 163 is removed by a laser process and thus a portion of the removable/sacrificial layer 1617 is exposed. As such, the encapsulation material 163 is divided into two portions 1630 and 1639, with the portion of the encapsulation material 1630 attached to the upper surface 1611 of the carrier 161 and the removable/sacrificial layer 1617, and the portion of the encapsulation material 1639 attached to the removable/sacrificial layer 1617.

Referring to fig. 7E, the removable/sacrificial layer 1617 is removed by a physical method or a chemical method, for example, a water cleaning process. In addition, the portion of the encapsulation material 1639 attached to the removable/sacrificial layer 1617 is removed (e.g., when the removable/sacrificial layer 1617 is removed). After removing portions of the removable/sacrificial layer 1617 and the encapsulation material 1639, portions of the encapsulation material 1630 remain on the carrier 161 and a portion of the upper surface 1611 of the carrier 161 and the recessed surface 1612 are exposed. A portion of the encapsulation material 1630 is disposed on the upper surface 1611 of the carrier 161. Portions of the encapsulating material 1630 have an upper surface 1631 and a lower surface 1632 opposite the upper surface 1631. The portion of encapsulation material 1630 further has a surface 1633 at a height between the height of the upper surface 1631 and the lower surface 1632, wherein the surface 1633 is spaced apart from the upper surface 1611 and the recessed surface 1612 of the carrier 161. At least a portion of surface 1633 rests on recessed surface 1612 of carrier 161. In addition, portions of the encapsulation material 1630 further have a surface 1634 adjacent to surface 1633 and lower than surface 1633. Surface 1634 is spaced apart from recessed surface 1612 of carrier 161. Surface 1634 may be substantially parallel to surface 1633. There is a space between surfaces 1633, 1634 and upper surface 1611 and recessed surface 1612. In addition, portions of the encapsulation material 1630 further have side surfaces 1635 that are connected to the lower surface 1632 and the surface 1633. The side surface 1635 is disposed on the upper surface 1611 of the carrier 161 and is not coplanar with the side surface 1615 of the recess 1610.

In addition, portions of the encapsulation material 1630 have side surfaces 1636. The angle F between side surface 1636 and upper surface 1631 ranges from about 90 degrees to about 110 degrees.

Fig. 8A, 8B, 8C, 8D, and 8E illustrate a method of manufacturing a semiconductor device package 170 according to another embodiment of the present invention. As shown in fig. 8A, carrier 171 has an upper surface 1711 and extensions 1710 formed on upper surface 1711. The carrier 171 further has a protruding surface 1712 that protrudes relative to the upper surface 1711. At least one electronic component 172 is disposed on an upper surface 1711 of carrier 171.

Additionally, referring to fig. 8B, glue is dispensed on the upper surface 1711 of the carrier 171, wherein the glue does not flow through the extensions 1710. Thus, a removable/sacrificial layer 1717 is formed on the upper surface 1711. Further, the removable/sacrificial layer 1717 has an upper surface 1718 that is substantially coplanar with the protruding surface 1712.

Referring to fig. 8C, an encapsulation material 173 is disposed on the carrier 171 and encapsulates at least one electronic component 172 and the removable/sacrificial layer 1717. The encapsulation material 173 covers the at least one electronic component 172, the upper surface 1711 and the protruding surface 1712 of the carrier 171, and the removable/sacrificial layer 1717.

Referring to fig. 8D, a portion of the encapsulation material 173 is removed by a laser process and thus a portion of the removable/sacrificial layer 1717 is exposed. As such, the encapsulation material 173 is divided into two portions 1730 and 1739, with portions of the encapsulation material 1730 attached to the upper surface 1711 and the protruding surface 1712 of the carrier 171 and the removable/sacrificial layer 1717, and portions of the encapsulation material 1739 attached to the removable/sacrificial layer 1717.

Referring to fig. 8E, the removable/sacrificial layer 1717 is removed by a physical method or a chemical method, for example, a water cleaning process. In addition, the portion of the encapsulation material 1739 attached to the removable/sacrificial layer 1717 is removed (e.g., when the removable/sacrificial layer 1717 is removed). After removing portions of the removable/sacrificial layer 1717 and the encapsulation material 1739, portions of the encapsulation material 1730 remain on the carrier 171 and a portion of the upper surface 1711 of the carrier 171 is exposed. A portion of the encapsulation material 1730 is disposed on the upper surface 1711 of the carrier 171. Portions of the encapsulation material 1730 have an upper surface 1731 and a lower surface 1732 opposite the upper surface 1731. Additionally, a portion of the encapsulation material 1730 further has a surface 1733 at a height between the height of the upper surface 1731 and the lower surface 1732, wherein a portion of the surface 1733 is attached to the protruding surface 1712 of the carrier 171 and a portion of the surface 1733 is spaced apart from the upper surface 1711 of the carrier 171. A space exists between surface 1733 and upper surface 1711.

In addition, portions of the encapsulation material 1730 have side surfaces 1736. The angle G between the side surface 1736 and the upper surface 1731 ranges from about 90 degrees to about 110 degrees.

Fig. 9A, 9B, 9C, 9D, and 9E illustrate a method of manufacturing a semiconductor device package 180 according to another embodiment of the present invention. As shown in fig. 9A, the carrier 181 has an upper surface 1811 and a protruding portion 1810 formed on the upper surface 1811. The carrier 181 further has a protruding surface 1812 that protrudes relative to the upper surface 1811. At least one electronic component 182 is disposed on an upper surface 1811 of the carrier 181.

Additionally, referring to fig. 9B, glue is dispensed onto the upper surface 1811 of the carrier 181, wherein the glue does not flow over the extensions 1810. Thus, a removable/sacrificial layer 1817 is formed on the upper surface 1811. In addition, removable/sacrificial layer 1817 has an upper surface 1818 that is lower than protruding surface 1812.

Referring to fig. 9C, an encapsulation material 183 is disposed on the carrier 181 and encapsulates the at least one electronic component 182 and the removable/sacrificial layer 1817. The encapsulation material 183 covers the at least one electronic component 182, the upper surface 1811 and the protruding surface 1812 of the carrier 181, and the removable/sacrificial layer 1817.

Referring to fig. 9D, a portion of the encapsulation material 183 is removed by a laser process and thus a portion of the removable/sacrificial layer 1817 is exposed. As such, the encapsulating material 183 is divided into two portions 1830 and 1839, with the portions of the encapsulating material 1830 attached to the upper surface 1811 and the protruding surface 1812 of the carrier 181 and the removable/sacrificial layer 1817, and the portions of the encapsulating material 1839 attached to the removable/sacrificial layer 1817.

Referring to fig. 9E, the removable/sacrificial layer 1817 is removed by a physical method or a chemical method, for example, a water washing process. In addition, portions of the encapsulation material 1839 attached to the removable/sacrificial layer 1817 are removed (e.g., when the removable/sacrificial layer 1817 is removed). After removing portions of the removable/sacrificial layer 1817 and the encapsulation material 1839, portions of the encapsulation material 1830 remain on the carrier 181 and a portion of the upper surface 1811 of the carrier 181 is exposed. Portions of the encapsulating material 1830 are disposed on the upper surface 1811 of the carrier 181. The portion of the encapsulating material 1830 has an upper surface 1831 and a lower surface 1832 opposite the upper surface 1831. In addition, a portion of the encapsulating material 1830 further has a surface 1833 at a height between the height of the upper surface 1831 and the lower surface 1832, wherein the surface 1833 is attached to the protruding surface 1812 of the carrier 181. In addition, portions of the encapsulation material 1830 further have a surface 1834 adjacent to the surface 1833 and below the surface 1833. Surface 1834 may be substantially parallel to surface 1833. Surface 1834 is spaced apart from upper surface 1811 of carrier 181. There is a space between surface 1834 and upper surface 1811.

Further, portions of the encapsulation material 1830 have side surfaces 1836. The angle H between side surface 1836 and upper surface 1831 is in a range from about 90 degrees to about 110 degrees.

Fig. 10A, 10B, 10C, 10D, and 10E illustrate a method of manufacturing a semiconductor device package 190 according to another embodiment of the present invention. As shown in fig. 10A, the carrier 191 has an upper surface 1911 and a protruding portion 1910 formed on the upper surface 1911. The carrier 191 further has an extended surface 1912 that extends relative to the upper surface 1911. At least one electronic component 192 is disposed on an upper surface 1911 of carrier 191.

Additionally, referring to FIG. 10B, glue is dispensed onto the upper surface 1911 of the carrier 191 where the glue extends over the extended surface 1912 but does not flow over the extended portion 1910. Thus, a removable/sacrificial layer 1917 is formed on the upper surface 1911 and the extended surface 1912. In addition, the removable/sacrificial layer 1917 has a substantially planar upper surface 1918.

Referring to fig. 10C, an encapsulation material 193 is disposed on carrier 191 and encapsulates at least one electronic component 192 and removable/sacrificial layer 1917. The encapsulation material 193 covers the at least one electronic component 192, the upper surface 1911 of the carrier 191 and the removable/sacrificial layer 1917.

Referring to fig. 10D, a portion of the encapsulation material 193 is removed by a laser process and thus a portion of the removable/sacrificial layer 1917 is exposed. As such, the encapsulation material 193 is divided into two portions 1930 and 1939, with the portions of the encapsulation material 1930 attached to the upper surface 1911 of the carrier 191 and the removable/sacrificial layer 1917, and the portions of the encapsulation material 1939 attached to the removable/sacrificial layer 1917.

Referring to fig. 10E, the removable/sacrificial layer 1917 is removed by a physical or chemical method, for example, a water cleaning process. In addition, the portion of the encapsulation material 1939 attached to the removable/sacrificial layer 1917 is removed (e.g., when the removable/sacrificial layer 1917 is removed). After removing portions of the removable/sacrificial layer 1917 and the encapsulation material 1939, portions of the encapsulation material 1930 remain on the carrier 191 and a portion of the upper surface 1911 of the carrier 191 is exposed. A portion of encapsulation material 1930 is disposed on upper surface 1911 of carrier 191. A portion of the encapsulation material 1930 has an upper surface 1931 and a lower surface 1932 opposite the upper surface 1931. Additionally, portions of encapsulation material 1930 further have a surface 1933 at a height between the height of upper surface 1931 and lower surface 1932, wherein surface 1933 is spaced apart from upper surface 1911 and extended surfaces 1912 of carrier 191. There is a space between surface 1933 and upper surface 1911 and extended surface 1912. The surface 1933 may be disposed above the protruding surface 1912.

Further, portions of the encapsulation material 1930 have side surfaces 1936. The angle I between the side surface 1936 and the upper surface 1931 ranges from about 90 degrees to about 110 degrees.

Fig. 11A, 11B, 11C, 11D, and 11E illustrate a method of manufacturing a semiconductor device package 200 according to another embodiment of the present invention. As shown in fig. 11A, the carrier 201 has an upper surface 2011 and protruding portions 2010 formed on the upper surface 2011. The carrier 201 further has a protruding surface 2012 protruding with respect to the upper surface 2011. At least one electronic component 202 is disposed on an upper surface 2011 of the carrier 201.

Additionally, referring to fig. 11B, glue is dispensed on the upper surface 2011 of the carrier 201, where the glue extends over the protrusion surface 2012 but does not flow through the protrusion 2010. Thus, a removable/sacrificial layer 2017 is formed on the upper surface 2011 and the projection surface 2012. In addition, the removable/sacrificial layer 2017 has a non-uniform upper surface 2018.

Referring to fig. 11C, an encapsulation material 203 is disposed on the carrier 201 and encapsulates the at least one electronic component 202 and the removable/sacrificial layer 2017. Encapsulation material 203 covers at least one electronic component 202, an upper surface 2011 of carrier 201, and removable/sacrificial layers 2017.

Referring to fig. 11D, a portion of the encapsulation material 203 is removed by a laser process and thus a portion of the removable/sacrificial layer 2017 is exposed. As such, the encapsulation material 203 is divided into two portions 2030 and 2039, with portions of the encapsulation material 2030 attached to the upper surface 2011 of the carrier 201 and the removable/sacrificial layer 2017, and portions of the encapsulation material 2039 attached to the removable/sacrificial layer 2017.

Referring to fig. 11E, the removable/sacrificial layer 2017 is removed by a physical method or a chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 2039 attached to the removable/sacrificial layer 2017 is removed (e.g., when the removable/sacrificial layer 2017 is removed). After removing portions of the removable/sacrificial layer 2017 and the encapsulation material 2039, portions of the encapsulation material 2030 remain on the carrier 201 and a portion of the upper surface 2011 of the carrier 201 is exposed. Portions of the encapsulating material 2030 are disposed on the upper surface 2011 of the carrier 201. Portions of the encapsulating material 2030 have an upper surface 2031 and a lower surface 2032 opposite the upper surface 2031. In addition, portions of the encapsulating material 2030 further have a surface 2033 at a height between the height of the top surface 2031 and the bottom surface 2032. Surface 2033 is spaced apart from (and, for example, disposed on) the protruding surface 2012 of the carrier 201. In addition, portions of the encapsulating material 2030 further have a surface 2034 adjacent to surface 2033 and below surface 2033. Surface 2034 may be substantially parallel to surface 2033. Surface 2034 is spaced apart from the upper surface 2011 of the carrier 201. There is a space between surfaces 2033, 2034 and upper surface 2011 and the projection surface 2012.

Further, portions of the encapsulating material 2030 have side surfaces 2036. The angle J between the side surface 2036 and the upper surface 2031 is in the range of from about 90 degrees to about 110 degrees.

Fig. 12A, 12B, 12C, 12D, 12E, and 12F illustrate a method of manufacturing a semiconductor device package 210 according to another embodiment of the present invention. As shown in fig. 12A, the carrier 211 has an upper surface 2111 and a recess 2110 formed in the upper surface 2111. Carrier 211 further has a recessed surface 2112 that is recessed relative to upper surface 2110 (e.g., that defines the bottom of recess 2110). At least one electronic component 212 is disposed on an upper surface 2111 of the carrier 211. In addition, the conductive layer 215 is disposed on the recessed surface 2112.

Additionally, referring to FIG. 12B, glue is dispensed on the upper surface 2111 of the carrier 211, with a portion of the glue flowing into the recess 2110. Thus, a removable/sacrificial layer 2117 is formed on the upper surface 2111 and the recessed surface 2112 of the carrier 211 and the conductive layer 215.

Referring to fig. 12C, an encapsulation material 213 is disposed on the carrier 211 and encapsulates the at least one electronic component 212 and the removable/sacrificial layer 2117. The encapsulation material 213 covers the at least one electronic component 212, the upper surface 2111 of the carrier 211, and the removable/sacrificial layer 2117.

Referring to fig. 12D, a portion of the encapsulation material 213 is removed by a laser process and thus a portion of the removable/sacrificial layer 2117 is exposed. The cutting gap formed by the laser is substantially aligned with the position of the conductive layer 215. The encapsulation material 213 is divided into two portions 2130 and 2139, with the portion of the encapsulation material 2130 attached to the upper surface 2111 of the carrier 211 and the removable/sacrificial layer 2117, and the portion of the encapsulation material 2139 attached to the removable/sacrificial layer 2117.

Referring to fig. 12E, the removable/sacrificial layer 2117 is removed by a physical method or a chemical method, for example, a water cleaning process. In addition, the portion of the encapsulation material 2139 that is attached to the removable/sacrificial layer 2117 is removed (e.g., when the removable/sacrificial layer 2117 is removed). After removing portions of the removable/sacrificial layer 2117 and the encapsulation material 2139, portions of the encapsulation material 2130 remain on the carrier 211 and a portion of the upper surface 2111 of the carrier 211 and the recessed surface 2112 and the conductive layer 215 are exposed. Portions of the encapsulating material 2130 are disposed on the upper surface 2111 of the carrier 211. The portion of the encapsulating material 2130 has an upper surface 2131 and a lower surface 2132 opposite the upper surface 2131. In addition, a portion of the lower surface 2132 is spaced apart from (and e.g., disposed on) the recessed surface 2112 of the carrier 211, and a portion of the lower surface 2132 is attached to the upper surface 2111 of the carrier 211. There is a space between the lower surface 2132 and the recessed surface 2112.

Further, portions of the encapsulation material 2130 have side surfaces 2136. The angle K between the side surface 2136 and the upper surface 2131 ranges from about 90 degrees to about 110 degrees.

Referring to fig. 12F, a shield layer 217 is formed over portions of the conductive layer 215 and the encapsulation material 2130.

Fig. 13A, 13B, 13C, 13D, 13E, and 13F illustrate a method of manufacturing a semiconductor device package 220 according to another embodiment of the present invention. As shown in fig. 13A, the carrier 221 has an upper surface 2211 and a conductive layer 225. A portion of the top surface of conductive layer 255 is exposed and recessed relative to the upper surface 2211 of carrier 221.

Additionally, referring to fig. 13B, glue is dispensed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, a removable/sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 as well as the conductive layer 225.

Referring to fig. 13C, an encapsulation material 223 is disposed on the carrier 221 and encapsulates the at least one electronic component 222 and the removable/sacrificial layer 2217. The encapsulation material 223 covers the at least one electronic component 222, the upper surface 2211 of the carrier 221, and the removable/sacrificial layer 2217.

Referring to fig. 13D, a portion of the encapsulation material 223 is removed by a laser process and thus a portion of the removable/sacrificial layer 2217 is exposed. The cutting gap formed by the laser is substantially aligned with the position of the conductive layer 225. The encapsulation material 223 is divided into two portions 2230 and 2239, with portions of the encapsulation material 2230 attached to the upper surface 2211 of the carrier 221 and the removable/sacrificial layer 2217, and portions of the encapsulation material 2239 attached to the removable/sacrificial layer 2217.

Referring to fig. 13E, the removable/sacrificial layer 2217 is removed by physical or chemical methods, for example, a water cleaning process. In addition, the portion of the encapsulation material 2239 that is attached to the removable/sacrificial layer 2217 is removed (e.g., when the removable/sacrificial layer 2217 is removed). After removing portions of the removable/sacrificial layer 2217 and the encapsulation material 2239, portions of the encapsulation material 2230 remain on the carrier 221 and a portion of the upper surface 2211 of the carrier 221 and the conductive layer 225 are exposed. Portions of the encapsulation material 2230 rest on the upper surface 2211 of the carrier 221. Portions of the encapsulation material 2230 have an upper surface 2231 and a lower surface 2232 opposite the upper surface 2231. Additionally, a portion of lower surface 2232 is spaced apart from conductive layer 225, and a portion of lower surface 2232 is attached to upper surface 2211 of carrier 221. A space exists between the lower surface 2232 and the conductive layer 225.

Further, portions of the encapsulation material 2230 have side surfaces 2236. The angle L between the side surface 2236 and the upper surface 2231 is in the range from about 90 degrees to about 110 degrees.

Referring to fig. 13F, a shield layer 227 is formed over portions of the conductive layer 225 and the encapsulation material 2230.

Fig. 14A, 14B, 14C, 14D, and 14E illustrate a method of manufacturing a semiconductor device package 230 according to another embodiment of the present invention. As shown in fig. 14A, carrier 231 has an upper surface 2311 and includes a conductive layer 235. A portion of the top surface of conductive layer 235 is exposed and recessed relative to upper surface 2311 of carrier 231. In addition, because portions of the top surface of conductive layer 235 are exposed and recessed relative to upper surface 2311 of carrier 231, carrier 231 further has side surfaces 2313, 2314 disposed on conductive layer 225 and adjacent to and angled relative to upper surface 2311 of carrier 231 (e.g., at about 90 degrees).

Additionally, referring to fig. 14B, glue is dispensed on the upper surface 2311 of carrier 231 and conductive layer 235. Thus, a removable/sacrificial layer 2317 is formed over upper surface 2311 and carrier 231 and conductive layer 235.

Referring to fig. 14C, an encapsulation material 233 is disposed on the carrier 231 and encapsulates the at least one electronic component 232 and the removable/sacrificial layer 2317. The encapsulation material 233 covers the at least one electronic component 232, the upper surface 2311 of the carrier 231, and the removable/sacrificial layer 2317.

Referring to fig. 14D, a portion of the encapsulation material 233 is removed by a laser process and thus a portion of the removable/sacrificial layer 2317 and a portion of the upper surface 2311 of the carrier 231 are exposed. In addition, when the encapsulation material 233 is cut using a laser, the laser contacts portions of the removable/sacrificial layer 2317 and portions of the upper surface 2311 of the carrier 231 that are exposed after the portions of the encapsulation material 233 have been removed. The portion of the upper surface 2311 of the carrier 231 contacted by the laser may be roughened by the laser. The encapsulation material 233 is divided into two portions 2330 and 2339, with portions of the encapsulation material 2330 attached to the upper surface 2311 of the carrier 231 and portions of the encapsulation material 2339 attached to the removable/sacrificial layer 2317.

Referring to fig. 14E, the removable/sacrificial layer 2317 is removed by a physical method or a chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 2339 attached to the removable/sacrificial layer 2317 is removed (e.g., when the removable/sacrificial layer 2317 is removed). After removing portions of removable/sacrificial layer 2317 and encapsulation material 2339, portions of encapsulation material 2330 remain on carrier 231 and a portion of upper surface 2311 of carrier 231 and conductive layer 235 are exposed. As mentioned above, the laser directly contacts portions of the upper surface 2311 when cutting the encapsulation material 233. Thus, the surface 2312 of the carrier 231 as between the portion of the encapsulation material 2330 and the conductive layer 235 has a roughness that is greater than the roughness of another portion of the upper surface 2311 of the carrier 231 and greater than the roughness of the side surfaces 2313, 2314 of the carrier 231 (e.g., by a factor of about 1.3 or greater, by a factor of about 1.5 or greater, by a factor of about 2 or greater, or greater).

In addition, portions of the encapsulation material 2330 have side surfaces 2336. The angle M between the side surface 2336 and the upper surface 2331 ranges from about 90 degrees to about 110 degrees.

References in this disclosure to the formation or positioning of a first feature over or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%.

For example, substantially parallel may refer to a range of angular variation of less than or equal to ± 10 ° relative to 0 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, substantially perpendicular may refer to a range of angular variation of less than or equal to ± 10 ° relative to 90 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be considered substantially flat if the displacement between the highest and lowest points of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be considered limiting. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The description may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a difference between the artistic reproduction in the present invention and the actual equipment. There may be other embodiments of the invention not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention.