阅读说明：本技术 半导体装置封装 (Semiconductor device package ) 是由 谢濠至 皮敦庆 江松弘 陈昱敞 于 2019-09-09 设计创作，主要内容包括：一种半导体装置封装包括安装到载体的数个中介层,其中所述数个中介层可布置成不规则图案。(A semiconductor device package includes a number of interposers mounted to a carrier, where the number of interposers may be arranged in an irregular pattern.)

1. A semiconductor device package, comprising:

a carrier having a first surface and a second surface opposite the first surface;

a plurality of first interposers disposed in the first surface of the carrier;

a first encapsulant encapsulating the first surface of the carrier and the number of first interposers and separating one of the number of first interposers from another of the number of first interposers, and

a second encapsulant encapsulating the second surface of the carrier;

wherein the number of first interposers are arranged in an irregular pattern.

2. The semiconductor device package of claim 1, wherein one of the first interposers comprises a redistribution layer.

3. The semiconductor device package of claim 1, wherein one of the first interposers comprises conductive vias having an hourglass-shaped cross-section.

4. The semiconductor device package of claim 1, wherein one of the first interposers has a third surface and the first encapsulant has a fourth surface, and wherein at least a portion of the fourth surface is lower than the third surface.

5. The semiconductor device package of claim 1, further comprising at least one first component disposed on the second surface of the carrier and encapsulated by the second encapsulant.

6. The semiconductor device package of claim 1, further comprising a second interposer stacked on two or more first interposers, wherein the second interposer has a fifth surface facing the first surface of the carrier and encapsulated by the first encapsulant.

7. The semiconductor device package of claim 6, further comprising a component mounted on the fifth surface of the second interposer.

8. The semiconductor device package of claim 6, wherein the second interposer has a sixth surface opposite the fifth surface, and wherein components are mounted on the sixth surface of the second interposer.

9. The semiconductor device package of claim 6, the second interposer having a cross-sectional width that is less than a cross-sectional width of the carrier.

10. The semiconductor device package of claim 1, further comprising a plurality of first components disposed on the second surface of the carrier and encapsulated by the second encapsulant, wherein the first components are passive components.

11. The semiconductor device package of claim 5, further comprising a second component disposed on the second surface of the carrier and encapsulated by the second encapsulation, and further comprising a compartment shielding structure disposed between the first component and the second component.

12. The semiconductor device package of claim 1, further comprising at least one packaging unit disposed on the second surface of the carrier and encapsulated by the second encapsulation, wherein the packaging unit comprises a substrate, a first electronic device disposed on the substrate, and a third encapsulation encapsulating the first electronic device and the substrate.

13. The semiconductor device package of claim 12, wherein the packaging unit comprises a second electronic device embedded in the substrate.

14. The semiconductor device package of claim 12, wherein the packaging unit comprises a shield layer formed on the third encapsulant and electrically connected to the substrate.

15. The semiconductor device package of claim 1, wherein a portion of the second surface of the carrier is not encapsulated by the second encapsulant, and wherein a third component is disposed on the portion of the second surface of the carrier that is not encapsulated by the second encapsulant.

16. The semiconductor device package of claim 1, wherein a portion of the first surface of the carrier is not encapsulated by the first encapsulant, and wherein a fourth component is disposed on the portion of the first surface of the carrier that is not encapsulated by the first encapsulant.

17. A semiconductor device package, comprising:

a carrier having a first surface; and

a first interposer disposed on the first surface of the carrier;

wherein the first interposer includes conductive vias having an hourglass-shaped cross-section.

18. The semiconductor device package of claim 17, further comprising a component disposed on the first surface of the carrier and a first encapsulant encapsulating the component, the first surface of the carrier, and the first interposer.

19. The semiconductor device package of claim 18, wherein the carrier has a second surface opposite the first surface, and wherein a second encapsulant encapsulates the second surface of the carrier, and wherein a component is disposed on and encapsulated by the second surface of the carrier.

20. The semiconductor device package of claim 17, further comprising a number of the first interposers disposed on the first surface of the carrier and a second interposer stacked on two or more first interposers, wherein the second interposer has a fifth surface facing the first surface of the carrier and a sixth surface opposite the fifth surface, and wherein a first component is mounted on the fifth surface of the second interposer and a second component is mounted on the sixth surface of the second interposer.

Technical Field

The present disclosure relates to a semiconductor device package having at least one interposer.

Background

To increase packaging density, a two-sided assembly is used for semiconductor packaging technology. That is, the electronic component may be mounted to the side of the carrier facing the printed circuit board to which the carrier is connected or to the side of the carrier connected to an external component. In addition, the electronic components are encapsulated by the molding compound.

Disclosure of Invention

According to one exemplary embodiment of the present disclosure, a semiconductor device package includes a carrier, a number of first interposers, a first encapsulant, and a second encapsulant. The carrier has a first surface and a second surface opposite the first surface. The first interposer is disposed in the first surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and the first interposer. In addition, the first encapsulation separates one of the first interposers from another of the number of first interposers. The second encapsulant encapsulates the second surface of the carrier. The first interposers are arranged in an irregular pattern.

According to another exemplary embodiment of the present disclosure, a semiconductor device package includes a carrier and a first interposer. The carrier has a first surface, and the first interposer is disposed on the first surface of the carrier. Additionally, the first interposer includes conductive vias having an hourglass-shaped cross-section.

In order to further understand the present invention, the following examples and illustrations are provided to facilitate an understanding of the present invention; however, the drawings are provided for reference and illustration purposes only and are not intended to limit the scope of the present disclosure.

Drawings

Fig. 1A is a top view of a semiconductor device package according to an embodiment of the present invention.

Figure 1B shows a semiconductor device package according to an embodiment of the present disclosure under a molding process.

Fig. 2A is a top view of a semiconductor device package according to another embodiment of the present disclosure.

Figure 2B shows a semiconductor device package according to another embodiment of the present disclosure under a molding process.

Fig. 3A is a top view of a semiconductor device package according to another embodiment of the present invention.

Figure 3B shows a semiconductor device package according to another embodiment of the present disclosure under a molding process.

Fig. 4A is a top view of a semiconductor device package according to another embodiment of the present invention.

Figure 4B shows a semiconductor device package according to another embodiment of the present disclosure under a molding process.

Fig. 5A is a top view of a semiconductor device package according to another embodiment of the present invention.

FIG. 5B illustrates a cross-sectional view along line I-I in FIG. 5A.

Fig. 6 shows a semiconductor device package according to another embodiment of the present disclosure.

Fig. 7 shows a semiconductor device package according to another embodiment of the present disclosure.

Fig. 8 shows a semiconductor device package according to another embodiment of the present disclosure.

Fig. 9 shows a semiconductor device package according to another embodiment of the present disclosure.

Detailed Description

The foregoing description, as well as the following detailed description, are exemplary and are intended to further illustrate the scope of the invention. Other objects and advantages associated with the present invention will be set forth in the description which follows and in the drawings.

Fig. 1A shows a semiconductor device package 1 according to an embodiment of the present disclosure. Referring to fig. 1A, the semiconductor device package 1 of this embodiment includes a carrier 11, wherein the carrier 11 may be a PCB board or a substrate. The interposer 12 and the number of components 13, 14, 15, 16 may be disposed on a surface 111 of the carrier 11. The interposer 12 may be annular, and the components 13, 14, 15, 16 may be surrounded by the interposer 12. Referring to fig. 1A, the surface 111 of the carrier 11 is substantially divided into two regions 1121, 1122, where the region 1121 is located outside the annular interposer 12 and the region 1122 is located within the annular interposer 12.

When the encapsulation material 18 is to be formed on the surface 111 of the carrier 11 and the interposer 12 and the components 13, 14, 15, and 16 are encapsulated by using a molding process, the flow of the encapsulation material 18 will be non-uniform (refer to fig. 1B). The flow rate of the encapsulation material 18 through the region 1121 may be greater than the flow rate of the encapsulation material 18 through the region 1122 while the flow of the encapsulation material 18 may flow from the side 113 of the carrier 11 toward the side 114 of the carrier 11. As shown in fig. 1B, a majority of the region 1121 is covered by the encapsulating material 18, but only a small portion of the region 1122 is covered by the encapsulating material 18.

Fig. 2A shows a semiconductor device package 2 according to an embodiment of the present disclosure. Referring to fig. 2A, the semiconductor device package 2 of this embodiment includes a carrier 21, wherein the carrier 21 may be a PCB board or a substrate. Several interposers 221, 222, 223, 224, 225, 226 and several components 23, 24, 25, 26 may be disposed on the surface 211 of the carrier 2. Interposers 221 and 222 may be substantially aligned with each other. The interposers 223 and 224 may be substantially aligned with each other. The interposers 225 and 226 may be substantially aligned with each other. Referring to fig. 2A, the surface 211 of the carrier is divided into seven regions. Regions 2121, 2123, 2125, and 2125 do not have any intervening layers. Region 2122 includes interposers 221 and 222. Region 2124 includes interposers 223 and 224. Region 2126 includes interposer 225 and 226.

When the encapsulation material 28 is to be formed on the surface 211 of the carrier 21 and the interposer 221, 222, 223, 224, 225, 226 and the components 23, 24, 25 and 26 are encapsulated by using a molding process, the flow of the encapsulation material 28 will be non-uniform (refer to fig. 2B). The flow rate of the encapsulation material 28 through the regions 2121, 2123, 2125, 2127 may be greater than the flow rate of the encapsulation material 18 through the regions 2122, 2124, 2126 as the flow of the encapsulation material 28 may flow from the side 213 of the carrier 21 toward the side 214 of the carrier 21. As shown in fig. 2B, most of the regions 2121, 2123, 2125, 2127 are covered by the encapsulating material 28, but only a small portion of the regions 2122, 2124, 2126 are covered by the encapsulating material 28.

Fig. 3A shows a semiconductor device package 3 according to an embodiment of the present disclosure. Referring to fig. 3A, the semiconductor device package 3 of this embodiment includes a carrier 31, wherein the carrier 21 may be a PCB board or a substrate. A number of interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 and a number of components 33, 34, 35, 36, 37 may be disposed on surface 311 of carrier 3. The interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 may be randomly arranged on the surface 311 of the carrier 3. That is, the interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 can be arranged in an irregular pattern. This means that the pattern formed by the arrangement of the interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 is irregular in shape or form. Referring to fig. 3A, it appears that interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 are dispersed on carrier 31. In addition, the pattern formed by the arrangement of interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 is not a regular geometric shape. Further, at least one of the interposers 321, 322, 323, 324, 325, 326, 327, 328, 329 may have a redistribution layer. Further, the interposers 321 and 322, which may be arranged in an L-shape, may be integrated with each other.

When the encapsulation material 38 is to be formed on the surface 311 of the carrier 31 and the interposer 321, 322, 323, 324, 325, 326, 327, 328, 329 and the components 33, 34, 35, 36, 37 are encapsulated by using a molding process, the flow of the encapsulation material 28 will be smooth (refer to fig. 3B). For example, as shown in fig. 3B, the encapsulation material 38 flows from side 313 of the carrier 31 toward side 314 of the carrier 31. As the encapsulating material 38 flows to the middle portion of the surface 311 of the carrier 31, a majority of the left half of the surface 311 of the carrier 31 is covered by the encapsulating material 38. Thus, as the encapsulating material 38 flows to the side 314 of the carrier 31, a majority of the surface 311 of the carrier 31 will be covered by the encapsulating material 38.

Fig. 4A shows a semiconductor device package 4 according to an embodiment of the present disclosure. Referring to fig. 4A, the semiconductor device package 4 of this embodiment includes a carrier 41, wherein the carrier 21 may be a PCB board or a substrate. A number of interposers 421, 422, 423, 424, 425, 426, 427 and a number of components 43, 44, 45, 46, 47 may be disposed on a surface 411 of the carrier 4. The interposers 421, 422, 423, 424, 425, 426, 427 may be randomly arranged on the surface 411 of the carrier 4. That is, the interposers 421, 422, 423, 424, 425, 426, 427 may be arranged in an irregular pattern. This means that the pattern formed by the arrangement of the interposers 421, 422, 423, 424, 425, 426, 427 is irregular in shape or form. Referring to fig. 4A, it appears that interposers 421, 422, 423, 424, 425, 426, 427 are dispersed on carrier 41. In addition, the pattern formed by the arrangement of the interposers 421, 422, 423, 424, 425, 426, 427 is not a regular geometric shape.

When the encapsulation material 48 is to be formed on the surface 411 of the carrier 41 and the interposer 421, 422, 423, 424, 425, 426, 427 and the components 43, 44, 45, 46, 47 are encapsulated by using a molding process, the flow of the encapsulation material 28 will be smooth (refer to fig. 4B). For example, as shown in fig. 4B, encapsulation material 48 flows from side 413 of carrier 41 toward side 414 of carrier 41. As the encapsulation material 48 flows to the middle portion of the surface 411 of the carrier 41, a majority of the left half of the surface 411 of the carrier 41 is covered by the encapsulation material 48. Thus, as the encapsulation material 48 flows to the side 414 of the carrier 41, a majority of the surface 411 of the carrier 41 will be covered by the encapsulation material 48.

Fig. 5A shows a semiconductor device package 5 according to an embodiment of the present disclosure. Referring to fig. 5A, the semiconductor device package 5 of this embodiment includes a carrier 51, wherein the carrier 51 may be a PCB board or a substrate. A number of interposers 521, 522, 523, 524, 525 and a number of components 531, 532, 533, 534, 535 may be disposed on the surface 511 of the carrier 5. The interposers 521, 522, 523, 524, 525 may be randomly arranged on the surface 511 of the carrier 5. That is, the interposer layers 521, 522, 523, 524, 525 may be arranged in an irregular pattern. This means that the pattern formed by the arrangement of the interposers 521, 522, 523, 524, 525 is irregular in shape or form. Referring to fig. 5A, it appears that the interposers 521, 522, 523, 524, 525 are dispersed on the carrier 51. In addition, the patterns formed by the arrangement of the interposers 521, 522, 523, 524, 525 are not regular geometric shapes. Further, at least one of the interposers 521, 522, 523, 524, 525 may have a redistribution layer. Further, the encapsulation material 53 may be disposed on the surface 511 of the carrier 51 and encapsulate the interposer 521, 522, 523, 524, 525 and the components 531, 532, 533, 534, 535.

FIG. 5B illustrates a cross-sectional view along line I-I in FIG. 5A. As shown in fig. 5B, the encapsulation material 53 may encapsulate the outer sides of the surface 511, components 531, 532, and interposers 521 and 522 of the carrier. In particular, the interposer 521 and the interposer 522 may be separated from each other by the encapsulation material 53. Further, a portion of the top surface 5301 of the encapsulation material 53 may be lower than the top surface 5211 of the interposer 521 or the top surface 5221 of the interposer 522. The interposer 521 may include a plurality of conductive vias 5212, and the interposer 522 may include a plurality of conductive vias 5222. Referring to fig. 5B, each of the conductive vias 5212, 5222 can have an hourglass-shaped cross-section.

In addition, carrier 51 further includes a surface 512 opposite surface 511. Components 541, 542, 543, and 544 may be mounted on surface 512 of carrier 51. Encapsulation material 55 may encapsulate a portion of surface 512 of carrier 51 and components 541, 542, 543. That is, another portion of surface 512 of carrier 51 is not covered by encapsulation material 53. Additionally, as shown in fig. 5B, component 544 is disposed on a portion of surface 512 of carrier 51 that is not encapsulated by encapsulation material 53. Thus, the component 544 is also not encapsulated by the encapsulation material 53. Further, referring to fig. 5B, a compartment shielding structure 545 may be disposed between the components 541 and 542.

Fig. 6 shows a semiconductor device package 6 according to an embodiment of the present disclosure. Referring to fig. 6, the semiconductor device package 6 may include a carrier 61, wherein the carrier 61 may be a PCB board or a substrate. Interposers 621 and 622 and components 631, 632, 633, 634, 635, 636 can be disposed on surface 611 of carrier 61. The encapsulation material 63 may encapsulate the surface 611 of the carrier 61, the components 631, 632, 633, 634, 635, 636 and the outer sides of the interposers 621 and 622. In particular, the interposer 621 and the interposer 622 may be separated from each other by the encapsulation material 63. Further, a portion of the top surface 6301 of the encapsulation material 63 may be lower than the top surface 6211 of the interposer 621 or the top surface 6221 of the interposer 622. The interposer 621 may include a plurality of conductive vias 6212, and the interposer 622 may include a plurality of conductive vias 6222. Referring to fig. 6, each of the conductive vias 6212, 6222 may have an hourglass-shaped cross-section. The interposers 621 and/or 622 may have redistribution layers.

In addition, carrier 61 further includes a surface 612 opposite surface 611. Components 641, 642, 643, 644, 645, 646, 647, and 648 can be mounted on surface 612 of carrier 61. The encapsulating material 65 may encapsulate the surface 612 and components 641, 642, 643, 644, 645, 646, 647, and 648 of the carrier 61.

Fig. 7 shows a semiconductor device package 7 according to an embodiment of the present disclosure. Referring to fig. 7, the semiconductor device package 7 may include a carrier 71, wherein the carrier 71 may be a PCB board or a substrate. Interposers 721 and 722 and components 731, 732, 733, 734, 735, 736 can be disposed on surface 711 of carrier 71. In addition, an interposer 723 may be stacked on the interposers 721 and 722, wherein the interposer 723 may be a PCB board or a substrate. The cross-sectional width of interposer 723 is smaller than the cross-sectional width of carrier 71. Encapsulation material 73 may encapsulate a portion of surface 711 of carrier 71, components 732, 733, 734, 735, 736, interposers 721, 722, and surface 7231, and the outside of interposer 723. That is, another portion of the surface 711 of the carrier 71 is not covered by the encapsulation material 73. In addition, as shown in fig. 7, component 731 is disposed on the portion of surface 711 of carrier 71 that is not encapsulated by encapsulating material 73. Thus, component 731 is also not encapsulated by encapsulation material 73.

The interposer 721 and the interposer 722 may be separated from each other by the encapsulation material 73. Further, the interposer 721 can include a plurality of conductive vias 7212, and the interposer 722 can include a plurality of conductive vias 7222. Referring to fig. 7, each of the conductive vias 7212, 7222 can have an hourglass-shaped cross-section. The interposers 721 and/or 722 may have redistribution layers.

Further, referring to fig. 7, interposer 723 can have a surface 7232 that is exposed and opposite surface 7231. Two components 771, 772 can be disposed on the surface 7232 of the interposer 723. In particular, the components 771, 772 may be PCB boards or substrates.

In addition, carrier 71 further includes a surface 712 opposite surface 711. The components 741, 742, 743, 744, 745, 746 may be mounted on the surface 712 of the carrier 71, wherein all components 741, 742, 743, 744, 745, 746 may be passive components. The encapsulation material 75 may encapsulate the surface 712 and the components 741, 742, 743, 744, 745, 746 of the carrier 71.

Fig. 8 shows a semiconductor device package 8 according to an embodiment of the present disclosure. Referring to fig. 8, the semiconductor device package 8 may include a carrier 81, wherein the carrier 81 may be a PCB board or a substrate. Interposers 821 and 822 and components 831, 832, 833, 834, 835, 836 can be disposed on surface 811 of carrier 81. In addition, an interposer 823 may be stacked on the interposers 821 and 822, wherein the interposer 823 may be a PCB board or a substrate. The interposer 823 has a cross-sectional width less than the cross-sectional width of the carrier 81. Interposer 823 may include a surface 8231 facing surface 811 of carrier 81. The components 881, 882, 883 may be disposed on the surface 8231 of the interposer 823. The interposers 821 and 822 may be coupled to a surface 8231 of the interposer 823 when the interposer 823 is supported on the interposers 821 and 822. Encapsulation material 83 may encapsulate a portion of surface 811 of carrier 81, components 832, 833, 834, 835, 836, interposers 821, 822, components 881, 882, 883, and surface 8231, as well as the exterior side of interposer 823. That is, another portion of the surface 811 of the carrier 81 is not covered by the encapsulation material 83. In addition, as shown in fig. 8, a component 831 is disposed on the portion of surface 811 of carrier 81 that is not encapsulated by encapsulating material 83. Thus, the component 831 is also not encapsulated by the encapsulating material 83.

The interposer 821 and the interposer 822 can be separated from each other by an encapsulation material 83. In addition, the interposer 821 may include a plurality of conductive vias 8212, and the interposer 822 may include a plurality of conductive vias 8222. Referring to fig. 8, each of the conductive vias 8212, 8222 may have an hourglass-shaped cross-section. The interposers 821 and/or 822 may have redistribution layers.

Further, referring to fig. 8, the interposer 823 may have a surface 8232 exposed and opposite to the surface 8231. Two components 871, 872 can be disposed on a surface 8232 of the interposer 823. In particular, the components 871, 872 may be PCB boards or substrates.

In addition, carrier 81 further includes a surface 812 opposite surface 811. Components 841, 842, 843, 844, 845, 846, 847, 848 may be mounted on surface 812 of carrier 81. The encapsulating material 85 may encapsulate the surface 812 of the carrier 81 and the components 841, 842, 843, 844, 845, 846, 847, 848.

Fig. 9 shows a semiconductor device package 9 according to an embodiment of the present disclosure. Referring to fig. 9, the semiconductor device package 9 may include a carrier 91, wherein the carrier 91 may be a PCB board or a substrate. Interposers 921 and 922 and components 931, 932, 933, 934, 935, 936 may be disposed on a surface 911 of carrier 91. In addition, interposer 923 can be stacked on interposers 921 and 922, where interposer 823 can be a PCB board or a substrate. The interposer 923 has a cross-sectional width that is less than the cross-sectional width of the carrier 91. Interposer 923 can include surface 9231 facing surface 911 of carrier 91. The encapsulation material 93 may encapsulate a portion of the surface 911 of the carrier 91, the components 932, 933, 934, 935, 936, the interposers 921, 922 and the surface 9231, and the outer side of the interposer 923. That is, another portion of the surface 911 of the carrier 91 is not covered by the encapsulation material 93. In addition, as shown in fig. 9, the component 931 is disposed on a portion of the surface 911 of the carrier 91 that is not encapsulated by the encapsulating material 93. Thus, the component 931 is also not encapsulated by the encapsulating material 93.

The interposer 921 and the interposer 922 may be separated from each other by the encapsulation material 93. Further, the interposer 921 can include a plurality of conductive vias 9212, and the interposer 922 can include a plurality of conductive vias 9222. Referring to fig. 9, each of the conductive vias 9212, 9222 may have an hourglass-shaped cross-section. The interposers 921 and/or 922 may have redistribution layers.

Further, referring to fig. 9, interposer 923 can have a surface 9232 that is exposed and opposite surface 9231. Two components 971, 972 can be disposed on the surface 9232 of the interposer 923. In particular, the components 971, 972 may be PCB boards or substrates.

In addition, carrier 91 further includes a surface 912 opposite surface 811. The components 941, 942, 943, 944 and the encapsulation units 945, 946 may be mounted on the surface 912 of the carrier 91. The encapsulation material 95 may encapsulate the surface 912 of the carrier 91 as well as the components 941, 942, 943, 944 and the encapsulation units 945, 946. The compartment shielding structure 948 may be disposed between the packaged unit 945 and the component 942.

Further, the packaged unit 945 may include a substrate 9451 having a surface 9452. The components 9453, 9454, 9455 can be mounted on a surface 9452 of a substrate 9451. The encapsulation material 9456 may encapsulate the surface 9452 of the substrate 9451 and the components 9453, 9454, 9455. Additionally, a shield layer 9457 may be formed over the encapsulation material 9456 and electrically connected to the substrate 9451. In addition, the component 9458 can be embedded in the substrate 9451.

The package unit 946 may include a substrate 9461 having a surface 9462. The assemblies 9463, 9464, 9465 can be mounted on a surface 9462 of a substrate 9461. The encapsulation material 9466 may encapsulate the surface 9462 of the substrate 9461 and the components 9463, 9464, 9465. Furthermore, substrate 9461 has a surface 9468 opposite surface 9462 and facing surface 912 of carrier 91. The assembly 9469 and solder balls 9460 may be mounted to a surface 9468 of a substrate 9461. The package unit 946 may be mounted to a surface 9468 of a substrate 9461 by solder balls 9460. The encapsulation material 9471 may encapsulate the surface 9468 of the substrate 9461, the outside of the solder balls 9460, and the components 9469. Additionally, a shield layer 9467 may be formed over the encapsulation material 9466 and the encapsulation material 9471 and electrically connected to the substrate 9461.

Further, active or passive dice may be embedded in carrier 91 and/or substrate 9461.

References in this disclosure to the formation or positioning of a first feature over or on a second feature may include embodiments in which the first feature is formed or disposed in direct contact with the second feature, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can refer to the situation in which the event or circumstance occurs specifically, as well as the situation in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%.

For example, substantially parallel may refer to a range of angular variation of less than or equal to ± 10 ° relative to 0 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, substantially perpendicular may refer to a range of angular variation of less than or equal to ± 10 ° relative to 90 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be considered substantially flat if the displacement between the highest and lowest points of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms "a" and "the" can include the plural referents unless the context clearly dictates otherwise.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

While the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be construed in a limiting sense. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a difference between artistic renditions in the present disclosure and actual devices. There may be other embodiments of the invention not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention.