阅读说明：本技术 一种晶圆级的封装结构及封装方法 (Wafer-level packaging structure and packaging method ) 是由 任玉龙 曹立强 于 2019-11-25 设计创作，主要内容包括：本发明属于封装技术领域,具体涉及一种晶圆级的封装结构及封装方法。该晶圆级封装结构包括塑封层、第一晶圆、导电金属柱、重布线层、载片；该结构通过在塑封层内设置导电金属柱,其两端分别与重布线层实现电连接,第一晶圆正面与第一重布线层电连接,且第二重布线层设置在第一晶圆背面的方向,使晶圆级封装结构无需TSV工艺就可以实现背面电互联,通过设置第一重布线层,可以提高空间利用率；在实际应用中,第一重布线层可以实现第一晶圆的直接互连、提高空间利用率,便于第二重布线层布局,使其应用更广。(The invention belongs to the technical field of packaging, and particularly relates to a wafer-level packaging structure and a packaging method. The wafer level packaging structure comprises a plastic packaging layer, a first wafer, a conductive metal column, a rewiring layer and a carrier; according to the structure, the conductive metal columns are arranged in the plastic package layer, two ends of each conductive metal column are electrically connected with the redistribution layer respectively, the front side of the first wafer is electrically connected with the first redistribution layer, and the second redistribution layer is arranged in the direction of the back side of the first wafer, so that the back side of the wafer level package structure can be electrically interconnected without a TSV (through silicon via) process, and the space utilization rate can be improved by arranging the first redistribution layer; in practical application, the first redistribution layer can realize direct interconnection of the first wafer, improve the space utilization rate, facilitate the layout of the second redistribution layer and enable the second redistribution layer to be more widely applied.)

1. A wafer level package structure, comprising,

a plastic packaging layer;

the first wafer is wrapped in the plastic packaging layer, and the front surface of the first wafer is arranged opposite to the carrier;

the conductive metal column is arranged in the plastic package layer in a penetrating mode, the first end of the conductive metal column is arranged in the plastic package layer, and the second end of the conductive metal column is exposed out of one side of the plastic package layer;

a rewiring layer including a first rewiring layer and a second rewiring layer; the first redistribution layer is electrically connected with the front surface of the first wafer and the first end of the conductive metal column respectively; the second rewiring layer is arranged in the direction of the back surface of the first wafer and is electrically connected with the second end of the conductive metal column;

the carrier is bonded with the front side of the first wafer through a bonding layer; the slide glass is provided with a groove which is arranged opposite to the front surface of the first wafer.

2. The wafer level package structure of claim 1, further comprising,

and the first bonding pad is arranged on the front surface of the first wafer and is electrically connected with the first rewiring layer.

3. The wafer level package structure of claim 1, further comprising,

and the second bonding pad is arranged in the direction of the back surface of the first wafer and is electrically connected with the second rewiring layer.

4. The wafer-level package structure of claim 1, wherein the conductive metal pillar is a copper pillar.

5. A method for packaging the wafer level package structure of any one of claims 1-4, comprising the steps of,

bonding the front surface of the first wafer with a slide glass, and then forming an opening;

rewiring the opening to form a first rewiring layer;

forming a conductive metal column on the first redistribution layer, and then carrying out plastic package to form a plastic package layer;

exposing a second end of the conductive metal pillar;

and rewiring the conductive metal column to form a second rewiring layer, and forming a second bonding pad on the surface of the second rewiring layer to obtain the wafer-level packaging structure.

6. The packaging method according to claim 5, wherein the opening is formed by a mechanical cutting method or a dry etching method.

7. The packaging method according to claim 6, wherein the conductive metal pillar is formed by an electroplating process.

Technical Field

The invention belongs to the technical field of packaging, and particularly relates to a wafer-level packaging structure and a packaging method.

Background

Wafer Level Packaging (WLP) is one of the IC packaging methods, and as an advanced packaging technology, all the process steps are completed before the wafer is diced. Wafer level chip scale packaging is to combine wafer level packaging and chip scale packaging together, directly package the wafer at wafer level after the previous process of manufacturing the wafer is completed, and carry out interconnection salient points and test on the wafer.

Wafer level packaging obtains extremely rapid increase in MEMS and CIS (CMOS image sensor) due to the advantages of high packaging processing efficiency, light, thin, short and small packaging size, good electric heating performance and the like, interconnection lines in the packaging are not generally bonded by leads, and the first method is to directly manufacture a redistribution layer on a dielectric layer on the front surface of a tube core and redistribute a pad on the tube core into an I/O array pad on the packaging, but the method cannot be directly applied due to the fact that a cavity needs to be protected or a movable part is arranged; secondly, a groove or a slope is made on a tube core body material, a pad on the front surface of the tube core is connected to the side surface or the back surface through a plane printed line, and then an I/O leading-out end is made, but the method has the defects of abnormal packaging appearance, low reliability, low utilization rate of the area of the front surface/the back surface of the tube core and the like; the third is Through Silicon Vias (TSV), which connect to the back side directly from the die front side pad vertically Through the bulk material; however, the TSV technology needs to perform insulation treatment on the sidewall of the silicon via, and the insulation treatment needs to be performed under high temperature and high pressure conditions when the sidewall of the silicon via is subjected to insulation treatment, which affects the performance of the chip, and the conditions of the sidewall insulation treatment are harsh and difficult to control. Therefore, the provision of a new wafer level chip packaging method is of great significance to the technical field of packaging.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defects of high wafer level packaging cost, high technical difficulty, low space utilization rate, etc. in the prior art, thereby providing a wafer level packaging structure and a packaging method.

Therefore, the invention provides the following technical scheme.

The invention provides a wafer level package structure, which comprises,

a plastic packaging layer;

the first wafer is wrapped in the plastic packaging layer, and the front surface of the first wafer is arranged opposite to the carrier;

the conductive metal column is arranged in the plastic package layer in a penetrating mode, the first end of the conductive metal column is arranged in the plastic package layer, and the second end of the conductive metal column is exposed out of one side of the plastic package layer;

a rewiring layer including a first rewiring layer and a second rewiring layer; the first redistribution layer is electrically connected with the front surface of the first wafer and the first end of the conductive metal column respectively; the second rewiring layer is arranged in the direction of the back surface of the first wafer and is electrically connected with the second end of the conductive metal column;

the carrier is bonded with the front side of the first wafer through a bonding layer; the slide glass is provided with a groove which is arranged opposite to the front surface of the first wafer.

The wafer level package structure further comprises a plurality of chip-scale packages,

and the first bonding pad is arranged on the front surface of the first wafer and is electrically connected with the first rewiring layer.

The wafer level package structure further comprises a plurality of chip-scale packages,

and the second bonding pad is arranged in the direction of the back surface of the first wafer and is electrically connected with the second rewiring layer.

The conductive metal pillar is a copper pillar.

The invention also provides a method for packaging the wafer level packaging structure, which comprises the following steps,

bonding the front surface of the first wafer with a slide glass, and then forming an opening;

rewiring the opening to form a first rewiring layer;

forming a conductive metal column on the first redistribution layer, and then carrying out plastic package to form a plastic package layer;

exposing a second end of the conductive metal pillar;

and rewiring the conductive metal column to form a second rewiring layer, and forming a second bonding pad on the surface of the second rewiring layer to obtain the wafer-level packaging structure.

The forming method of the opening is a mechanical cutting method or a dry etching method.

The forming process of the conductive metal column is an electroplating process.

The technical scheme of the invention has the following advantages:

1. the invention provides a wafer level packaging structure, which comprises a plastic packaging layer and a first wafer, wherein the first wafer is wrapped in the plastic packaging layer, and the front surface of the first wafer is arranged opposite to a carrier; the conductive metal column is arranged in the plastic package layer in a penetrating mode, the first end of the conductive metal column is arranged in the plastic package layer, and the second end of the conductive metal column is exposed out of one side of the plastic package layer; a rewiring layer including a first rewiring layer and a second rewiring layer; the first redistribution layer is electrically connected with the front surface of the first wafer and the first end of the conductive metal column respectively; the second rewiring layer is arranged in the direction of the back surface of the first wafer and is electrically connected with the second end of the conductive metal column; the carrier is bonded with the front side of the first wafer through a bonding layer; the slide glass is internally provided with a groove which is arranged opposite to the front side of the first wafer; according to the structure, the conductive metal columns are arranged in the plastic package layer, two ends of each conductive metal column are electrically connected with the redistribution layer respectively, the front side of the first wafer is electrically connected with the first redistribution layer, and the second redistribution layer is arranged in the direction of the back side of the first wafer, so that the back side of the wafer level packaging structure can be electrically interconnected without a TSV (through silicon via) process, and the space utilization rate can be improved by arranging the first redistribution layer.

The wafer level packaging structure can realize back interconnection of the wafer structure without a TSV process, has the advantages of simple structure and high yield, can realize special gas or liquid airtight packaging, meets the packaging requirements of special chips such as MEMS and CIS, can be used for integration of multilayer heterogeneous chips, and is wide in application range.

2. According to the wafer-level packaging structure provided by the invention, the conductive metal column, the wafer, the redistribution layer and the bonding pad are electrically connected, so that the direct interconnection among the first wafers can be realized, the transmission distance can be reduced, the space is efficiently utilized, the diameter of the conductive metal column can be adjusted according to actual requirements, and more production requirements can be met. In practical application, the space utilization rate is improved, the layout of the second redistribution layer is convenient, and the application range is wider.

3. The packaging method of the wafer level packaging structure provided by the invention has the advantages of simple process flow, avoidance of TSV packaging technology, especially PECVD side wall insulation treatment, simple process flow, low cost and small technical difficulty, and no influence on the performance of a wafer and a chip.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a wafer level package structure according to an embodiment of the invention;

fig. 2A to 2F are schematic views illustrating a packaging process of a wafer level package structure according to embodiment 3 of the present invention;

fig. 3 is a top view of a first redistribution layer in a wafer level package structure flow diagram of embodiment 3 of the present invention in fig. 2C;

reference numerals:

1-a first wafer; 2-a first rewiring layer; 3-a second rewiring layer; 4-a first pad; 5-conductive metal posts; 6-plastic packaging layer; 7-a second pad; 8-a bonding layer; 9-carrying sheet;

1-1-a first wafer front side; 1-2 a first wafer back side;

5-1-a conductive metal pillar first end; 5-2-conductive metal pillar second end.

Detailed Description

The following examples are provided to further understand the present invention, not to limit the scope of the present invention, but to provide the best mode, not to limit the content and the protection scope of the present invention, and any product similar or similar to the present invention, which is obtained by combining the present invention with other prior art features, falls within the protection scope of the present invention.