阅读说明：本技术 封装结构 (Packaging structure ) 是由 陈韦志 郭宏瑞 胡毓祥 廖思豪 王博汉 朱永祺 卓鸿钧 于 2019-08-30 设计创作，主要内容包括：一种封装结构包括半导体管芯及重布线路结构。所述重布线路结构设置在所述半导体管芯上并电连接到所述半导体管芯,且包括图案化导电层、介电层及层间膜。所述介电层设置在所述图案化导电层上。所述层间膜夹置在所述介电层与所述图案化导电层之间,其中所述图案化导电层通过所述层间膜与所述介电层分离。(A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution routing structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an interlayer film. The dielectric layer is disposed on the patterned conductive layer. The interlayer film is interposed between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer by the interlayer film.)

1. A package structure, comprising:

a semiconductor die; and

a redistribution line structure disposed on and electrically connected to the semiconductor die and comprising:

patterning the conductive layer;

a dielectric layer disposed on the patterned conductive layer; and

an interlayer film interposed between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer by the interlayer film.

Technical Field

The disclosed embodiments relate to a package structure and a method for manufacturing the same.

Background

Semiconductor devices and integrated circuits are typically fabricated on a single semiconductor wafer. The dies of a wafer may be processed and packaged at the wafer level (wafer level) with other semiconductor devices or dies, and various techniques have been developed for wafer level packaging (e.g., forming redistribution routing structures/layers). In addition, such a package may be further integrated into a semiconductor substrate or carrier after dicing (dicing).

Disclosure of Invention

The embodiment of the disclosure provides a package structure including a semiconductor die and a redistribution circuit structure. The redistribution routing structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an interlayer film. The dielectric layer is disposed on the patterned conductive layer. The interlayer film is interposed between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer by the interlayer film.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-15 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

Fig. 16 is a flow chart illustrating a method of fabricating a package structure according to some embodiments of the present disclosure.

Fig. 17 and 18 are flow diagrams illustrating methods of fabricating a redistribution routing structure/layer of a package structure according to some embodiments of the present disclosure.

Fig. 19 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 20 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 21-32 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

Fig. 33 is a flow diagram illustrating a method of fabricating a redistribution routing structure/layer for a package structure according to some embodiments of the present disclosure.

Fig. 34 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 35 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 36-42 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure.

Fig. 43 is a flow diagram illustrating a method of fabricating a redistribution routing structure/layer for a package structure according to some embodiments of the present disclosure.

Fig. 44 is a schematic cross-sectional view of a package structure according to some example embodiments of the present disclosure.

Fig. 45 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 46 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure.

Fig. 47 is a flow diagram illustrating a method of fabricating a redistribution routing structure/layer of a package structure according to some embodiments of the present disclosure.

Fig. 48 is a schematic cross-sectional view of a package structure according to some example embodiments of the present disclosure.

Fig. 49 is a schematic cross-sectional view of a package structure according to some example embodiments of the present disclosure.

Fig. 50 is a schematic cross-sectional view illustrating an example of an interlayer film according to some embodiments of the present disclosure.

[ description of symbols ]

112: carrier

114: peeling layer

116: buffer layer

130. 130-1, 130-2, 130-3: semiconductor die

130 a: active surface

130 b: connecting pad

130 c: passivation layer

130 d: conducting hole

130e, 130 e: protective layer

130 f: backside surface

130 s: semiconductor substrate

140. 140': insulating packaging body

140 a: top surface

150. 250, 350, 450: redistribution circuit structure

151. 151a, 155-1, 155-2, 155-3, 155a, 255-1, 255-2, 255-3, 255-4, 255a, 355-1, 355-2, 355-3, 455-1, 455-2, 455-3, 455-4: interlayer film

152. 152-1, 152-2, 152-3, 156, 252-1, 252-2, 252-3, 252-4, 252a, 352, 356-1, 356-2, 356-3, 356 a', 452-1, 452-2, 452-3, 452-4: dielectric layer

153. 153-1, 153-2, 153-3, 153a, 253-1, 253-2, 253-3, 253-4, 353-1, 353-2, 353-3, 453-1, 453-2, 453-3, 453-4, SL 1: seed layer

154. 154-1, 154-2, 154-3, 254-1, 254-2a, 254-2b, 254-3, 254-4, 354-1, 354-2, 354-3, 454-1, 454-2a, 454-2b, 454-3, 454-4: patterned conductive layer

160: seed layer pattern

170. 180, 190: conductive element

And (3) CP: conductive pole

HD: holding device

O1, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12: opening of the container

P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12: packaging structure

PR 1: patterned photoresist layer

S10, S20, S30, S40, S41a, S41a-1, S41a-2, S41a-3, S41a-4, S41a-5, S41a-o, S41b, S41c, S41d, S42a, S42b, S42c, S42d, S43a, S43b, S43c, S43d, S44a, S44b, S44c, S44d, S45a, S45b, S45d, S46a, S46b, S46d, S47a, S50, S60: step (ii) of

S252-1, S252-2, S254-1, S254-2b, S255-1, S255-2: top surface

TH: thermal treatment

u1, u 2: under Ball Metal (UBM) Pattern

X: direction of rotation

Z: direction/stacking direction

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "under … … (beneath)", "under … … (below)", "under (lower)", "over … … (above)", "over (upper)" may be used herein to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Additionally, for ease of description, terms such as "first", "second", "third", "fourth", "fifth", and the like may be used herein to describe similar or different elements or features shown in the figures, and may be used interchangeably depending on the order of presentation or context of description.

Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structure may, for example, include test pads formed in a redistribution layer or on a substrate that enable testing of a 3D package or 3DIC, use of probes and/or probe cards (probe card), and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of known good dies (known good die) to improve yield (yield) and reduce cost.

Fig. 1-15 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig. 16 is a flow chart illustrating a method of fabricating a package structure according to some embodiments of the present disclosure. Fig. 17 and 18 are flow diagrams illustrating methods of fabricating a redistribution routing structure/layer of an encapsulation structure according to some embodiments of the present disclosure, wherein the methods of fig. 17 and 18 may be (but are not limited to) implemented in the method of fig. 16. In some embodiments, the method of manufacturing is part of a packaging process. In fig. 1 to 15, one (semiconductor) chip or die is shown to represent a plurality of (semiconductor) chips or dies of a wafer, and one (semiconductor) package structure is shown to represent a plurality of (semiconductor) package structures obtained after a (semiconductor) manufacturing method, to which the present disclosure is not limited.

In some embodiments, a carrier is provided according to step S10 shown in fig. 16. Referring to fig. 1, in some embodiments, a carrier 112 having a release layer 114 and a buffer layer 116 coated thereon is provided. In one embodiment, carrier 112 may be a glass carrier or any carrier suitable for carrying semiconductor wafers or reconstituted wafers (reconstitued wafers) for the manufacturing process of semiconductor packages.

In some embodiments, the exfoliation layer 114 is disposed on the carrier 112, and the material of the exfoliation layer 114 can be any material suitable for bonding and exfoliation of the carrier 112 relative to an overlying layer (e.g., the buffer layer 116) or for bonding and exfoliation of any wafer disposed thereon (e.g., the carrier 112). In some embodiments, the release layer 114 may include a release layer (e.g., a light-to-heat conversion ("LTHC") layer or an adhesive layer (e.g., a uv-curable adhesive or a heat-curable adhesive layer).

As shown in fig. 1, in some embodiments, a buffer layer 116 is disposed on the exfoliation layer 114, and the exfoliation layer 114 is located between the carrier 112 and the buffer layer 116. In some embodiments, the buffer layer 116 may be a layer of dielectric material. In some embodiments, the buffer layer 116 may be a polymer layer made of polyimide, Polybenzoxazole (PBO), benzocyclobutene (BCB), or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer 116 may be an Ajinomoto Build Film (ABF), a solder mask (SR), or the like. The top surface of the buffer layer 116 may be planarized and may have a high degree of coplanarity.

For example, the peeling layer 114 and the buffer layer 116 can be formed by a suitable fabrication technique such as spin-coating (spin-coating), lamination (deposition), deposition, and the like. The present disclosure is not particularly limited thereto.

In some embodiments, semiconductor dies are disposed on carrier 112 according to step S10 shown in fig. 16. In some embodiments, at least one semiconductor die 130 is provided. As shown in fig. 1, for example, the at least one semiconductor die 130 includes a plurality of semiconductor dies, such as semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3. In some embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 are picked and placed over carrier 112 and disposed on buffer layer 116. For example, as shown in fig. 1, semiconductor dies 130-1, 130-2, 130-3 are arranged side-by-side with each other along direction X, and direction X is perpendicular to the stacking direction Z of carrier 112, exfoliation layer 114, buffer layer 116, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3. As shown in fig. 1, only three semiconductor dies 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) are presented for purposes of illustration, however, it should be noted that the number of semiconductor dies 130 can be one or more than one, and the disclosure is not so limited.

In some embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 each include: a semiconductor substrate 130s having an active surface 130a and a backside surface 130f opposite the active surface 130 a; a plurality of pads 130b distributed on the active surface 130 a; a passivation layer 130c covering the active surface 130a and portions of the pads 130 b; a plurality of via holes 130d connected to the pads 130b exposed through the passivation layer 130 c; and a protective layer 130e disposed on the via hole 130 d. The pad 130b, the passivation layer 130c, the via 130d, and the passivation layer 130e are formed on the semiconductor substrate 130 s. The pad 130b is partially exposed through the passivation layer 130c, the via holes 130d are respectively disposed on the pad 130b and electrically connected to the pad 130b, and the passivation layer 130e covers the passivation layer 130c and the via holes 130d exposed through the via holes 130 d.

However, the present disclosure may not be limited thereto. For example, the via 130d and the passivation layer 130e may be omitted. In an alternative embodiment, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may each include: a semiconductor substrate 130s having an active surface 130a and a backside surface 130f opposite the active surface 130 a; the pads 130b are distributed on the active surface 130 a; and a passivation layer 130c covering the active surface 130a and portions of the pads 130 b.

The material of the semiconductor substrate 130s may include a silicon substrate including active components (e.g., transistors and/or memories, such as N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, etc.) and/or passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. In some embodiments, such active and passive components may be formed in a front-end-of-line (FEOL) process. In alternative embodiments, the semiconductor substrate 130s may be a bulk silicon substrate (e.g., a bulk monocrystalline silicon substrate), a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. The present disclosure is not so limited.

In addition, the semiconductor substrate 130s may further include an interconnect structure (not shown) disposed on the active surface 130 a. In some embodiments, the interconnect structure may include one or more interlayer dielectric layers and one or more patterned conductive layers alternately stacked to provide a wiring function for active and passive components embedded in the semiconductor substrate 130s, wherein the pad 130b may be referred to as an outermost layer of the patterned conductive layer. In one embodiment, the interconnect structure may be formed in a back-end-of-line (BEOL) process. For example, the interlayer dielectric layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and may be formed by deposition or the like. For example, the patterned conductive layer may be a patterned copper layer or other suitable patterned metal layer, and may be formed by electroplating or deposition. However, the present disclosure is not limited thereto.

For example, the pad 130b is an aluminum pad or other suitable metal pad. For example, the via 130d is a copper pillar, a copper alloy pillar, or other suitable metal pillar including copper metal. In some embodiments, the passivation layer 130c and the protection layer 130e may be a Polybenzoxazole (PBO) layer, a Polyimide (PI) layer, or other suitable polymers. In some alternative embodiments, the passivation layer 130c and the protection layer 130e may be made of inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. For example, the material of the passivation layer 130c may be the same as or different from the material of the protection layer 130 e.

Note that the at least one semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) may be referred to herein as a semiconductor chip or Integrated Circuit (IC). In an alternative embodiment, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 described herein may be semiconductor devices. In some embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may include one or more digital, analog, or mixed-signal chips, such as an application-specific integrated circuit ("ASIC") chip, a sensor chip, a wireless and Radio Frequency (RF) chip, a memory chip, a logic chip, or a voltage regulator chip.

In some embodiments, the at least one semiconductor die described herein may further include additional semiconductor dies that are of the same type or different types in addition to semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3. In alternative embodiments, the additional semiconductor die may include a digital chip, an analog chip, or a mixed signal chip, such as an ASIC chip, a sensor chip, a wireless and RF chip, a memory chip, a logic chip, or a voltage regulator chip. The present disclosure is not so limited.

In the present disclosure, it is understood that the illustrations of semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3, as well as other components, are schematic and not drawn to scale throughout the figures. In one embodiment, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may be identical. In alternative embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 may be different from each other.

With continued reference to fig. 1, in some embodiments, semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) is disposed directly on buffer layer 116, with backside surface 130f of each of semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 in physical contact with the buffer layer. However, the present disclosure is not limited thereto.

In an alternative embodiment, buffer layer 116 may optionally be omitted from exfoliation layer 114, with each of semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) then disposed on exfoliation layer 114 by a connecting film (not shown). In some embodiments, the first connecting film is located between the semiconductor die 130-1 and the lift-off layer 114, and two opposing sides of the first connecting film physically contact the backside surface 130f of the semiconductor die 130-1 and the lift-off layer 114. In some embodiments, the second connecting film is located between the semiconductor die 130-2 and the peeling layer 114, and two opposing sides of the second connecting film physically contact the backside surface 130f of the semiconductor die 130-2 and the peeling layer 114. In some embodiments, the third connecting film is located between the semiconductor die 130-3 and the peeling layer 114, and two opposing sides of the third connecting film physically contact the backside surface 130f of the semiconductor die 130-3 and the peeling layer 114. In some embodiments, semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3 are stably bonded to exfoliation layer 114 due to the above connecting films. In some embodiments, the above connection film may be, but is not limited to, a die attach film (die attach film) or layer made of an adhesive, an epoxy-based resin (epoxy-based resin), an acrylic polymer (acrylic polymer), other suitable insulating material, or the like, and it may or may not have a filler (e.g., silica, alumina, or the like) filled therein. The present disclosure is not so limited.

Referring to fig. 2, in some embodiments, semiconductor die 130 is encapsulated in insulating encapsulant 140 in accordance with step S20 shown in fig. 16. In some embodiments, an insulating encapsulant 140 is formed on buffer layer 116 and over carrier 112. As shown in fig. 2, for example, insulating encapsulant 140 fills at least the gaps between semiconductor die 130 (e.g., semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3). In some embodiments, an insulating encapsulant 140 covers semiconductor die 130. In other words, for example, the semiconductor die 130 is embedded in the insulating encapsulant 140 and is not exposed by the insulating encapsulant 140 in a accessible manner.

In some embodiments, the insulating encapsulation 140 is a molding compound formed by a molding process. In some embodiments, insulating encapsulant 140 may, for example, comprise a polymer (e.g., epoxy resin, phenolic resin, silicon-containing resin, or other suitable resin), a dielectric material, or other suitable material. In alternative embodiments, insulating enclosure 140 may comprise an acceptable insulating enclosure material. In some embodiments, the insulating envelope 140 may further include an inorganic filler or inorganic compound (e.g., silica, clay, etc.) that may be added thereto to optimize the Coefficient of Thermal Expansion (CTE) of the insulating envelope 140. The present disclosure is not so limited.

Referring to fig. 3, in some embodiments, insulating encapsulant 140 is planarized to form insulating encapsulant 140' exposing semiconductor die 130, according to step S30 of fig. 16. In some embodiments, as shown in fig. 3, after planarization, the top surface of semiconductor die 130 (e.g., the top surface of via 130d and the top surface of protective layer 130e of each of semiconductor die 130-1, semiconductor die 130-2, and semiconductor die 130-3) is exposed through top surface 140a of insulating encapsulant 140'. That is, for example, the top surface of the semiconductor die 130 becomes substantially flush (substandally level) with the top surface 140a of the insulating encapsulant 140'. In other words, the top surface of semiconductor die 130 and the top surface 140a of insulating encapsulant 140' are substantially coplanar with each other (substentially coplanar). In some embodiments, as shown in fig. 3, semiconductor die 130 is exposed in an accessible manner through insulating encapsulant 140'. That is, for example, the via 130d of the semiconductor die 130 is exposed in a manner accessible through the insulating encapsulant 140'.

For example, the insulating encapsulation 140 may be planarized by mechanical grinding or Chemical Mechanical Polishing (CMP). After the planarization step, a cleaning step may optionally be performed, for example, to clean and remove residues resulting from the planarization step. However, the present disclosure is not so limited and the planarization step may be performed by any other suitable method.

In some embodiments, during planarization of insulating encapsulant 140, vias 130d and protective layer 130e of semiconductor die 130-1, semiconductor die 130-2, and/or semiconductor die 130-3 may also be planarized. In some embodiments, a planarization step may be performed, for example, on the overmolded insulating encapsulant 140 to planarize the top surface 140a of the insulating encapsulant 140' and the top surfaces of the vias 130d and the protective layer 130e of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3.

In some embodiments, redistribution routing structure 150 is formed over semiconductor die 130 and insulating encapsulant 140' in accordance with step S40 of fig. 16 (e.g., involving steps S41 a-S47 a of fig. 17 and steps S41 a-1-S41 a-5 and S41a-o of fig. 18). In some embodiments, as shown in fig. 4-12, the redistribution line structure 150 includes an interlayer film 151, a dielectric layer 152 (e.g., dielectric layer 152-1, dielectric layer 152-2, and dielectric layer 152-3), a seed layer 153 (e.g., seed layer 153-1, seed layer 153-2, and seed layer 153-3), a patterned conductive layer 154 (e.g., patterned conductive layer 154-1, patterned conductive layer 154-2, and patterned conductive layer 154-3), an interlayer film 155 (e.g., interlayer film 155-1, interlayer film 155-2, and interlayer film 155-3), and a dielectric layer 156. However, in the present disclosure, the number of layers of the dielectric layer 152, the seed layer 153, the patterned conductive layer 154 and the interlayer film 155 is not limited to the number of layers illustrated in fig. 4 to 12, wherein the number of layers of the dielectric layer 152, the seed layer 153, the patterned conductive layer 154 and the interlayer film 155 may be one or more than one. In some embodiments, the dielectric layer 152, the seed layer 153, the patterned conductive layer 154, and the interlayer film 155 are interposed between the interlayer film 151 and the dielectric layer 156 and are sequentially stacked.

Referring to fig. 4, in some embodiments, an interlayer film 151a is formed on the via hole 130d of each of the semiconductor die 130-1, the semiconductor die 130-2, and the semiconductor die 130-3 exposed by the protective layer 130e and the insulating encapsulant 140', according to step S41a shown in fig. 17. In some embodiments, forming the interlayer film 151a may include (but is not limited to): an adhesive precursor is applied to semiconductor die 130 (step S41a-3 shown in fig. 18), at aboutPerforming a thermal process at a workable temperature (workable temperature) of 30 ℃ to about 80 ℃ for 1 to 5 minutes to cause the adhesive precursor to form a bond with the via 130d of the semiconductor die 130 therebetween (step S41a-4 shown in fig. 18), and removing the adhesive precursor that is not bonded to the via 130d of the semiconductor die 130 by cleaning (step S41a-5 shown in fig. 18); thereby forming an interlayer film 151a on the via hole 130 d. In some embodiments, prior to applying the adhesive precursor on the semiconductor die 130, a pre-cleaning step may be performed to remove any undesired substances or particles remaining on the vias 130d of the semiconductor die 130 (step S41a-1 shown in fig. 18). For example, the precleaning step includes using, for example, CX-100 (e.g., citric acid) or other suitable chemicals (e.g., HCl or H)₂SO₄) And the like. In some embodiments, after the pre-cleaning step, a rinsing step (using Deionized (DI) water) may be performed to remove chemicals used in the pre-cleaning process (step S41a-2 shown in fig. 18). In addition, after each of the cleaning steps, such as step S41a-2 and/or step S41a-5, a drying step (step S41a-o shown in FIG. 18) may optionally be performed, for example, by using nitrogen gas at a workable temperature of about 30 ℃ to about 80 ℃ for 1 minute.

In some embodiments, the binder precursor comprises a compound represented by the following formula:

wherein nitrogen (N) atoms in the above chemical formula are respectively bonded to copper (Cu) atoms contained in the via 130d of the semiconductor die 130 and/or provided by the via 130d of the semiconductor die 130 to form a three-dimensional network structure including- (Cu-N) -bonds during the thermal process in step S41 a-4. The interlayer film 151a is formed on the top surface of the via hole 130d of the semiconductor die 130 by cross-linking between N atoms of the adhesive precursor and Cu atoms of the via hole 130d of the semiconductor die 130. In some embodiments, the thickness of the interlayer film 151a is greater than or substantially equal to 50nm and less than or substantially equal to 350nm as measured along the direction Z.

In the above chemical formula, Ar is an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulae (1) to (35):

in the above formula, R¹Represents a hydrogen atom, a substituted alkyl chain (alkyl chain) or an unsubstituted alkyl chain having a linear-like structure, a branched-like structure, a comb-like structure, or a star-like structure, or an aromatic ring (aromatizing). In the present disclosure, R is directly bonded in the formula¹One of the two N atoms in the ring of (a) is bonded to a hydrogen atom to form a group-NH, as shown above.

In the above formula, R²To R³Each independently substituted alkylene or unsubstituted alkylene, wherein n1 and n2 are each independently integers ranging from 1 to 30. In one embodiment, R²To R³The same as each other or different from each other. In one embodiment, n1 and n2 are the same as or different from each other.

In the above chemical formula, X and Y are each independently-H, -OH, -SH, -F, -Cl, -Br, -I, carboxyl (carboxyl group), ester (ester group), amine (amine group), quaternary ammonium cation (quaternary ammonium), trimethylsilyl (trimethylsilyl group), triethylsilyl (trimethylsilyl group), sulfo (sulfo group), carbonyl (carboxyl group), carbonate (carbonate ester group), or amide (amide group). Or epoxy groups (epoxy groups). In one embodiment, X and Y are the same as or different from each other.

For example, fig. 50 partially schematically shows the bonding relationship between the interlayer film 151a and the via 130d of the semiconductor die 130, where R is a hydrogen atom, an alkyl chain, or an aromatic ring. However, the present disclosure is not limited thereto. In addition, a top layer of Cu atoms (shown in fig. 50) may be further bonded to the compound contained in the binder precursor. As shown below, in the present disclosure, for example, the interlayer film 151a is formed in a layer having a copper complex of an imidazole derivative.

In some embodiments, applying the adhesive precursor on the semiconductor die 130 may include coating an adhesive precursor mixture on the semiconductor die 130, wherein the adhesive precursor mixture includes 0.01 weight percent (wt%) to 100 wt% of the adhesive precursor. In other words, the amount of binder precursor is about 0.01 wt% to about 100 wt% and the amount of solvent is about 0 wt% to about 99.99 wt%, based on the total amount of binder precursor mixture. For example, the aforementioned solvent refers to a solvent capable of enabling the binder precursor to be uniformly distributed therein without reacting therewith. In some embodiments, the solvent may be deionized water having a pH greater than 7.

Referring to fig. 5, in some embodiments, a dielectric layer 152-1 is formed on the interlayer film 151a according to step S42a shown in fig. 17. In some embodiments, the dielectric layer 152-1 is formed by (but not limited to): a blanket layer of dielectric material (blanket layer) is formed over the structure illustrated in fig. 4 to completely cover the interlayer film 151a, and patterned to form a dielectric layer 152-1. In some embodiments, during patterning of the blanket layer of dielectric material to form the dielectric layer 152-1, the interlayer film 151a is also patterned, with a plurality of openings O1 formed in the interlayer film 151a and the blanket layer of dielectric material to form the interlayer film 151 and the dielectric layer 152-1, respectively. In other words, the via 130d of the semiconductor die 130 is exposed in a manner that can be reached through the interlayer film 151 and the dielectric layer 152-1 via the opening O1.

In some embodiments, the material of the dielectric layer 152-1 may be polyimide, Polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, and the like, which may be patterned using a photolithography process and/or an etching process. In some embodiments, the dielectric layer 152-1 may be formed by a suitable fabrication technique such as spin-on coating (spin-on coating), Chemical Vapor Deposition (CVD) (e.g., plasma-enhanced chemical vapor deposition (PECVD)), and the like.

Referring to fig. 6, in some embodiments, a seed layer 153a is formed over the dielectric layer 152-1, in accordance with step S43a shown in fig. 17. In some embodiments, seed layer 153a is formed on dielectric layer 152-1 and extends into opening O1 formed in dielectric layer 152-1 and interlayer film 151 to physically contact via 130d of semiconductor die 130, the portion of dielectric layer 152-1, and the portion of interlayer film 151 (exposed through opening O1) exposed through opening O1. In other words, the seed layer 153a penetrates the dielectric layer 152-1 and the interlayer film 151, and the sidewalls of the opening O1 are completely covered with the seed layer 153 a.

In some embodiments, the seed layer 153a is formed over the carrier 112 in the form of a blanket layer made of a metal or metal alloy material, to which the present disclosure is not limited. In some embodiments, the seed layer 153a is referred to as a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, the seed layer 153a comprises titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, and the like. For example, the seed layer 153a may include a titanium layer and a copper layer over the titanium layer. The seed layer 153a may be formed by sputtering (sputtering), Physical Vapor Deposition (PVD), or the like. In some embodiments, the seed layer 153a may be conformally formed on the dielectric layer 152-1 by sputtering and contacts the dielectric layer 152-1, the interlayer film 151 and the via 130d exposed through the opening O1.

Referring to fig. 7, in some embodiments, a patterned conductive layer 154-1 is formed on the seed layer 153a, according to step S44a shown in fig. 17. In some embodiments, the patterned conductive layer 154-1 may be formed by (but is not limited to): a blanket layer of conductive material is formed over the structure depicted in fig. 6 to completely cover the seed 153a and patterned to form a patterned conductive layer 154-1.

In one embodiment, the patterned conductive layer 154-1 may be made of a conductive material (e.g., copper, a copper alloy, aluminum, an aluminum alloy, or a combination thereof) formed by electroplating or deposition and may be patterned using a photolithography process and an etching process. In some embodiments, the patterned conductive layer 154-1 may be a patterned copper layer or other suitable patterned metal layer. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing inevitable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

Referring to fig. 8, in some embodiments, the seed layer 153a is patterned to form a seed layer 153-1, according to step S45a shown in fig. 17. In some embodiments, the seed layer 153a is patterned using the patterned conductive layer 154-1 as an etch mask to form the seed layer 153-1. For example, the etching process may be a dry etching process (dry etching process), a wet etching process (wet etching process), or a combination thereof; the present disclosure is not so limited. In other words, for example, in a perpendicular projection (e.g., a perpendicular projection along direction Z) on insulating encapsulant 140', patterned conductive layer 154-1 completely overlaps seed layer 153-1. In some embodiments, as shown in fig. 8, the patterned conductive layer 154-1 is electrically connected to the semiconductor die 130 by physically connecting the seed layer 153-1 and the vias 130 d.

Referring to fig. 9, in some embodiments, an interlayer film 155a is formed on the patterned conductive layer 154-1 and the seed layer 153-1 according to step S46a shown in fig. 17. The formation of the interlayer film 155a is the same as or similar to the process of forming the interlayer film 151a described in fig. 4 using the adhesive precursor described in the method shown in fig. 18, and thus, for the sake of brevity, no further description will be given herein. As shown in fig. 9, for example, the patterned conductive layer 154-1 is completely surrounded by the interlayer film 155a and the seed layer 153-1, wherein the interlayer film 155a physically contacts both the seed layer 153-1 and the patterned conductive layer 154-1.

Referring to fig. 10, in some embodiments, dielectric layer 152-2 is formed in accordance with step S47a shown in fig. 17. In some embodiments, dielectric layer 152-2 is formed by (but not limited to): a blanket layer of dielectric material is formed over the structure depicted in fig. 9 to completely cover the interlayer film 155a and patterned to form the dielectric layer 152-2. In some embodiments, during patterning of the blanket layer of dielectric material to form the dielectric layer 152-2, the interlayer film 155a is also patterned, with a plurality of openings O2 formed in the interlayer film 155a and the blanket layer of dielectric material to form the interlayer film 155-1 and the dielectric layer 152-2, respectively. In other words, the opening O2 penetrates the interlayer film 155-1 and the dielectric layer 152-2, and thus a portion of the patterned conductive layer 154-1 is exposed in a accessible manner through the interlayer film 155-1 and the dielectric layer 152-2 via the opening O2.

As shown in fig. 10, the interlayer film 151 is interposed between the via 130d and the dielectric layer 152-1, wherein the interlayer film 151 serves as a copper diffusion barrier between the conductive layer and the dielectric layer (e.g., the via 130d and the dielectric layer 152-1), and since a diffusion rate of copper atoms from the conductive layer (e.g., a copper layer) to the dielectric layer is reduced by the interlayer film 151, a copper diffusion phenomenon is greatly suppressed. And, as a result, voids created between the conductive layer and the dielectric layer due to copper atom diffusion (e.g., copper atom diffusion from the conductive layer to the dielectric layer) are significantly reduced. Accordingly, the adhesive strength between the via 130d and the dielectric layer 152-1 is enhanced due to the interlayer film 151, and delamination (delamination) between the via 130d and the dielectric layer 152-1 is suppressed.

In some embodiments, as shown in fig. 10, an interlayer film 155-1 is sandwiched between the patterned conductive layer 154-1 and the dielectric layer 152-2. Due to the interlayer film 155-1, adhesive strength between the patterned conductive layer 154-1 and the dielectric layer 152-2 and between the seed layer 153-1 and the dielectric layer 152-2 is enhanced, and delamination between the patterned conductive layer 154-1 and the dielectric layer 152-2 and between the seed layer 153-1 and the dielectric layer 152-2 is suppressed.

In one embodiment, the material of the dielectric layer 152-2 may be the same as the material of the dielectric layer 152-1. In an alternative embodiment, the material of dielectric layer 152-2 may be different from the material of dielectric layer 152-1. The present disclosure is not so limited.

Referring to fig. 11, in some embodiments, a seed layer 153-2, a patterned conductive layer 154-2, an interlayer film 155-2, and a dielectric layer 152-3 are sequentially formed on the structure illustrated in fig. 10. The formation and material of the seed layer 153-2 are the same as or similar to those of the seed layer 153-1 described in fig. 6-8, the formation and material of the patterned conductive layer 154-2 is the same as or similar to those of the patterned conductive layer 154-1 described in fig. 7, the formation and material of the interlayer film 155-2 is the same as or similar to those of the interlayer film 155-1 described in fig. 9 and 10, and the formation and material of the dielectric layer 152-3 is the same as or similar to those of the dielectric layer 152-2 formed in fig. 10, and thus, further description thereof is omitted herein.

In some embodiments, a seed layer 153-2 is formed on the dielectric layer 152-2 and extends into the opening O2 formed in the interlayer film 155-1 and the dielectric layer 152-2 to physically contact the patterned conductive layer 154-1 exposed through the opening O2 in addition to portions of the interlayer film 155-1 and portions of the dielectric layer 152-2 (exposed through the opening O2). In other words, the seed layer 153-2 penetrates the dielectric layer 152-2 and the interlayer film 155-1, and the sidewalls of the opening O2 are completely covered by the seed layer 153-2. In some embodiments, the patterned conductive layer 154-2 is formed on the seed layer 153-2 (e.g., in physical contact with the seed layer 153-2), wherein a projected area of the patterned conductive layer 154-2 overlaps a projected area of the seed layer 153-2 in a perpendicular projection along direction Z on the insulating encapsulant 140'. For example, as shown in fig. 11, the patterned conductive layer 154-2 is electrically connected to the patterned conductive layer 154-1 through the seed layer 153-2.

In some embodiments, an interlayer film 155-2 and a dielectric layer 152-3 are formed on the patterned conductive layer 154-2, wherein the interlayer film 155-2 is interposed between the patterned conductive layer 154-2 and the dielectric layer 152-3, and between the seed layer 153-2 and the dielectric layer 152-3. Due to the interlayer film 155-2, adhesive strength between the patterned conductive layer 154-2 and the dielectric layer 152-3 and between the seed layer 153-2 and the dielectric layer 152-3 is enhanced, and delamination between the patterned conductive layer 154-2 and the dielectric layer 152-3 and between the seed layer 153-2 and the dielectric layer 152-3 is suppressed.

Referring to fig. 12, in some embodiments, a seed layer 153-3, a patterned conductive layer 154-3, an interlayer film 155-3, and a dielectric layer 156 are sequentially formed on the structure illustrated in fig. 11. The formation/material of the seed layer 153-3 is the same as or similar to the process and material for forming the seed layer 153-1 described in fig. 6-8, the formation/material of the patterned conductive layer 154-3 is the same as or similar to the process and material for forming the patterned conductive layer 154-1 described in fig. 7, the formation/material of the interlayer film 155-3 is the same as or similar to the process and material for forming the interlayer film 155-1 described in fig. 9 and 10, and the formation/material of the dielectric layer 156 is the same as or similar to the process and material for forming the dielectric layer 152-2 described in fig. 10, and thus, the description thereof is omitted herein.

In some embodiments, a seed layer 153-3 is formed on the dielectric layer 152-3 and extends into the opening O3 formed in the interlayer film 155-2 and the dielectric layer 152-3 to physically contact the patterned conductive layer 154-2 exposed through the opening O3 in addition to portions of the interlayer film 155-2 and portions of the dielectric layer 152-3 (exposed through the opening O3). In other words, the seed layer 153-3 penetrates the dielectric layer 152-3 and the interlayer film 155-2, and the sidewalls of the opening O3 are completely covered by the seed layer 153-3. In some embodiments, the patterned conductive layer 154-3 is formed on the seed layer 153-3 (e.g., in physical contact with the seed layer 153-3), wherein a projected area of the patterned conductive layer 154-3 overlaps a projected area of the seed layer 153-3 in a perpendicular projection along direction Z on the insulating encapsulant 140'. For example, as shown in fig. 12, the patterned conductive layer 154-3 is electrically connected to the patterned conductive layer 154-2 through the seed layer 153-3.

In some embodiments, an interlayer film 155-3 and a dielectric layer 156 are formed on the patterned conductive layer 154-3, wherein the interlayer film 155-3 is interposed between the patterned conductive layer 154-3 and the dielectric layer 156, and between the seed layer 153-3 and the dielectric layer 156. Due to the interlayer film 155-3, the adhesive strength between the patterned conductive layer 154-3 and the dielectric layer 156 and between the seed layer 153-3 and the dielectric layer 156 is enhanced, and delamination between the patterned conductive layer 154-3 and the dielectric layer 156 and between the seed layer 153-3 and the dielectric layer 156 is suppressed.

In some embodiments, as shown in fig. 12, portions of the patterned conductive layer 154-3 are exposed through a plurality of openings O4 formed in the dielectric layer 156 and the interlayer film 155-3 to electrically connect to subsequently formed connectors. At this time, the redistribution circuit structure 150 of the package structure P1 is completed.

Referring to fig. 10, 11, and 12 together, in some embodiments, a redistribution routing structure 150 is formed over the semiconductor die 130 and the insulating encapsulant 140', wherein the redistribution routing structure 150 is electrically connected to the semiconductor die 130 (e.g., semiconductor die 130-1, 130-2, 130-3). For example, the redistribution line structure 150 is formed on the top surface of the semiconductor die 130 (e.g., the top surface of the via 130d and the top surface of the protection layer 130e of the semiconductor die 130) and the top surface 140a of the insulating encapsulation 140'. In some embodiments, the redistribution circuit structure 150 is electrically connected to the semiconductor die 130 through the via 130d and the pad 130 b. In some embodiments, the rerouting circuit structure 150 is referred to as a front side rerouting layer of the semiconductor die 130 for providing routing functionality. In some embodiments, the semiconductor die 130 is located between the redistribution routing structure 150 and the buffer layer 116, and the insulating encapsulant 140' is located between the redistribution routing structure 150 and the buffer layer 116. As shown in fig. 12, the semiconductor dies 130-1, 130-2, 130-3 are in electrical communication with each other, for example, through a redistribution routing structure 150.

In the present disclosure, the layers formed in fig. 11 (e.g., the seed layer 153-2, the patterned conductive layer 154-2, the interlayer film 155-2, and the dielectric layer 152-3) and the layers formed in fig. 12 (e.g., the seed layer 153-3, the patterned conductive layer 154-3, the interlayer film 155-3, and the dielectric layer 156) may be respectively referred to as one layer of the first constituent layer (first build-up) of the redistribution routing structure 150. For illustrative purposes, two first constituent layers are included in the reroute route structure 150 shown in FIG. 12; however, the present disclosure is not limited thereto. The number of first constituent layers included in the redistribution routing structure 150 is not limited in this disclosure. In one embodiment, the number of first constituent layers included in the reroute route structure 150 may be zero. For example, both the first constituent layer formed in fig. 11 and the first constituent layer formed in fig. 12 may be optionally omitted from the redistribution line structure 150. In alternative embodiments, the number of first constituent layers included in the reroute route structure 150 may be one or more than one.

Referring to fig. 13, in some embodiments, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are formed over the redistribution routing structure 150 according to step S50 shown in fig. 16. In some embodiments, as shown in fig. 13, the seed layer patterns 160 are each located between a respective one of the conductive elements 170 and the dielectric layer 156 of the redistribution routing structure 150. Due to the seed layer pattern 160, the adhesive strength between the conductive element 170 and the dielectric layer 156 is enhanced. In some embodiments, the seed layer pattern 160 is directly on the portion of the patterned conductive layer 154-3 exposed through the opening O4 formed in the dielectric layer 156 and the interlayer film 155-3. As shown in fig. 13, in some embodiments, the seed layer pattern 160 is electrically connected to the redistribution routing structure 150, and the conductive element 170 is electrically connected to the redistribution routing structure 150 through the seed layer pattern 160.

In some embodiments, the conductive element 170 is electrically connected to the semiconductor die 130 through the redistribution routing structure 150 and the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-1 through the redistribution line structure 150 and corresponding ones of the seed layer patterns 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-2 by respective ones of the redistribution routing structure 150 and the seed layer pattern 160. For example, some of the conductive elements 170 are electrically connected to the semiconductor die 130-3 through the redistribution line structure 150 and corresponding ones of the seed layer patterns 160.

In some embodiments, the seed layer pattern 160 is formed by (but not limited to): forming a blanket layer of seed layer material (not shown) over the dielectric layer 156; forming conductive elements 170 on the blanket layer of seed layer material; the blanket layer of seed layer material is patterned using conductive elements 170 as a mask. In some embodiments, a blanket layer of seed layer material is formed over the dielectric layer 156 and extends into the opening O4 formed in the dielectric layer 156 and the interlayer film 155-3 to physically and electrically contact the patterned conductive layer 154-3 exposed through the opening O4, to physically contact portions of the dielectric layer 156 and portions of the interlayer film 155-3 (exposed through the opening O4). In other words, the blanket layer of seed layer material penetrates through dielectric layer 156 and interlayer film 155-3, and the sidewalls of opening O4 are completely covered by the blanket layer of seed layer material. The formation and material of the blanket layer of seed layer material is the same as or similar to the formation and material of seed layer 153a and thus will not be described in detail herein.

In some embodiments, the formation of the conductive element 170 may be formed by: forming a patterned photoresist layer (not shown) having a plurality of openings exposing portions of the seed layer 160a by photolithography; and immersing the entire structure including the patterned photoresist layer formed thereon in a plating solution to plate the conductive element 170 on the blanket layer of seed layer material, the conductive element 170 corresponding in position to the portion of the blanket layer of seed layer material exposed through the opening formed in the patterned photoresist layer. In one embodiment, the patterned photoresist layer may be formed through a coating process, a photolithography process, and the like. In some embodiments, the material of the patterned photoresist layer includes, for example, a positive resist material or a negative resist material suitable for a patterning process such as a photolithographic process using a mask or a photolithographic process without a mask (e.g., electron-beam (e-beam) writing or ion beam writing). Due to the patterned photoresist layer, the size and number of conductive elements 170 can be easily modified by adjusting the size and number of openings in the patterned photoresist layer. As shown in fig. 13, the conductive element 170 includes, for example, a copper pillar, a copper via, or the like; the present disclosure is not so limited.

After the conductive elements 170 are formed, the patterned photoresist layer is removed to expose the blanket layer of seed layer material that is not covered by the conductive elements 170. In one embodiment, the patterned photoresist layer is removed by an acceptable ashing process (ashing process) and/or photoresist stripping process (photoresist stripping process), for example using oxygen plasma or the like, and the disclosure is not limited thereto.

In some embodiments, the blanket layer of seed layer material is patterned using the conductive elements 170 as an etch mask to form the seed layer pattern 160. For example, the etching process may be a dry etching process, a wet etching process, or a combination thereof; the present disclosure is not so limited. In other words, the blanket layer of seed layer material not covered by the conductive element 170 is removed to form the seed layer pattern 160. In some embodiments, as shown in fig. 13, the sidewalls of the seed layer pattern 160 are aligned with the sidewalls of a respective one of the conductive elements 170.

Referring to fig. 14, in some embodiments, the entire structure depicted in fig. 13 is flipped (upside down) with carrier 112 according to step S60 shown in fig. 16, wherein conductive elements 170 are placed to retention devices HD, and carrier 112 is then peeled off from buffer layer 116. In some embodiments, the retention device HD may be a tape (tape), a carrier film (carrier film), or a suction pad (suction pad). The present disclosure is not so limited.

In some embodiments, buffer layer 116 is easily separated from carrier 112 due to exfoliation layer 114. In some embodiments, the carrier 112 is detached from the buffer layer 116 by a peeling process, and the carrier 112 and the peeling layer 114 are removed. In some embodiments, as shown in fig. 14, the buffer layer 116 is exposed. In one embodiment, the lift-off process is a laser lift-off process. During the peeling step, the package structure P1 is fixed using the holding device HD before peeling the carrier 112 and the peeling layer 114.

Referring to fig. 15, in some embodiments, the conductive element 170 is released from the retention device HD to form a package structure P1. In some embodiments, a singulation process is performed to singulate the plurality of package structures P1 interconnected therebetween into individual and separate package structures P1 prior to releasing conductive elements 170 from retention device HD. In one embodiment, the dicing (singulation) process is a wafer dicing process including mechanical blade sawing or laser dicing. The present disclosure is not so limited. At this point, the fabrication of the package structure P1 is completed.

However, the present disclosure is not limited thereto. In alternative embodiments, the conductive elements 170 may include solder balls or Ball Grid Array (BGA) balls, see the package structure P2 shown in fig. 19. In other alternative embodiments, the package structure may further include a plurality of conductive pillars CP, see package structure P3 illustrated in fig. 20.

Fig. 19 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Referring to fig. 15 and 19 together, a package structure P1 shown in fig. 15 is similar to the package structure P2 shown in fig. 19; such that elements that are similar or substantially the same as those described above will be given the same reference numerals, and some details or descriptions (e.g., formation and materials) of the same elements and their relationships (e.g., relative positioning arrangements and electrical connections) will not be repeated herein. For such an embodiment as shown in fig. 19 where the conductive elements 170 are solder balls or BGA balls, the seed layer pattern 160 is replaced by an under-ball metallurgy (UBM) pattern u1 to prevent solder material from diffusing from the conductive elements 170 to the redistribution structure 150, thereby ensuring the performance of the package structure P2. In some embodiments, the material of the UBM pattern u1 may include copper, nickel, titanium, tungsten, or an alloy thereof, etc., and may be formed in multiple layers (e.g., having different materials in any two adjacent layers in the UBM pattern u 1) by, for example, an electroplating process. The number of UBM patterns u1 is not limited in this disclosure.

Fig. 20 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Referring to fig. 19 and 20 together, a package structure P2 shown in fig. 19 is similar to the package structure P3 shown in fig. 20; such that elements that are similar or substantially the same as those described above will be given the same reference numerals, and some details or descriptions (e.g., formation and materials) of the same elements and their relationships (e.g., relative positioning arrangements and electrical connections) will not be repeated herein. For such an embodiment including conductive pillars CP as shown in fig. 20, conductive pillars CP are arranged alongside semiconductor die 130 in direction X and embedded in insulating encapsulant 140'. In some embodiments, the conductive pillar CP may be a via, such as an integrated fan-out (InFO) via. For simplicity, only two conductive pillars CP are presented in fig. 20 for illustration purposes, however, it should be noted that the number of conductive pillars CP may be less than two or more than two; the present disclosure is not so limited. The number of conductive pillars CP to be formed may be selected based on requirements.

In some embodiments, both ends of each of the conductive pillars CP are exposed through the insulating encapsulant 140'. For example, the conductive pillars CP are sandwiched between the buffer layer 116 and the redistribution routing structure 150, wherein a first end of each conductive pillar CP is physically connected to the redistribution routing structure 150, and the conductive pillars CP are electrically connected to the semiconductor die 130 through the redistribution routing structure 150. For example, the conductive pillars CP are formed on the buffer layer 116 by photolithography, plating, a photoresist stripping process, or any other suitable method. In one embodiment, the conductive pillar CP may be formed by (but is not limited to): forming a mask pattern (not shown) covering the buffer layer 116, the mask pattern having a plurality of openings exposing portions of the buffer layer 116; forming a metal material filling the plurality of openings to form a plurality of conductive pillars CP by electroplating or deposition; and then removing the mask pattern. For example, the material of the conductive pillar CP may include a metal material, such as copper or a copper alloy. However, the present disclosure is not limited thereto.

With continued reference to fig. 20, in some embodiments, a plurality of openings O5 are formed in the buffer layer 116 to expose the second end of each of the conductive pillars CP. The number of openings O5 is not limited in this disclosure and may be specified based on requirements and design layout. In some embodiments, a plurality of conductive elements 190 are respectively formed on the second end of each of the conductive pillars CP exposed by the opening O5, and a plurality of UBM patterns u2 are respectively formed between one of the conductive pillars CP and a corresponding one of the conductive elements 190. However, the present disclosure is not so limited, and in alternative embodiments, the UBM pattern u2 may be omitted based on the design layout and requirements. The formation and material of the conductive element 190 are the same as or similar to those of the conductive element 180, and the formation and material of the UBM pattern u2 are the same as or similar to those of the UBM pattern u1, and thus are not described in detail herein. As shown in fig. 20, conductive element 190 is electrically connected to semiconductor die 130 through UBM pattern u2, conductive pillar CP and redistribution routing structure 150. For example, after the conductive element 190 is disposed on the conductive pillar CP, a package structure P3 with a dual-side terminal (dual-side terminal) is completed.

In still other alternative embodiments, additional semiconductor elements (not shown) may be disposed on the redistribution routing structure 150 by the seed layer pattern 160 and/or the UBM patterns u1, u2 in addition to the conductive elements 170 in fig. 13 and/or the conductive elements 180 in fig. 19-20 to be electrically connected to at least one of the semiconductor dies 130. In some embodiments, the additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in this disclosure and may be specified based on requirements and design layout.

Fig. 21-32 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig. 33 is a flow diagram illustrating a method of fabricating a redistribution routing structure/layer for a package structure according to some embodiments of the present disclosure. Elements that are similar or substantially the same as previously described elements will be given the same reference numerals and some details or description of the same elements will not be repeated herein. Referring to fig. 15 and 32, a package structure P4 shown in fig. 32 is similar to the package structure P1 shown in fig. 15; the difference is that in package P4, rerouting structure 150 is replaced by rerouting structure 250.

In some embodiments, redistribution routing structures 250 are formed over semiconductor die 130 and insulating encapsulant 140' using the process described in fig. 21-29. In some embodiments, as shown in fig. 21-29, the redistribution line structure 250 includes a dielectric layer 252 (e.g., dielectric layer 252-1, dielectric layer 252-2, dielectric layer 252-3, and dielectric layer 252-4), a seed layer 253 (e.g., seed layer 253-1, seed layer 253-2, seed layer 253-3, and seed layer 253-4), a patterned conductive layer 254 (e.g., patterned conductive layer 254-1, patterned conductive layer 254-2a, patterned conductive layer 254-2b, patterned conductive layer 254-3, and patterned conductive layer 254-4), and an interlayer film 255 (e.g., interlayer film 255-1, interlayer film 255-2, and interlayer film 255-3, and interlayer film 255-4). However, in the present disclosure, the number of layers of the dielectric layer 252, the seed layer 253, the patterned conductive layer 254 and the interlayer film 255 is not limited to the number of layers illustrated in fig. 21 to 29, wherein the number of layers of the dielectric layer 252, the seed layer 253, the patterned conductive layer 254 and the interlayer film 255 may be one or more than one. In some embodiments, the dielectric layer 252, the seed layer 253, the patterned conductive layer 254, and the interlayer film 255 are formed on the insulating encapsulant 140' and sequentially stacked.

Referring to fig. 21, in some embodiments, after the process as described in fig. 3, a seed layer SL1 is formed on semiconductor die 130 and insulating encapsulant 140' in accordance with step S41b shown in fig. 33. For example, seed layer SL1 is formed on semiconductor die 130 and insulating encapsulant 140' in the form of a blanket layer made of a metal or metal alloy material, although the disclosure is not limited thereto. In some embodiments, seed layer SL1 is referred to as a metal layer, which may be a single layer or a composite layer comprising multiple sub-layers formed of different materials. In some embodiments, seed layer SL1 may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, and the like. For example, seed layer SL1 may include a titanium layer and a copper layer over the titanium layer. Seed layer SL1 may be formed, for example, using sputtering, PVD, or the like. In some embodiments, seed layer SL1 may be conformally formed over semiconductor die 130 and insulating encapsulant 140' by sputtering. As shown in fig. 21, in some embodiments, seed layer SL1 physically contacts via 130d of semiconductor die 130 and top surface 140a of insulating encapsulant 140'.

A patterned photoresist layer PR1 is formed on the seed layer SL1, wherein the patterned photoresist layer PR1 includes, for example, at least one opening O6. In some embodiments, as shown in fig. 21, a plurality of openings O6 are formed in the patterned photoresist layer PR 1. In one embodiment, the patterned photoresist layer PR1 may be formed through a coating process, a photolithography process, and the like. The number of openings O6 may, for example, correspond to the number of subsequently formed conductive structures (e.g., conductive pillars or vias). However, the present disclosure is not limited thereto. As shown in fig. 21, portions of seed layer SL1 are exposed through openings O6 formed in patterned photoresist layer PR1, respectively. In some embodiments, the material of the patterned photoresist layer PR1 includes, for example, a positive resist material or a negative resist material suitable for a patterning process such as a photolithographic process using a mask or a photolithographic process without a mask (e.g., electron beam (e-beam) writing or ion beam writing).

Referring to fig. 22, in some embodiments, a patterned conductive layer 254-1 is formed in the openings O6, respectively, in accordance with step S42b shown in fig. 33. In some embodiments, the patterned conductive layer 254-1 is formed by a plating process, which may include electroplating or electroless plating (electroplating), or the like, or any other suitable method. In one embodiment, the patterned conductive layer 254-1 may be formed by: a metal material filling the opening O6 is formed by electroplating or deposition to form the patterned conductive layer 254-1. In one embodiment, the material of the patterned conductive layer 254-1 may include a metal material, such as copper or a copper alloy. The number of patterned conductive layers 254-1 may be selected based on requirements and may be adjusted by varying the number of openings O6. In some embodiments, the material of the patterned conductive layer 254-1 may be the same as the material of the patterned conductive layer 154-1. In other embodiments, the material of the patterned conductive layer 254-1 may be different from the material of the patterned conductive layer 154-1.

With continued reference to fig. 22, for example, after the patterned conductive layer 254-1 is formed, the patterned photoresist layer PR1 is removed. In one embodiment, the patterned photoresist layer PR1 is removed by an acceptable ashing process and/or photoresist stripping process, for example using an oxygen plasma or the like. The present disclosure is not so limited.

Referring to fig. 23, in some embodiments, seed layer SL1 is patterned to form seed layer 253-1 in accordance with step S43b shown in fig. 33. In some embodiments, portions of seed layer SL1 (shown in fig. 22) not covered by patterned conductive layer 254-1 are removed to form seed layer 253-1. In some embodiments, seed layer SL1 is etched using patterned conductive layer 254-1 as an etch mask to form seed layer 253-1. For example, the etching process may include a dry etching process or a wet etching process. As shown in fig. 23, the seed layer 253-1 includes, for example, one or more conductive segments that are mechanically (physically) isolated and electrically isolated from each other. In some embodiments, as shown in fig. 23, the seed layer 253-1 is mechanically (physically) and electrically connected to a respective one of the patterned conductive layers 254-1. In some embodiments, the sidewalls of the seed layer 253-1 are aligned with the sidewalls of a corresponding one of the patterned conductive layers 254-1. As shown in fig. 23, patterned conductive layer 254-1 is electrically connected to semiconductor die 130 through seed layer 253-1. In some embodiments, the material of seed layer 253-1 may be the same as the material of seed layer 153-1. In other embodiments, the material of seed layer 253-1 may be different from the material of seed layer 153-1.

Referring to fig. 24, in some embodiments, an interlayer film 255a is formed to cover the seed layer 153-1 and the patterned conductive layer 254-1, according to step S44b shown in fig. 33. The formation and materials of the interlayer film 255a are the same as or similar to the process for forming the interlayer film 151a as described in fig. 4 according to the method shown in fig. 18, and thus are not described in detail herein. As shown in fig. 24, for example, patterned conductive layer 254-1 is wrapped by interlayer film 255a and seed layer 253-1 together.

Referring to fig. 25, in some embodiments, a dielectric layer 252a is formed on the interlayer film 255a according to step S45b shown in fig. 33. The dielectric layer 252a is formed by (but not limited to) the following: a blanket layer of dielectric material is formed over the structure depicted in fig. 24 to completely cover the interlayer film 155a and the semiconductor die 130 and insulating encapsulant 140' exposed by the interlayer film 155 a. In some embodiments, the material of the dielectric layer 252a may be polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, combinations thereof, and the like. In some embodiments, the dielectric layer 252a may be formed by a suitable fabrication technique, such as spin-on coating, CVD (e.g., PECVD), and the like.

Referring to fig. 26, in some embodiments, a planarization step is performed on the dielectric layer 252a to form a dielectric layer 252-1, according to step S46b shown in fig. 33. For example, the dielectric layer 252a may be planarized by mechanical polishing or CMP. In some embodiments, the material of dielectric layer 252a may be the same as the material of dielectric layer 152-1. In other embodiments, the material of the dielectric layer 252a may be different from the material of the dielectric layer 152-1.

During the planarization of the dielectric layer 252a, the interlayer film 255a is also planarized to form an interlayer film 255-1 exposing the top surface S254-1 of the patterned conductive layer 254-1. As shown in fig. 26, for example, sidewalls of the patterned conductive layer 254-1 and sidewalls of the seed layer 253-1 are wrapped by the interlayer film 255-1. In some embodiments, the material of the interlayer film 255-1 may be the same as the material of the interlayer film 155-1. In other embodiments, the material of the interlayer film 255-1 may be different from the material of the interlayer film 155-1. In some embodiments, for example, a planarization step may be performed on the dielectric layer 252a to planarize the top surface S252-1 of the dielectric layer 252-1, the top surface S254-1 of the patterned conductive layer 254-1, and the top surface S255-1 of the interlayer film 255-1. For example, the top surface S254-1 of the patterned conductive layer 254-1 and the top surface S255-1 of the interlayer film 255-1 are exposed in an accessible manner through the top surface S252-1 of the dielectric layer 252-1.

During the planarization of the dielectric layer 252a and the interlayer film 255a, the patterned conductive layer 254-1 may also be planarized. After the planarization step, a cleaning step may optionally be performed, for example, to clean and remove residues resulting from the planarization step. However, the present disclosure is not so limited and the planarization step may be performed by any other suitable method. Due to the interlayer film 255-1, the adhesive strength between the patterned conductive layer 254-1 and the dielectric layer 252-1 and between the seed layer 253-1 and the dielectric layer 252-1 is enhanced, and delamination between the patterned conductive layer 254-1 and the dielectric layer 252-1 and between the seed layer 253-1 and the dielectric layer 252-1 is suppressed. In the present disclosure, the layers formed in fig. 21 to 26 (e.g., the seed layer 253-1, the patterned conductive layer 254-1, the interlayer film 255-1, and the dielectric layer 252-1) may be referred to as one layer of the second constituent layer (second sidewall-up layer) of the re-routing structure 250.

Referring to fig. 27, in some embodiments, a seed layer 253-2, a patterned conductive layer 254-2a, a patterned conductive layer 254-2b, an interlayer film 255-2, and a dielectric layer 252-2 are sequentially formed on a dielectric layer 252-1. In the present disclosure, the layers formed in FIG. 27 (e.g., the seed layer 253-2, the patterned conductive layer 254-2a/254-2b, the interlayer film 255-2, and the dielectric layer 252-2) may be referred to as one layer of a third constituent layer (third build-up layer) of the redistribution routing structure 250. Note that in the present disclosure, the plating process of the patterned conductive layer 254-2b shares the same seed layer (e.g., seed layer 253-2) as the plating process of the patterned conductive layer 254-2a, where different patterned photoresist layers having different sized openings are used in the formation of the patterned conductive layers 254-2a and 254-2 b. That is, the seed layer 253-2 may serve as a seed layer for plating both the patterned conductive layers 254-2a and 254-2 b. The above patterned photoresist layer with openings of different sizes is formed of the same or similar material and formation as the patterned photoresist layer PR1, and thus will not be described in detail herein.

In some embodiments, the seed layer 253-2 is directly on the dielectric layer 252-1, the patterned conductive layer 254-1 and the interlayer film 255-1. For example, seed layer 253-2 is electrically connected to patterned conductive layer 254-1. In some embodiments, patterned conductive layer 254-2a is on seed layer 253-2 and is electrically connected to seed layer 253-2. In some embodiments, the sidewalls of the seed layer 253-2 are aligned with the sidewalls of a corresponding one of the patterned conductive layers 254-2 a. As shown in fig. 27, the seed layer 253-2 is interposed between the patterned conductive layer 254-2a and the patterned conductive layer 254-1, and the patterned conductive layer 254-2a is electrically connected to the patterned conductive layer 254-1 through the seed layer 253-2.

In some embodiments, the patterned conductive layer 254-2b is formed on the patterned conductive layer 254-2 a. As shown in fig. 27, for example, the patterned conductive layer 254-2b is directly on the patterned conductive layer 254-2a and is electrically connected to the patterned conductive layer 254-2 a. In some embodiments, the patterned conductive layer 254-2a is sandwiched between the patterned conductive layer 254-2b and the seed layer 253-2, and the patterned conductive layer 254-2b is electrically connected to the seed layer 253-2 by the patterned conductive layer 254-2 a.

The formation and material of seed layer 253-2 is the same as or similar to the formation and material of seed layer 253-1 and therefore will not be described in detail herein. The formation and material of each of the patterned conductive layers 254-2a/254-2b is the same as or similar to the formation and material of the patterned conductive layer 254-1, and thus will not be described in detail herein.

In some embodiments, the interlayer film 255-2 covers at least a portion of the patterned conductive layer 254-2b, the patterned conductive layer 254-2a, and the seed layer 253-2. As shown in fig. 27, for example, the sidewalls of the patterned conductive layers 254-2a, 254-2b and the sidewalls of the seed layer 253-2 are wrapped by the interlayer film 255-2, wherein the top surface S254-2b of the patterned conductive layer 254-2b is exposed by the top surface S255-2 of the interlayer film 255-2. The formation and materials of the interlayer film 255-2 are the same as or similar to those of the interlayer film 255-1, and thus are not described in detail herein.

In some embodiments, the dielectric layer 252-2 is located on the patterned conductive layer 254-2b, the patterned conductive layer 254-2a, the seed layer 253-2, the interlayer film 255-2, and the dielectric layer 252-1. As shown in fig. 27, the top surface S255-2 of the interlayer film 255-2 and the top surface S254-2b of the patterned conductive layer 254-2b are exposed in an accessible manner through the top surface S252-2 of the dielectric layer 252-2. The formation and materials of the dielectric layer 252-2 are the same as or similar to those of the dielectric layer 252-1, and thus are not described in detail herein. Due to the interlayer film 255-2, the adhesive strength between the patterned conductive layer 254-2 and the dielectric layer 252-2 and between the seed layer 253-2 and the dielectric layer 252-2 is enhanced, and delamination between the patterned conductive layer 254-2 and the dielectric layer 252-2 and between the seed layer 253-2 and the dielectric layer 252-2 is suppressed.

Referring to fig. 28, in some embodiments, a seed layer 253-3, a patterned conductive layer 254-3, an interlayer film 255-3, and a dielectric layer 252-3 are sequentially formed on a dielectric layer 252-2. In the present disclosure, the layers formed in fig. 28 (e.g., the seed layer 253-3, the patterned conductive layer 254-3, the interlayer film 255-3, and the dielectric layer 252-3) may be referred to as one layer of the fourth constituent layer (four build-up layer) of the redistribution routing structure 250.

In some embodiments, the seed layer 253-3 is directly on the dielectric layer 252-2, the patterned conductive layer 254-2b, and the interlayer film 255-2. As shown in fig. 28, the seed layer 253-3 is electrically connected to the patterned conductive layer 254-2 b. In some embodiments, patterned conductive layer 254-3 is on seed layer 253-3 and is electrically connected to seed layer 253-3. In some embodiments, the sidewalls of the seed layer 253-3 are aligned with the sidewalls of a respective one of the patterned conductive layers 254-3. As shown in fig. 28, the seed layer 253-3 is interposed between the patterned conductive layer 254-3 and the patterned conductive layer 254-2b, and the patterned conductive layer 254-3 is electrically connected to the patterned conductive layer 254-2b through the seed layer 253-3. The formation and material of seed layer 253-3 is the same as or similar to the formation and material of seed layer 253-1 and therefore will not be described in detail herein. The formation and material of the patterned conductive layer 254-3 are the same as or similar to those of the patterned conductive layer 254-1, and thus are not described in detail herein.

In some embodiments, an interlayer film 255-3 is formed to cover the patterned conductive layer 254-3 and the seed layer 253-3. As shown in fig. 28, for example, sidewalls of the patterned conductive layer 254-3 and sidewalls of the seed layer 253-3 are wrapped by the interlayer film 255-3. The formation and material of the interlayer film 255-3 are the same as or similar to those of the interlayer film 155-2, and thus will not be described in detail herein. In some embodiments, a dielectric layer 252-3 is formed on the interlayer film 255-3, the patterned conductive layer 254-3, the seed layer 253-3, and the dielectric layer 252-2. As shown in fig. 28, for example, a plurality of openings O7 are formed in the dielectric layer 252-3 and the interlayer film 255-3, wherein portions of the patterned conductive layer 254-3 are exposed through the openings O7. The formation and materials of the dielectric layer 252-3 are the same as or similar to those of the dielectric layer 152-2, and thus are not described in detail herein. Due to the interlayer film 255-3, the adhesive strength between the patterned conductive layer 254-3 and the dielectric layer 252-3 and between the seed layer 253-3 and the dielectric layer 252-3 is enhanced, and delamination between the patterned conductive layer 254-3 and the dielectric layer 252-3 and between the seed layer 253-3 and the dielectric layer 252-3 is suppressed.

Referring to fig. 29, in some embodiments, a seed layer 253-4, a patterned conductive layer 254-4, an interlayer film 255-4, and a dielectric layer 252-4 are sequentially formed. The formation and materials of the seed layer 253-4, the patterned conductive layer 254-4, the interlayer film 255-4 and the dielectric layer 252-4 are the same as or similar to those of the seed layer 153-3, the patterned conductive layer 154-3, the interlayer film 155-3 and the dielectric layer 256, and thus, detailed descriptions thereof will be omitted. In the present disclosure, the layers formed in FIG. 29 (e.g., the seed layer 253-4, the patterned conductive layer 254-4, the interlayer film 255-4, and the dielectric layer 252-4) may be referred to as one of the first constituent layers of the redistribution line structure 250.

In some embodiments, the seed layer 253-4 is located on the dielectric layer 252-3 and extends into the opening O7 formed in the interlayer film 255-3 and the dielectric layer 252-3 to physically contact the patterned conductive layer 254-3 exposed through the opening O7. In other words, the seed layer 253-4 penetrates through the dielectric layer 252-3 and the interlayer film 255-3 and is directly on the patterned conductive layer 254-3 exposed through the opening O7. In some embodiments, the sidewalls of opening O7 are completely covered by seed layer 253-4. In some embodiments, patterned conductive layer 254-4 is on seed layer 253-4 (e.g., physically contacting seed layer 253-4), wherein a projected area of patterned conductive layer 254-4 overlaps a projected area of seed layer 253-4 in a perpendicular projection along direction Z on insulating encapsulant 140'. For example, as shown in fig. 29, the patterned conductive layer 254-4 is electrically connected to the patterned conductive layer 254-3 through the seed layer 253-4. In some embodiments, the interlayer film 255-4 and the dielectric layer 252-4 are on the patterned conductive layer 254-4 and the seed layer 253-4, with the interlayer film 255-4 interposed between the patterned conductive layer 254-4 and the dielectric layer 252-4, and between the seed layer 253-4 and the dielectric layer 252-4. Due to the interlayer film 255-4, the adhesive strength between the patterned conductive layer 254-4 and the dielectric layer 252-4 and between the seed layer 253-4 and the dielectric layer 252-4 is enhanced, and delamination between the patterned conductive layer 254-4 and the dielectric layer 252-4 and between the seed layer 253-4 and the dielectric layer 252-4 is suppressed.

As shown in fig. 29, portions of the patterned conductive layer 254-4 are exposed through a plurality of openings O8 formed in the dielectric layer 252-4 and the interlayer film 255-4 to be electrically connected to a connector to be formed later. At this time, the redistribution circuit structure 250 of the package structure P4 is completed. The re-routing circuit structure 250 further obtains a fine pitch (fine pitch) structure for routing functions according to the method of fig. 32 and the processes described in fig. 21-26, 27, and/or 28 (e.g., using the second, third, and fourth constituent layers). As shown in fig. 29, the semiconductor dies 130-1, 130-2, 130-3 are in electrical communication with each other, for example, through a redistribution routing structure 250.

For illustrative purposes, four constituent layers (e.g., one layer each of the first, second, third, and fourth constituent layers) are included in the reroute route structure 250 shown in fig. 29; however, the present disclosure is not limited thereto. The number of first, second, third, and fourth constituent layers included in the reroute route structure 250 is not limited in this disclosure. For example, the number of first, second, and third constituent layers included in the reroute route structure 250 may be one or more than one, while the number of fourth constituent layers included in the reroute route structure 250 may be zero, one, or more than one.

Referring to fig. 30, in some embodiments, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are sequentially formed over the redistribution routing structure 150. Due to the seed layer pattern 160, the adhesive strength between the conductive element 170 and the dielectric layer 252-4 is enhanced. In some embodiments, the seed layer pattern 160 is directly on the portion of the patterned conductive layer 254-4 exposed through the opening O8 formed in the dielectric layer 252-4 and the interlayer film 255-4.

In some embodiments, the seed layer pattern 160 is electrically connected to the redistribution routing structure 250, and the conductive element 170 is electrically connected to the redistribution routing structure 250 through the seed layer pattern 160. As shown in fig. 30, for example, the conductive elements 170 are electrically connected to the semiconductor die 130 through the redistribution line structure 250 and the corresponding one of the seed layer patterns 160. The formation and materials of the seed layer pattern 160 and the conductive element 170 have been described in the process of fig. 13 and thus will not be described in detail herein.

Referring to fig. 31, in some embodiments, the entire structure depicted in fig. 30 is flipped (upside down) with carrier 112, with conductive element 170 placed to holding device HD and carrier 112 peeled from buffer layer 116 by peeling layer 114. During the peeling step, the package structure P4 is fixed using the holding device HD before peeling the carrier 112 and the peeling layer 114.

Referring to fig. 32, in some embodiments, the conductive element 170 is released from the retention device HD to form a package structure P4. In some embodiments, a dicing (singulation) process is performed to dice the plurality of package structures P4 interconnected therebetween into individual and separate package structures P4 prior to releasing the conductive elements 170 from the retention device HD. At this point, the fabrication of the package structure P4 is completed.

In some embodiments, the conductive elements 170 may include copper pillars, copper vias, and the like, see the package structure P4 illustrated in fig. 32. However, the disclosure is not limited thereto, and in alternative embodiments, the conductive elements 170 may include solder balls or BGA balls, while the seed layer pattern 160 is replaced with a UBM pattern u1, see the package structure P5 illustrated in fig. 34. In other alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, while the seed layer pattern 160 is replaced with the UBM pattern u1, and may further include a plurality of conductive pillars CP in the presence of the conductive element 190 and the UBM pattern u2, see the package structure P6 illustrated in fig. 35. However, the present disclosure is not so limited, and in alternative embodiments, the UBM pattern u2 may be omitted based on the design layout and requirements.

In still other alternative embodiments, additional semiconductor elements (not shown) may be disposed on the redistribution routing structure 250 through the seed layer pattern 160 and/or the UBM patterns u1, u2 in addition to the conductive elements 170 in fig. 32 and/or the conductive elements 180 in fig. 34-35. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in this disclosure and may be specified based on requirements and design layout.

As shown in package structures P1 through P6, in redistribution routing structure 150/250, dielectric layers (e.g., 152-1/152-2/152-3/156, 829) are formed as interlayer films (e.g., 151/155-1/155-2/155-3, 255-1/255-2/255-3/255-4) are located between dielectric layers (e.g., 152-1/152-2/152-3/156, 252-1/252-2/252-3/252-4) and patterned conductive layers (e.g., 154-1/154-2/154-3, 254-1/254-2a/254-2b/254-3/254-4), 252-1/252-2/252-3/252-4) are separated from the patterned conductive layer (e.g., 154-1/154-3/154-3, 254-1/254-2a/254-2b/254-3/254-4) by an interlayer film (e.g., 151/155-1/155-2/155-3, 255-1/255-2/255-3/255-4), and thus voids generated therebetween are greatly reduced, thereby suppressing the delamination phenomenon. In addition, as shown in the package structures P1 through P6, in the redistribution circuit structure 150/250, since the interlayer film (e.g., the interlayer film 151, 255-1) is located between the via hole (e.g., the via hole 130d) and the dielectric layer (e.g., the dielectric layer 152-1, 252-1), the dielectric layer (e.g., the dielectric layer 152-1, 252-1) is separated from the via hole (e.g., the via hole 130d) by the interlayer film (e.g., the interlayer film 151, 255-1), and thus the void generated therebetween is also reduced, thereby suppressing the delamination phenomenon. In the present disclosure, each of the interlayer films 151-1, 155-1 to 155-3, 255-1 to 255-3 has a thickness greater than or substantially equal to 50nm and less than or substantially equal to 350nm as measured along the direction Z. Due to this configuration, the adhesive strength between one of the patterned conductive layers and its corresponding one of the dielectric layers is enhanced, and thus better yield and reliability of the package structures P1 to P6 are achieved.

Fig. 36-42 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig. 43 is a flow diagram illustrating a method of fabricating a redistribution routing structure/layer for a package structure according to some embodiments of the present disclosure. Elements that are similar or substantially the same as previously described elements will be given the same reference numerals and some details or description of the same elements will not be repeated herein. Referring to fig. 15 and 42, the package structure P7 shown in fig. 42 is similar to the package structure P1 shown in fig. 15; the difference is that in package P7, rerouting structure 150 is replaced by rerouting structure 350.

In some embodiments, redistribution routing structures 350 are formed and disposed on semiconductor die 130 and insulating encapsulant 140' using the processes described in fig. 36-39. In some embodiments, as shown in fig. 36-39, the redistribution line structure 350 includes a dielectric layer 352, a seed layer 353 (e.g., seed layer 353-1, seed layer 353-2, and seed layer 353-3), a patterned conductive layer 354 (e.g., patterned conductive layer 354-1, patterned conductive layer 354-2, and patterned conductive layer 354-3), an interlayer film 355 (e.g., interlayer film 355-1, interlayer film 355-2, and interlayer film 255-3), and a dielectric layer 356 (e.g., dielectric layer 356-1, dielectric layer 356-2, and dielectric layer 356-3). However, in the present disclosure, the number of layers of the seed layer 353, the patterned conductive layer 354, the interlayer film 355, and the dielectric layer 356 is not limited to the number of layers illustrated in fig. 31 to 39. The number of layers of the seed layer 253, the patterned conductive layer 254, the interlayer film 355, and the dielectric layer 356 may be one or more than one. In some embodiments, the seed layer 253, the patterned conductive layer 254, the interlayer film 355, and the dielectric layer 356 are formed on the dielectric layer 252 and sequentially stacked.

Referring to fig. 36, in some embodiments, after the process as described in fig. 3, a dielectric layer 352 is formed over semiconductor die 130 and insulating encapsulant 140' in accordance with step S41c shown in fig. 43. The formation and material of dielectric layer 352 is the same as or similar to the formation and material of dielectric layer 152-1, and thus will not be described in detail herein. As shown in fig. 36, for example, the vias 130d of the semiconductor die 130 are exposed through a plurality of openings O9 formed in the dielectric layer 352. In other words, the vias 130d of the semiconductor die 130 are exposed in an accessible manner through the openings O9 formed in the dielectric layer 352.

In some embodiments, seed layer 353-1 is formed directly on dielectric layer 352 and patterned conductive layer 354-1 is formed to be disposed on seed layer 353-1, according to step S42c shown in fig. 43. The formation and materials of the seed layer 353-1 and the patterned conductive layer 354-1 are the same as or similar to the formation and materials of the seed layer 153-1 and the patterned conductive layer 154-1, respectively, and thus are not described in detail herein. For example, as shown in fig. 36, seed layer 351-1 penetrates dielectric layer 352, wherein seed layer 351-1 extends into opening O9 to physically connect to via 130d of semiconductor die 130 exposed through opening O9. In some embodiments, the sidewalls of opening O9 are completely covered by seed layer 353-1. In some embodiments, patterned conductive layer 354-1 is located on seed layer 353-1 (e.g., physically contacting seed layer 353-1), wherein a projected area of patterned conductive layer 354-1 overlaps a projected area of seed layer 353-1 in a perpendicular projection along direction Z on insulating encapsulant 140'. For example, as shown in fig. 36, the patterned conductive layer 354-1 is electrically connected to the via 130d of the semiconductor die 130 through the seed layer 353-1.

With continued reference to fig. 36, in some embodiments, a dielectric layer 356a is disposed on the patterned conductive layer 354-1, in accordance with step S43c shown in fig. 43. For example, a dielectric layer 356a is coated on the seed layer 353-1, the patterned conductive layer 354-1, and the dielectric layer 352 exposed through the seed layer 353-1 and the patterned conductive layer 354-1. In other words, the seed layer 353-1 and the patterned conductive layer 354-1 are embedded in the dielectric layer 356a, wherein the dielectric layer 352 exposed through the seed layer 353-1 and the patterned conductive layer 354-1 is covered by the dielectric layer 356 a. For example, dielectric layer 356a is coated on seed layer 353-1, patterned conductive layer 354-1, and dielectric layer 352 exposed through seed layer 353-1 and patterned conductive layer 354-1 by, but not limited to: a blanket layer of dielectric material mixture is formed over seed layer 353-1, patterned conductive layer 354-1, and dielectric layer 352 exposed through seed layer 353-1 and patterned conductive layer 354-1 to completely cover seed layer 353-1, patterned conductive layer 354-1, and dielectric layer 352 exposed through seed layer 353-1 and patterned conductive layer 354-1. In some embodiments, the dielectric layer 356a may be formed by a suitable fabrication technique, such as spin coating.

In some embodiments, the dielectric material mixture includes a dielectric material and an additive. For example, the dielectric material may include polyimide, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, acrylate resin (acrylate resin), combinations thereof, and the like. For example, the additives may include small molecules (e.g., silane-based small molecules) having an average molecular weight of less than 1000 grams per mole (g/mol) or oligomers (e.g., polyethylene glycol-based oligomers, acrylate-based oligomers, etc.) having an average molecular weight of about 1000g/mol to about 10000 g/mol. In some embodiments, the amount of dielectric material is about 95 wt% to about 99 wt% and the amount of additive is about 1 wt% to about 5 wt% based on the total amount of the dielectric material mixture. In an alternative embodiment, a solvent may optionally be added to the dielectric material mixture to facilitate mixing between the additive and the dielectric material, the solvent being one that enables the additive and the dielectric material to be uniformly mixed therein but not reacted therewith. In some embodiments, the solvent may include n-methylpyrrolidinone (NMP) or a nitrogen-containing solvent.

Referring to fig. 37, in some embodiments, according to step S44c shown in fig. 43, a heat treatment TH is performed on the structure shown in fig. 36 to form an interlayer film 355-1 on the patterned conductive layer 354-1. For example, a thermal treatment TH is performed on the dielectric layer 356a to form a fully cured dielectric layer 356a 'and an interlayer film 355-1, wherein the interlayer film 355-1 is located between the fully cured dielectric layer 356 a' and the patterned conductive layer 354-1. In some embodiments, the thickness of the interlayer film 355-1 is greater than or substantially equal to 5nm and less than or substantially equal to 250 nm. As shown in fig. 37, for example, an interlayer film 355-1 is directly on the patterned conductive layer 354-1, wherein the dielectric layer 356 a' is separated from the patterned conductive layer 354-1 by the interlayer film 355-1.

In some embodiments, during the heat treatment TH, the dielectric layer 356a is sufficiently cured while the additives contained in the dielectric layer 356a interact with copper (Cu) atoms of the patterned conductive layer 254-1 to form the interlayer film 355-1, wherein additional oxygen (O) atoms (e.g., from the external atmosphere) are also provided during the heat treatment TH to further perform an oxidation process, thereby forming the interlayer film 355-1 with a nanostructure composed of copper oxide having a grain size (grain size) of 200nm or more than 200 nm. In some embodiments, interlayer film 355-1 comprises a film formed from polycrystalline copper oxide (polycrystalline Cu)₂O) a nanostructure layer. In the present disclosure, the interlayer film 355-1 is conductive, and the interlayer film 355-1 is electrically connected to the patterned conductive layer 354-1. During the performance of the thermal process TH, parameters in the formation of the interlayer film 355-1, such as the oxidation rate of copper atoms, the crystal orientation, and the layer density, can be controlled by adjusting the addition (type and/or amount) of additives included in the dielectric material mixture used to form the dielectric layer 356a, based on requirements and design layout. The curing temperature of the dielectric layer 356a is significantly reduced due to the additives contained in the dielectric material mixture. In one embodiment, the heat treatment TH is performed at an operable temperature of about 170 ℃ to about 320 ℃ and an operable pressure (workable pressure) of about 50 torr to about 100 torr. For example, the additional oxygen atoms may be provided by (but not limited to) providing pure oxygen gas.

In some embodiments, as shown in fig. 38, the dielectric layer 356 a' is patterned to form a dielectric layer 356-1 having a plurality of openings O10, wherein the opening O10 exposes portions of the interlayer film 355-1. The number of openings O10 is not limited to the number depicted in fig. 38 and may be specified based on requirements and design layout.

With continued reference to fig. 38, in some embodiments, patterned conductive layer 354-1 is completely surrounded by seed layer 353-1 and interlayer film 355-1. In some embodiments, an interlayer film 355-1 is located between patterned conductive layer 354-1 and dielectric layer 356-1 and between seed layer 353-1 and dielectric layer 356-1, wherein patterned conductive layer 354-1 and seed layer 353-1 are independently separated from dielectric layer 356-1 by interlayer film 355-1. Since the interlayer film 355-1 is interposed between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1, the interlayer film 355-1 having a grain size of 200nm or more serves as a copper diffusion barrier between the conductive layer and the dielectric layer (e.g., the patterned conductive layer 354-1 and the dielectric layer 356-1, and the seed layer 353-1 and the dielectric layer 356-1), and thus the copper diffusion phenomenon is greatly suppressed due to a reduction in the diffusion rate of copper atoms from the conductive layer (e.g., a copper layer) to the dielectric layer due to the interlayer film 355-1. In detail, the number of grain boundaries in a given area decreases as the grain size increases, so that the generation of voids between the conductive layer and the dielectric layer (which is caused by the diffusion of copper atoms diffused from the conductive layer to the dielectric layer and the grain boundaries of the grains in the conductive layer) is significantly reduced. Accordingly, the adhesive strength between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is enhanced due to the presence of the interlayer film 355-1, and delamination between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is suppressed. Due to the interlayer film 355-1, adhesive strength between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is enhanced, and delamination between the patterned conductive layer 354-1 and the dielectric layer 356-1 and between the seed layer 353-1 and the dielectric layer 356-1 is suppressed.

Referring to fig. 39, in some embodiments, a seed layer 353-2, a patterned conductive layer 354-2, an interlayer film 355-2 and a dielectric layer 356-2 are sequentially formed on a dielectric layer 356-1, and a seed layer 353-3, a patterned conductive layer 354-3, an interlayer film 355-3 and a dielectric layer 356-3 are sequentially formed on the dielectric layer 356-2. The formation and material of the seed layers 353-2 and 353-3 are the same as or similar to the formation and material of the seed layer 353-1, the formation and material of the patterned conductive layers 354-2 and 354-3 is the same as or similar to the formation and material of the patterned conductive layer 354-1, the formation and material of the interlayer films 355-2 and 355-3 is the same as or similar to the formation and material of the interlayer film 355-1, and the formation and material of the dielectric layers 356-2 and 356-3 is the same as or similar to the formation and material of the dielectric layer 356-1, and thus will not be described herein again.

In some embodiments, seed layer 353-2 is located on dielectric layer 356-1 and extends into opening O10 formed in dielectric layer 356-1 to physically contact the portion of interlayer film 355-1 exposed through opening O10. In other words, seed layer 353-2 penetrates dielectric layer 356-1 and the sidewalls of opening O10 are completely covered by seed layer 353-2. As shown in fig. 39, for example, seed layer 353-2 is electrically connected to patterned conductive layer 354-1 through interlayer film 355-1. In some embodiments, patterned conductive layer 354-2 is located on seed layer 353-2 (e.g., in physical contact with seed layer 353-2), wherein a projected area of patterned conductive layer 354-2 overlaps a projected area of seed layer 353-2 in a perpendicular projection along direction Z on insulating encapsulant 140'. For example, as shown in fig. 39, the patterned conductive layer 354-2 is electrically connected to the patterned conductive layer 354-1 through the seed layer 353-2 and the interlayer film 355-1. In some embodiments, interlayer film 355-2 is located on patterned conductive layer 354-2 (e.g., physically contacting patterned conductive layer 354-2), wherein the surface of patterned conductive layer 354-2 that is not in contact with seed layer 353-2 and the sidewalls of seed layer 353-2 are covered by interlayer film 355-2. As shown in fig. 39, for example, interlayer film 355-2 is electrically connected to patterned conductive layer 354-2 and seed layer 353-2. In some embodiments, dielectric layer 356-2 is located on interlayer film 355-2, wherein interlayer film 355-2 is sandwiched between patterned conductive layer 354-2 and dielectric layer 356-2, and between seed layer 353-2 and dielectric layer 356-2. Due to the interlayer film 355-2, adhesive strength between the patterned conductive layer 354-2 and the dielectric layer 356-2 and between the seed layer 353-2 and the dielectric layer 356-2 is enhanced, and delamination between the patterned conductive layer 354-2 and the dielectric layer 356-2 and between the seed layer 353-2 and the dielectric layer 356-2 is suppressed. In some embodiments, as shown in FIG. 39, portions of the interlayer film 355-2 are exposed through a plurality of openings O11 formed in the dielectric layer 356-2 to electrically connect to subsequently formed connectors.

In some embodiments, seed layer 353-3 is located on dielectric layer 356-2 and extends into opening O11 formed in dielectric layer 356-2 to physically contact the portion of interlayer film 355-2 exposed through opening O11. In other words, seed layer 353-3 penetrates dielectric layer 356-2, and the sidewalls of opening O11 are completely covered by seed layer 353-3. As shown in fig. 39, for example, seed layer 353-3 is electrically connected to patterned conductive layer 354-2 through interlayer film 355-2. In some embodiments, patterned conductive layer 354-3 is located on seed layer 353-3 (e.g., in physical contact with seed layer 353-3), wherein a projected area of patterned conductive layer 354-3 overlaps a projected area of seed layer 353-3 in a perpendicular projection along direction Z onto insulating encapsulant 140'. For example, as shown in fig. 39, the patterned conductive layer 354-3 is electrically connected to the patterned conductive layer 354-2 through the seed layer 353-3 and the interlayer film 355-2. In some embodiments, an interlayer film 355-3 is located on patterned conductive layer 354-3 (e.g., physically contacting patterned conductive layer 354-3), wherein the surface of patterned conductive layer 354-3 that is not in contact with seed layer 353-3 and the sidewalls of seed layer 353-3 are covered by interlayer film 355-3. As shown in fig. 39, for example, interlayer film 355-3 is electrically connected to patterned conductive layer 354-2 and seed layer 353-3. In some embodiments, dielectric layer 356-3 is located on interlayer film 355-3, wherein interlayer film 355-3 is sandwiched between patterned conductive layer 354-3 and dielectric layer 356-3, and between seed layer 353-3 and dielectric layer 356-3. Due to the interlayer film 355-3, adhesive strength between the patterned conductive layer 354-3 and the dielectric layer 356-3 and between the seed layer 353-3 and the dielectric layer 356-3 is enhanced, and delamination between the patterned conductive layer 354-3 and the dielectric layer 356-3 and between the seed layer 353-3 and the dielectric layer 356-3 is suppressed. In some embodiments, as shown in fig. 39, portions of the interlayer film 355-3 are exposed through a plurality of openings O12 formed in the dielectric layer 356-3 to electrically connect to subsequently formed connectors. At this time, the redistribution circuit structure 350 of the package structure P7 is completed. As shown in fig. 39, the semiconductor dies 130-1, 130-2, 130-3 are in electrical communication with each other, for example, through a redistribution routing structure 350.

In the present disclosure, the seed layer 353-2, the patterned conductive layer 354-2, the interlayer film 355-2, and the dielectric layer 356-2 formed in fig. 39, and the seed layer 353-3, the patterned conductive layer 354-3, the interlayer film 355-3, and the dielectric layer 356-3 formed in fig. 39 may be referred to as one layer of a fifth constituent layer (fine build-up layer) of the redistribution routing structure 350, respectively. The number of fifth constituent layers included in the redistribution routing structure 350 is not limited in this disclosure. In one embodiment, the number of fifth constituent layers included in the reroute route structure 350 may be zero. For example, both of the two fifth constituent layers formed in fig. 39 may be optionally omitted from the redistribution line structure 350. In alternative embodiments, the number of fifth constituent layers included in the reroute route structure 350 may be one or more than one.

Referring to fig. 40, in some embodiments, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are sequentially formed on the redistribution routing structure 350. The adhesive strength between the conductive element 170 and the dielectric layer 356-3 is enhanced due to the seed layer pattern 160. In some embodiments, the seed layer pattern 160 is directly on the portion of the interlayer film 355-3 exposed through the opening O12 formed in the dielectric layer 356-3, and the seed layer pattern 160 is electrically connected to the patterned conductive layer 354-3 through the interlayer film 355-3.

In some embodiments, the seed layer pattern 160 is electrically connected to the redistribution routing structure 350, and the conductive element 170 is electrically connected to the redistribution routing structure 350 through the seed layer pattern 160. As shown in fig. 40, for example, some of the conductive elements 170 are electrically connected to the semiconductor die 130 through the redistribution routing structure 350 and corresponding ones of the seed layer patterns 160. The formation and materials of the seed layer pattern 160 and the conductive element 170 have been described in the process of fig. 13 and thus will not be described in detail herein.

Referring to fig. 41, in some embodiments, the entire structure depicted in fig. 40 is flipped (upside down) with carrier 112, with conductive element 170 placed to holding device HD, and carrier 112 is then peeled from buffer layer 116 due to peeling layer 114. During the peeling step, the package structure P7 is fixed using the holding device HD before peeling the carrier 112 and the peeling layer 114.

Referring to fig. 42, in some embodiments, the conductive element 170 is released from the retention device HD to form a package structure P7. In some embodiments, a dicing (singulation) process is performed to dice the plurality of package structures P7 interconnected therebetween into individual and separate package structures P7 prior to releasing the conductive elements 170 from the retention device HD. At this point, the fabrication of the package structure P7 is completed.

In some embodiments, the conductive elements 170 may include copper pillars, copper vias, and the like, referring to the package structure P7 illustrated in fig. 42. However, the disclosure is not limited thereto, and in alternative embodiments, the conductive elements 170 may include solder balls or BGA balls, while the seed layer pattern 160 is replaced with a UBM pattern u1, as shown in the package structure P8 of fig. 44. In other alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, while the seed layer pattern 160 is replaced with the UBM pattern u1, and may further include a plurality of conductive pillars CP in the presence of the conductive element 190 and the UBM pattern u2, see the package structure P9 illustrated in fig. 45. However, the present disclosure is not so limited, and in alternative embodiments, the UBM pattern u2 may be omitted based on the design layout and requirements.

In still other alternative embodiments, additional semiconductor elements (not shown) may be disposed on the redistribution routing structure 350 via the seed layer pattern 160 and/or the UBM patterns u1, u2 in addition to the conductive element 170 of fig. 42 and/or the conductive element 180 of fig. 44-45. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in this disclosure and may be specified based on requirements and design layout.

Fig. 46 is a schematic cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. Fig. 47 is a flow diagram illustrating a method of fabricating a redistribution routing structure/layer of a package structure according to some embodiments of the present disclosure. Elements that are similar or substantially the same as previously described elements will be given the same reference numerals and some details or description of the same elements will not be repeated herein. Referring to fig. 15 and 46, a package structure P10 shown in fig. 46 is similar to the package structure P1 shown in fig. 15; the difference is that in package P10, the reroute route structure 150 is replaced by the reroute route structure 450.

In some embodiments, use is made ofThe steps (processes) described in fig. 47 form and place redistribution line structures 450 on semiconductor die 130 and insulating encapsulant 140'. In some embodiments, as shown in FIG. 46, the redistribution line structure 450 includes a dielectric layer 452 (e.g., dielectric layer 452-1, dielectric layer 452-2, dielectric layer 452-3, and dielectric layer 452-4), a seed layer 453 (e.g., seed layer 453-1, seed layer 453-2, seed layer 453-3, and seed layer 453-4), a patterned conductive layer 454 (e.g., patterned conductive layer 454-1, patterned conductive layer 454-2a, patterned conductive layer 454-2b, patterned conductive layer 454-3, and patterned conductive layer 454-4), and an interlayer film 455 (e.g., interlayer film 455-1, interlayer film 455-2, and interlayer film 455-3, and interlayer film 455-4). However, in the present disclosure, the number of layers of the dielectric layer 452, the seed layer 453, the patterned conductive layer 454 and the interlayer film 455 is not limited to the number of layers illustrated in fig. 46, wherein the number of layers of the dielectric layer 452, the seed layer 453, the patterned conductive layer 454 and the interlayer film 455 may be one or more than one. In some embodiments, a dielectric layer 452, a seed layer 453, a patterned conductive layer 454, and an interlayer film 455 are formed on the insulating encapsulant 140' and sequentially stacked. In the present disclosure, the interlayer films 455-1 to 455-4 are independently formed with nanostructures composed of copper oxide having a crystal grain size of 200nm or more than 200 nm. In some embodiments, interlayer films 455-1 through 455-4 comprise polycrystalline copper oxide (Cu)₂O) a nanostructure layer. In the present disclosure, the interlayer films 455-1 to 455-4 are conductive.

As shown in fig. 46, in some embodiments, the patterned conductive layer 454-1 is completely surrounded (covered) by the seed layer 453-1 and the interlayer film 455-1. For example, an interlayer film 455-1 is located between the patterned conductive layer 454-1 and the dielectric layer 456-1 and between the seed layer 453-1 and the dielectric layer 456-1, wherein the patterned conductive layer 454-1 and the seed layer 453-1 are independently and physically separated from the dielectric layer 456-1 by the interlayer film 455-1. Due to the interlayer film 455-1, the adhesive strength between the patterned conductive layer 454-1 and the dielectric layer 456-1 and between the seed layer 453-1 and the dielectric layer 456-1 is enhanced, and delamination between the patterned conductive layer 454-1 and the dielectric layer 456-1 and between the seed layer 453-1 and the dielectric layer 456-1 is suppressed. As shown in fig. 46, the conductive layer 454-1 is electrically connected to the via 130d through the seed layer 453-1 and is electrically connected to the interlayer film 455-1 through direct contact.

In some embodiments, the patterned conductive layer 454-2a and the patterned conductive layer 454-2b disposed thereon are completely surrounded (covered) by the seed layer 453-2 and the interlayer film 455-2. For example, an interlayer film 455-2 is located between the patterned conductive layers 454-2a, 454-2b and the dielectric layer 456-2 and between the seed layer 453-2 and the dielectric layer 456-2, wherein the patterned conductive layers 454-2a, 454-2b and the seed layer 453-2 are independently and physically separated from the dielectric layer 456-2 by the interlayer film 455-2. Due to the interlayer film 455-2, the adhesive strength between the patterned conductive layers 454-2a, 454-2b and the dielectric layer 456-2 and between the seed layer 453-2 and the dielectric layer 456-2 is enhanced, and delamination between the patterned conductive layers 454-2a, 454-2b and the dielectric layer 456-2 and between the seed layer 453-2 and the dielectric layer 456-2 is suppressed. As shown in fig. 46, the patterned conductive layer 454-2a is electrically connected to the patterned conductive layer 454-1 through the seed layer 453-2 and the interlayer film 455-1, and is electrically connected to the interlayer film 455-2 through direct contact, while the patterned conductive layer 454-2b is electrically connected to the patterned conductive layer 454-2a and the interlayer film 455-2 through direct contact.

In some embodiments, the patterned conductive layer 454-3 is completely surrounded (covered) by the seed layer 453-3 and the interlayer film 455-3. For example, an interlayer film 455-3 is located between the patterned conductive layer 454-3 and the dielectric layer 456-3 and between the seed layer 453-3 and the dielectric layer 456-3, wherein the patterned conductive layer 454-3 and the seed layer 453-3 are independently and physically separated from the dielectric layer 456-3 by the interlayer film 455-3. Due to the interlayer film 455-3, the adhesive strength between the patterned conductive layer 454-3 and the dielectric layer 456-3 and between the seed layer 453-3 and the dielectric layer 456-3 is enhanced, and delamination between the patterned conductive layer 454-3 and the dielectric layer 456-3 and between the seed layer 453-3 and the dielectric layer 456-3 is suppressed. As shown in fig. 46, the conductive layer 454-3 is electrically connected to the conductive layer 454-2a through the seed layer 453-3 and the interlayer film 455-2.

In some embodiments, the patterned conductive layer 454-4 is completely surrounded (covered) by the seed layer 453-4 and the interlayer film 455-4. For example, an interlayer film 455-4 is located between the patterned conductive layer 454-4 and the dielectric layer 456-4 and between the seed layer 453-4 and the dielectric layer 456-4, wherein the patterned conductive layer 454-4 and the seed layer 453-4 are independently and physically separated from the dielectric layer 456-4 by the interlayer film 455-4. Due to the interlayer film 455-4, the adhesive strength between the patterned conductive layer 454-4 and the dielectric layer 456-4 and between the seed layer 453-4 and the dielectric layer 456-4 is enhanced, and delamination between the patterned conductive layer 454-4 and the dielectric layer 456-4 and between the seed layer 453-4 and the dielectric layer 456-4 is suppressed. As shown in fig. 46, the conductive layer 454-4 is electrically connected to the conductive layer 454-3 through the seed layer 453-4 and the interlayer film 455-3.

For example, for illustrative purposes, the formation of the redistribution line structure 450 may be performed by the processing steps S41d through S46d shown in fig. 47 described below. The present disclosure is not so limited.

In some embodiments, after the process described in fig. 3, a seed layer (not shown) is formed on semiconductor die 130 and insulating encapsulant 140' according to step S41d shown in fig. 47. For example, the formation and material of the seed layer is similar to or substantially the same as the formation and material of seed layer SL1 illustrated in fig. 21, and therefore, will not be described in detail herein. In some embodiments, a patterned conductive layer 454-1 is formed on the seed layer, according to step S42d shown in fig. 47. For example, the formation and material of the patterned conductive layer 454-1 are similar or substantially the same as those of the patterned conductive layer 254-1 illustrated in fig. 22, and thus are not repeated herein. In certain embodiments, the seed layer is patterned to form seed layer 453-1 using patterned conductive layer 454-1 as an etch mask, according to step S43d shown in FIG. 47. For example, the formation and material of the seed layer 453-1 is similar or substantially the same as the formation and material of the seed layer 253-1 illustrated in FIG. 23, and thus will not be described in detail herein. In some embodiments, a dielectric layer (not shown) is disposed over the patterned conductive layer 454-1, according to step S44d shown in FIG. 47. For example, the formation and material of the dielectric layer are similar to or substantially the same as those of the dielectric layer 356a shown in fig. 36, and therefore, the description thereof is omitted here. In some embodiments, a thermal treatment is then performed to form an interlayer film 455-1 on the patterned conductive layer 454-1, according to step S45d shown in fig. 47. For example, the process of the heat treatment is similar or substantially the same as the process of the heat treatment described in fig. 37, and thus will not be described in detail herein. In some embodiments, a patterning step is performed on the dielectric layer to form the dielectric layer 452-1 and expose the interlayer film 455-1, according to step S46d shown in FIG. 47. For example, the process of the patterning step is similar to or substantially the same as the process of the planarization step described in fig. 26, and therefore, the description thereof is omitted here.

In addition, the formation and materials of the dielectric layers 452-2 to 452-4, the seed layers 453-2 to 453-4, the patterned conductive layers 454-2a, 454-2b, 454-3, 454-4, and the interlayer films 455-2 to 455-4 are similar to or substantially the same as the dielectric layers 452-1, the seed layers 453-1, the patterned conductive layers 454-1, and the interlayer films 455-1 described in fig. 47, or similar to or substantially the same as the seed layers 353-1, the patterned conductive layers 354-1, the interlayer films 355-1, and the dielectric layers 356-1 described in fig. 36 to 38, and thus, for the sake of brevity, no further description is provided herein. In the redistribution line structure 450 in the present disclosure, the layers (e.g., the seed layer 453-1, the patterned conductive layer 454-1, the interlayer film 455-1, and the dielectric layer 452-1) may be referred to as one layer of a sixth constituent layer (sixth structured-upper layer), the layers (e.g., the seed layer 453-2, the patterned conductive layers 454-2a, 454-2b, the interlayer film 455-2, and the dielectric layer 452-2) may be referred to as one layer of a seventh constituent layer (seven structured-upper layer), the layers (e.g., the seed layer 453-3, the patterned conductive layer 454-3, the interlayer film 455-3, and the dielectric layer 452-3) may be referred to as one layer of an eighth constituent layer (eightstructured-upper layer), and the layers (e.g., the seed layer 453-4, the patterned conductive layer 454-4, the interlayer film 455-4, and the dielectric layer 452-4) may be referred to as one layer of a fifth constituent layer. For illustrative purposes, four constituent layers (e.g., one layer each of the fifth, sixth, seventh, and eighth constituent layers) are included in the reroute route structure 450 shown in fig. 46; however, the present disclosure is not limited thereto. The number of fifth, sixth, seventh, and eighth constituent layers included in the redistribution routing structure 450 is not limited in this disclosure. For example, the number of fifth, sixth, and seventh constituent layers included in the reroute route structure 450 may be one or more than one, while the number of eighth constituent layers included in the reroute route structure 450 may be zero, one, or more than one.

With continued reference to fig. 46, a plurality of seed layer patterns 160 and a plurality of conductive elements 170 are sequentially formed over the redistribution layer 450, and the carrier 112 is then peeled off from the buffer layer 116 due to the peeling layer 114. The formation and materials of the seed layer pattern 160 and the conductive element 170 have been described in the process of fig. 13 and thus will not be described in detail herein. In some embodiments, the conductive element 170 is electrically connected to the redistribution routing structure 450 through the seed layer pattern 160. In some embodiments, some of the conductive elements 170 are electrically connected to the semiconductor die 130 through the redistribution routing structure 450 and corresponding ones of the seed layer patterns 160. During the peeling step, the package structure P10 is fixed using the holding device HD before peeling the carrier 112 and the peeling layer 114. In some embodiments, the conductive element 170 is released from the retention device HD to form the package structure P10. In some embodiments, a dicing (singulation) process is performed to dice the plurality of package structures P10 interconnected therebetween into individual and separate package structures P10 prior to releasing the conductive elements 170 from the retention device HD. At this point, the fabrication of the package structure P10 is completed.

In some embodiments, the conductive elements 170 may include copper pillars, copper vias, and the like, see the package structure P10 illustrated in fig. 46. However, the disclosure is not limited thereto, and in alternative embodiments, the conductive elements 170 may include solder balls or BGA balls, while the seed layer pattern 160 is replaced with a UBM pattern u1, as shown in the package structure P11 of fig. 48. In other alternative embodiments, the conductive element 170 may include a solder ball or a BGA ball, while the seed layer pattern 160 is replaced with the UBM pattern u1, and may further include a plurality of conductive pillars CP in the presence of the conductive element 190 and the UBM pattern u2, see the package structure P12 illustrated in fig. 49. However, the present disclosure is not so limited, and in alternative embodiments, the UBM pattern u2 may be omitted based on the design layout and requirements.

In still other alternative embodiments, additional semiconductor elements (not shown) may be disposed on the redistribution routing structure 450 via the seed layer pattern 160 and/or the UBM patterns u1, u2 in addition to the conductive elements 170 in fig. 46 and/or the conductive elements 180 in fig. 48-49. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in this disclosure and may be specified based on requirements and design layout.

As shown in package structures P7 through P12, in redistribution line structure 350/450, since an interlayer film (e.g., 355-1/355-2/355-3, 455-1/455-2/455-3/455-4) is located between a dielectric layer (e.g., 356-1/356-2/356-3, 452-1/452-2/452-3/452-4) and a patterned conductive layer (e.g., 354-1/354-2/354-3, 454-1/454-2a/454-2b/454-3/454-4), the dielectric layer (e.g., 356-1/356-2/356-3, 356-1/452-2/356-3), 452-1/452-2/452-3/452-4) are separated from the patterned conductive layer (e.g., 354-1/354-2/354-3, 454-1/454-2a/454-2b/454-3/454-4) by an interlayer film (e.g., 355-1/355-2/355-3, 455-1/455-2/455-3/455-4) and thus voids generated therebetween are greatly reduced, thereby suppressing the delamination phenomenon. In the present disclosure, each of the interlayer films 355-1/355-2/355-3, 455-1/455-2/455-3/455-4 has a thickness greater than or substantially equal to 5nm and less than or substantially equal to 250 nm. Due to this configuration, the adhesive strength between one of the patterned conductive layers and its corresponding one of the dielectric layers is enhanced, and thus better yield and reliability of the package structures P7 to P12 are achieved. In addition, the temperature at which the redistribution line structures 350, 450 are formed (e.g., the curing temperature of the dielectric layer) is reduced due to the formation of the interlayer film (e.g., addition of an additive).

In some embodiments, the package structures P1-P12 may further be mounted with additional packages, chips/dies, other electronic devices, or suitable substrates (e.g., organic substrates) to form stacked package structures, although the disclosure is not limited thereto.

According to some embodiments, a package structure includes a semiconductor die and a redistribution routing structure. The redistribution routing structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an interlayer film. The dielectric layer is arranged on the patterned conductive layer. The interlayer film is interposed between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer by the interlayer film.

According to some embodiments, the package structure further comprises: a seed layer, wherein the patterned conductive layer is disposed on the seed layer, and the patterned conductive layer is wrapped by the seed layer and the interlayer film. According to some embodiments, in the package structure, wherein a first surface of the interlayer film physically contacts the patterned conductive layer, a second surface of the interlayer film physically contacts the dielectric layer, and the first surface is opposite to the second surface. According to some embodiments, in the package structure, wherein the interlayer film includes an adhesive layer, and the adhesive layer is formed by contacting an adhesive precursor with the patterned conductive layer, and the adhesive precursor includes a compound represented by the following chemical formula:

wherein: ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulae (1) to (35):

and

R¹represents a hydrogen atom, an alkyl group or an aromatic ring, R²And R³Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y are each independently-H, -OH, -SH, -F, -Cl, -Br, -I, carboxyl, ester, amine, quaternary ammonium cation, trimethylsilyl, triethylsilyl, sulfo, carbonyl, carbonate, amide, or epoxy. According to some embodiments, in the package structure, a thickness of the interlayer film is greater than or substantially equal to 50nm and less than or substantially equal to 350 nm. According to some embodiments, in the package structure, the interlayer film comprises a nanostructure layer, and the nanostructure layer comprises polycrystalline Cu₂And O. According to some embodiments, in the package structure, a thickness of the nanostructure layer is greater than or substantially equal to 5nm and less than or substantially equal to 250 nm. According to some embodiments, the package structure further comprises: an insulating encapsulant encapsulating the semiconductor die, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die, and the redistribution line circuit structure is disposed on the surface of the insulating encapsulant that is substantially coplanar with the surface of the semiconductor die; and a plurality of conductive elements on and electrically connected to the redistribution routing structure, wherein the redistribution routing structure is located between the insulating encapsulation and the plurality of conductive elements. According to some embodiments, the package structure further comprises: a plurality of vias arranged alongside the semiconductor die and electrically connected to the redistribution routing structure, wherein the plurality of vias are electrically connected to the semiconductor die through the redistribution routing structure; an insulating encapsulant encapsulating the semiconductor die and the plurality of vias, wherein a surface of the insulating encapsulant is substantially coplanar with a surface of the semiconductor die and a surface of the plurality of vias, and the redistribution line circuit structure is disposed on the surface of the insulating encapsulant that is substantially coplanar with the surface of the semiconductor die and the surface of the plurality of vias; and a plurality of conductive elements on and electrically connected to the redistribution routing structure, wherein the redistribution routing structure is located between the insulating encapsulation and the plurality of conductive elements. According to some embodiments, the package structure further comprises: one or more semiconductor devices disposed on and electrically connected to the redistribution routing structure, wherein the one or more semiconductor devices are electrically communicated to the semiconductor die through the redistribution routing structure.

According to some embodiments, a method of manufacturing a package structure comprises the steps of: providing a semiconductor die having a plurality of conductive terminals; forming a redistribution routing structure on the semiconductor die, wherein the redistribution routing structure is electrically connected to the semiconductor die, and forming the redistribution routing structure comprises: depositing a first dielectric layer on the semiconductor die, the first dielectric layer exposing portions of the plurality of conductive terminals; forming a patterned conductive layer on the first dielectric layer and connecting the patterned conductive layer to the portions of the plurality of conductive terminals exposed through the first dielectric layer; forming a first interlayer film on the patterned conductive layer, wherein the first interlayer film conformally covers the patterned conductive layer; and depositing a second dielectric layer on the first interlayer film, wherein the patterned conductive layer is separated from the second dielectric layer by the first interlayer film; and forming a plurality of conductive elements on the redistribution routing structure to electrically connect the plurality of conductive elements to the redistribution routing structure.

According to some embodiments, in the method of encapsulating a structure, wherein forming the first interlayer film comprises: applying a binder precursor on the patterned conductive layer to form the first interlayer film on the patterned conductive layer, wherein a bond is formed between the binder precursor and the patterned conductive layer, and the binder precursor comprises a compound represented by the following chemical formula:

wherein: ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulae (1) to (35):

and

R¹represents a hydrogen atom, an alkyl group or an aromatic ring, R²And R³Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer from 1 to 30, and X and Y are each independently-H, -OH, -SH, -F, -Cl, -Br, -I, carboxyl, ester, amine, quaternary ammonium cation, trimethylsilyl, triethylsilyl, sulfo, carbonyl, carbonate, amide, or epoxy; removing portions of the binder precursor that are not bonded to the patterned conductive layer by cleaning; and drying the first interlayer film. According to some embodiments, the method of packaging a structure further comprises forming a second interlayer film on the plurality of conductive terminals, wherein forming the second interlayer film comprises: applying an adhesive precursor on the plurality of conductive terminals to form the second interlayer film on the patterned conductive layer, wherein the adhesive precursor forms a bond with the plurality of conductive terminals, and the adhesive precursor comprises a compound represented by the following formula:

wherein: ar represents an aromatic ring selected from the group consisting of aromatic rings represented by the following chemical formulae (1) to (35):

and

R¹represents a hydrogen atom, an alkyl group or an aromatic ring, R²And R³Each independently represents a substituted alkylene group or an unsubstituted alkylene group, wherein n1 and n2 are each independently an integer of 1 to 30, and X and Y are each independently-H, -OH, -SH, -F, -Cl, -Br, -I, carboxyl, ester, amine, quaternary ammonium cation, trimethylsilyl, triethylsilyl, sulfo, carbonyl, carbonate, amide, or epoxy; removing portions of the adhesive precursor not bonded to the plurality of conductive terminals by washing; and drying the second interlayer film. According to some embodiments, in the method for packaging a structure, before forming the redistribution routing structure, the method further includes: encapsulating the semiconductor die in an insulating encapsulant. According to some embodiments, in the method of packaging a structure, before encapsulating the semiconductor die, further comprising: forming a plurality of vias arranged alongside the semiconductor die, wherein the plurality of vias are electrically connected to the semiconductor die through the redistribution routing structure, wherein encapsulating the semiconductor die further comprises encapsulating the plurality of vias in the insulating encapsulant. According to some embodiments, in the method for packaging a structure, after forming the redistribution routing structure, the method further includes: one or more semiconductor devices are disposed on and electrically connected to the redistribution routing structure.

According to some embodiments, a method of manufacturing a package structure comprises the steps of: providing a semiconductor die; encapsulating the semiconductor die in an insulating encapsulant; forming a redistribution line structure on the insulating encapsulation, wherein the redistribution line structure is electrically connected to the semiconductor die, and the forming the redistribution line structure comprises: forming a patterned conductive layer on the semiconductor die, the patterned conductive layer electrically connecting the semiconductor die; depositing a dielectric layer on the patterned conductive layer, and forming a nanostructured conductive layer between the dielectric layer and the patterned conductive layer; and forming a plurality of conductive elements on the redistribution routing structure to electrically connect the redistribution routing structure with the plurality of conductive elements.

In the method of encapsulating a structure, according to some embodiments, wherein depositing a dielectric layer on the patterned conductive layer comprises mixing a dielectric material with an additive comprising a small molecule or oligomer to form a dielectric material mixture, and coating the dielectric material mixture on the patterned conductive layer to form the dielectric layer, and forming the nanostructured conductive layer between the dielectric layer and the patterned conductive layer comprises subjecting the dielectric layer and the patterned conductive layer to a thermal treatment, to form the nanostructured conductive layer composed of metal oxide between the dielectric layer and the patterned conductive layer, wherein in the thermal treatment, the additive contained in the dielectric layer interacts with the patterned conductive layer to form the nanostructured conductive layer composed of a metal oxide. According to some embodiments, in the method of packaging a structure, before encapsulating the semiconductor die, further comprising: forming a plurality of vias arranged alongside the semiconductor die, wherein the plurality of vias are electrically connected to the semiconductor die through the redistribution routing structure, wherein encapsulating the semiconductor die further comprises encapsulating the plurality of vias in the insulating encapsulant. According to some embodiments, in the method for packaging a structure, after forming the redistribution routing structure, the method further includes: one or more semiconductor devices are disposed on and electrically connected to the redistribution routing structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.