阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 李源俊 申多慧 李一炯 于 2019-06-14 设计创作，主要内容包括：提供了一种半导体器件,其包括位于衬底上的导电结构、位于所述导电结构上的蚀刻停止层、位于所述蚀刻停止层上的绝缘层以及延伸穿过所述蚀刻停止层和所述绝缘层并接触所述导电结构的接触插塞。所述接触插塞可以包括顺序堆叠并彼此接触的第一导电图案结构和第二导电图案结构。所述第一导电图案结构的上表面的宽度可以大于所述第二导电图案结构的下表面的宽度。所述第一导电图案结构的至少上部可以具有不垂直于所述衬底的上表面而是相对于所述衬底的所述上表面倾斜的侧壁。(A semiconductor device is provided that includes a conductive structure on a substrate, an etch stop layer on the conductive structure, an insulating layer on the etch stop layer, and a contact plug extending through the etch stop layer and the insulating layer and contacting the conductive structure. The contact plug may include a first conductive pattern structure and a second conductive pattern structure that are sequentially stacked and contact each other. The width of the upper surface of the first conductive pattern structure may be greater than the width of the lower surface of the second conductive pattern structure. At least an upper portion of the first conductive pattern structure may have a sidewall that is not perpendicular to an upper surface of the substrate but inclined with respect to the upper surface of the substrate.)

1. A semiconductor device, the semiconductor device comprising:

a conductive structure on a substrate;

an etch stop layer on the conductive structure;

an insulating layer on the etch stop layer; and

a contact plug extending through the etch stop layer and the insulating layer and contacting the conductive structure,

wherein the contact plug includes a first conductive pattern structure and a second conductive pattern structure sequentially stacked and contacting each other, a width of an upper surface of the first conductive pattern structure is greater than a width of a lower surface of the second conductive pattern structure, and at least an upper portion of the first conductive pattern structure has a sidewall that is not perpendicular to an upper surface of the substrate but is inclined with respect to the upper surface of the substrate.

2. The semiconductor device of claim 1, wherein the width of the upper surface of the first conductive pattern structure is greater than a width of a lower surface of the first conductive pattern structure.

3. The semiconductor device of claim 1, wherein a lower portion of the first conductive pattern structure comprises sidewalls substantially perpendicular to the upper surface of the substrate.

4. The semiconductor device of claim 1, wherein the lower portion of the first conductive pattern structure comprises a sidewall having a slope substantially the same as a slope of the upper portion of the first conductive pattern structure.

5. The semiconductor device of claim 1, wherein sidewalls of the upper portion of the first conductive pattern structure have a first slope relative to the upper surface of the substrate, and

wherein sidewalls of a lower portion of the first conductive pattern structure have a second slope relative to the upper surface of the substrate that is greater than the first slope.

6. The semiconductor device of claim 1, wherein the second conductive pattern structure has sidewalls substantially perpendicular to the upper surface of the substrate.

7. The semiconductor device of claim 1, wherein the sidewall of the upper portion of the first conductive pattern structure has a first slope relative to the upper surface of the substrate, and

wherein sidewalls of the second conductive pattern structure have a second slope relative to the upper surface of the substrate that is greater than the first slope.

8. The semiconductor device of claim 1, wherein a width of the lower portion of the first conductive pattern structure is substantially the same as a width of the second conductive pattern structure.

9. The semiconductor device of claim 1, wherein the etch stop layer comprises silicon nitride or silicon carbonitride.

10. The semiconductor device of claim 1, wherein the insulating layer comprises silicon oxide.

11. The semiconductor device according to claim 1, wherein the first conductive pattern structure comprises a first conductive pattern and a first barrier pattern covering a lower surface and sidewalls of the first conductive pattern, and the second conductive pattern structure comprises a second conductive pattern and a second barrier pattern covering sidewalls of the second conductive pattern.

12. A semiconductor device, the semiconductor device comprising:

a conductive structure on a substrate;

an etch stop layer on the conductive structure;

an insulating layer on the etch stop layer; and

a contact plug extending through the etch stop layer and the insulating layer in a vertical direction substantially perpendicular to an upper surface of the substrate and contacting the conductive structure,

wherein the contact plug includes a protruding portion protruding in a horizontal direction substantially parallel to the upper surface of the substrate in the vertical direction at least at a center portion of the contact plug.

13. The semiconductor device according to claim 12, wherein the protruding portion is formed not only at the central portion but also at a lower portion of the contact plug.

14. The semiconductor device of claim 12, wherein a lower portion of the contact plug comprises a sidewall having a constant slope with respect to the upper surface of the substrate.

15. The semiconductor device of claim 12, wherein an upper portion of the contact plug comprises a sidewall having a constant slope with respect to the upper surface of the substrate.

16. The semiconductor device of claim 12, wherein sidewalls of upper and lower portions of the contact plug are each substantially perpendicular to the upper surface of the substrate.

17. A semiconductor device, the semiconductor device comprising:

an insulating interlayer located on the substrate and containing a conductive structure therein;

an etch stop layer on the conductive structure and the insulating interlayer;

an insulating layer on the etch stop layer;

a contact plug extending through the etch stop layer and the insulating layer and contacting the conductive structure;

a lower electrode on the contact plug;

a magnetic tunnel junction structure located on the lower electrode; and

an upper electrode on the magnetic tunnel junction structure,

wherein the contact plug includes a first conductive pattern structure and a second conductive pattern structure, a width of an upper surface of the first conductive pattern structure is greater than a width of a lower surface of the second conductive pattern structure, and at least an upper portion of the first conductive pattern structure has a sidewall that is not perpendicular to an upper surface of the substrate but is inclined with respect to the upper surface of the substrate.

18. The semiconductor device of claim 17, wherein the width of the upper surface of the first conductive pattern structure is greater than a width of a lower surface of the first conductive pattern structure.

19. The semiconductor device of claim 17, wherein the sidewall of the upper portion of the first conductive pattern structure has a first slope relative to the upper surface of the substrate, and

wherein sidewalls of a lower portion of the first conductive pattern structure have a second slope relative to the upper surface of the substrate that is greater than the first slope.

20. The semiconductor device of claim 17, wherein the etch stop layer comprises silicon nitride or silicon carbonitride and the insulating layer comprises silicon oxide.

Technical Field

Background

In manufacturing a semiconductor device, it is necessary to form a contact plug in contact with a conductive structure.

Disclosure of Invention

Drawings

Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the attached drawings, wherein:

fig. 1 to 7 show cross-sectional views of stages of a method of manufacturing a semiconductor device according to an example embodiment.

Fig. 8 to 11 show cross-sectional views of a semiconductor device according to example embodiments.

Fig. 12 to 23 show cross-sectional views of stages of a method of manufacturing a semiconductor device according to an example embodiment.

Embodiments relate to a semiconductor device.