阅读说明：本技术 半导体封装件 (Semiconductor package ) 是由 金永培 于 2019-03-29 设计创作，主要内容包括：一种半导体封装件包括：封装件衬底；耦接至封装件衬底的倒装芯片；插入件,其堆叠在倒装芯片上,并且包括其上表面上的第一端子和第二端子；接合线,其将第一端子与封装件衬底连接；以及模制层,其覆盖插入件、倒装芯片和接合线。模制层在插入件的上表面上具有暴露第二端子的信号孔和与信号孔间隔开的至少一个伪孔。(A semiconductor package includes: a package substrate; a flip chip coupled to the package substrate; an interposer stacked on the flip chip and including first and second terminals on an upper surface thereof; a bonding wire connecting the first terminal with the package substrate; and a molding layer covering the interposer, the flip chip, and the bonding wires. The molding layer has a signal hole exposing the second terminal and at least one dummy hole spaced apart from the signal hole on an upper surface of the insert.)

1. A semiconductor package, comprising:

a package substrate;

a flip chip coupled to the package substrate;

an interposer stacked on the flip-chip and including an interposer substrate and first and second terminals on an upper surface of the interposer substrate;

a bonding wire connecting the first terminal with the package substrate; and

a molding layer covering the interposer, the flip chip, and the bonding wires,

wherein the mold layer has a signal hole therein that opens to and at the second terminal, and at least one dummy hole therein that is spaced apart from the signal hole and is located above the upper surface of the interposer substrate.

2. The semiconductor package of claim 1, wherein a portion of the molding layer extends above the upper surface of the interposer substrate, and

each of the at least one dummy hole extends completely through the portion of the molded layer.

3. The semiconductor package of claim 2, further comprising:

a protective film on the upper surface of the interposer substrate and exposed through each of the at least one dummy hole.

4. The semiconductor package of claim 3, wherein the first and second terminals are disposed on a first region of the upper surface of the interposer substrate, and

the protective film is disposed on a second region of the upper surface of the interposer substrate other than the first region.

5. The semiconductor package of claim 1, wherein the respective shapes of the signal hole and each of the at least one dummy hole are the same.

6. The semiconductor package of claim 1, wherein the at least one dummy hole comprises a plurality of dummy holes, each of the plurality of dummy holes being located above the upper surface of the interposer substrate, and

the respective sizes of the signal hole and each of the plurality of dummy holes are the same when viewed in a plan view.

7. The semiconductor package of claim 1, wherein the respective depths of the signal hole and each of the at least one dummy hole are the same.

8. The semiconductor package of claim 1, wherein the signal via is located over a first region of the upper surface of the interposer substrate,

the at least one dummy hole is located over a second region of the upper surface of the interposer substrate, and

the first region is located more towards a periphery of the upper surface of the interposer substrate than the second region.

9. The semiconductor package of claim 1, further comprising:

micro bumps electrically connecting the package substrate with the flip chip.

10. A semiconductor package, comprising:

a lower package; and

an upper package stacked on the lower package,

wherein the lower package comprises:

a package substrate;

a flip chip coupled to the package substrate;

an interposer stacked on the flip chip and including an interposer substrate and first and second terminals on an upper surface of the interposer substrate, an

A molding layer covering the interposer and the flip chip,

the mold layer has a signal hole therein that opens to and at the second terminal, and at least one dummy hole therein that is spaced apart from the signal hole and is located above the upper surface of the interposer substrate.

11. The semiconductor package according to claim 10, wherein the lower package further comprises solder balls located in the signal holes and disposed in contact with the second terminals,

wherein the upper package is in contact with the solder balls.

12. The semiconductor package of claim 10, wherein the upper package comprises a first memory chip and a second memory chip stacked on the first memory chip.

13. The semiconductor package according to claim 10, wherein the lower package further comprises a bonding wire connecting the package substrate with the first terminal.

14. The semiconductor package of claim 10, wherein the at least one dummy hole comprises a plurality of dummy holes, and

the arrangement of the plurality of dummy holes is non-uniform.

15. The semiconductor package of claim 10, wherein an air gap exists between the upper package and the lower package.

16. A semiconductor package, comprising:

a package substrate;

a plurality of micro-bumps disposed on the package substrate;

a flip chip stacked on the plurality of micro-bumps and electrically connected to the package substrate via the plurality of micro-bumps;

an underfill film surrounding the plurality of micro-bumps between the flip-chip and the package substrate;

an adhesive film on the flip chip;

an interposer stacked on the adhesive film and including an interposer substrate and first and second terminals on an upper surface of the interposer substrate;

a bonding wire electrically connecting the first terminal with the package substrate; and

a molding layer covering the interposer, the flip chip, and the bonding wires,

wherein the mold layer has a signal hole therein that opens to and at the second terminal, and at least one dummy hole therein that is spaced apart from the signal hole and is located above the upper surface of the interposer substrate.

17. The semiconductor package of claim 16, wherein a dimension of the interposer in a horizontal direction parallel to the upper surface of the interposer substrate is greater than a dimension of the flip chip in the horizontal direction.

18. The semiconductor package of claim 16, further comprising:

a solder ball disposed within the signal hole.

19. The semiconductor package of claim 18, further comprising:

a memory package stacked on the solder balls.

20. The semiconductor package of claim 16, wherein the at least one dummy hole comprises a plurality of dummy holes located above the upper surface of the interposer substrate.

Technical Field

The present inventive concept relates to a semiconductor package.

Background

The semiconductor industry is constantly trying to miniaturize and reduce the thickness and weight of semiconductor products while maintaining high integration of the products. For this reason, various types of packages having a component stack mounted on a substrate have been developed, and their applications and uses are also gradually increasing.

However, the stacked components of the package include various materials having different coefficients of thermal expansion. Therefore, during the manufacturing process (e.g., when forming a molding layer encapsulating the components on the substrate), warpage in which the package is distorted in a specific direction may occur. Such warpage may greatly reduce the reliability of the package. Therefore, it is necessary to take countermeasures to prevent the warpage.

Disclosure of Invention

According to an aspect of the inventive concept, there is provided a semiconductor package including: a package substrate; a flip chip coupled to the package substrate; an interposer stacked on the flip chip and including a substrate and first and second terminals on an upper surface of the substrate of the interposer; a bonding wire connecting the first terminal with the package substrate; and a molding layer covering the interposer, the flip chip, and the bonding wires. The molding layer has a signal hole therein that opens to the second terminal, and at least one dummy hole therein that is spaced apart from the signal hole and is located above the upper surface of the interposer.

According to another aspect of the inventive concept, there is provided a semiconductor package including a lower package and an upper package stacked on the lower package, and wherein the lower package includes: a package substrate; a flip chip coupled to the package substrate; an interposer stacked on the flip chip and including a substrate and first and second terminals on an upper surface of the substrate of the interposer; and a molding layer covering the interposer and the flip chip. The molding layer has a signal hole therein that is open at the second terminal, and has at least one dummy hole therein that is spaced apart from the signal hole and is located above the upper surface of the interposer.

According to another aspect of the inventive concept, there is provided a semiconductor package including: a package substrate; a plurality of micro-bumps disposed on the package substrate; a flip chip stacked on the plurality of micro-bumps and electrically connected to a package substrate via the plurality of micro-bumps; an underfill film surrounding the plurality of micro-bumps between the flip-chip and the package substrate; an adhesive film on the flip chip; an interposer stacked on the adhesive film and including a substrate and a first terminal and a second terminal at an upper surface of the substrate of the interposer; a bonding wire electrically connecting the first terminal and the package substrate; and a molding layer covering the interposer, the flip chip, and the bonding wires. The molding layer has a signal hole therein that is open at the second terminal, and has at least one dummy hole therein that is spaced apart from the signal hole and is located above the upper surface of the interposer.

Drawings

The above and other aspects and features of the present inventive concept will become more apparent by describing in detail various examples thereof with reference to the attached drawings, in which:

fig. 1 is a cross-sectional view of an example of a semiconductor package according to the inventive concept;

fig. 2 is a conceptual diagram illustrating warpage of the semiconductor package of fig. 1;

FIG. 3 is an enlarged view of portion A of the package of FIG. 1;

fig. 4 is a plan view of the semiconductor package of fig. 1;

fig. 5 is a cross-sectional view of another example of a semiconductor package according to the inventive concept;

fig. 6 is a plan view of the semiconductor package of fig. 5;

fig. 7 is a cross-sectional view of another example of a semiconductor package according to the inventive concept;

fig. 8 is a plan view of an example of a semiconductor package according to the inventive concept;

fig. 9 is a plan view of another example of a semiconductor package according to the inventive concept;

fig. 10 is a plan view of another example of a semiconductor package according to the inventive concept;

fig. 11 is a plan view of another example of a semiconductor package according to the inventive concept;

fig. 12 is a plan view of another example of a semiconductor package according to the inventive concept;

fig. 13 is a plan view of still another example of a semiconductor package according to the inventive concept;

fig. 14 is a cross-sectional view of another example of a semiconductor package according to the inventive concept;

fig. 15 is a cross-sectional view of another example of a semiconductor package according to the inventive concept; and

fig. 16 is a cross-sectional view of still another example of a semiconductor package according to the inventive concept.

Detailed Description

One example of a semiconductor package according to the inventive concept will now be described with reference to fig. 1 to 4.

In the figure, the direction X is a first horizontal direction, and the direction Y is a second horizontal direction intersecting the first direction X. The first direction X and the second direction Y may be perpendicular to each other. The third direction Z has a vertical component and intersects both the first direction X and the second direction Y. For example, the third direction Z may be a vertical direction, i.e., may be perpendicular to the first direction X and the second direction Y. In this case, the first direction X, the second direction Y, and the third direction Z may all be orthogonal to each other.

Further, in the following description, although the drawings show a plurality of the same elements, these elements may sometimes be individually referred to for convenience of description. It will be understood that each description of a feature or aspect of a single element generally applies to the other identical elements. Also, like elements are represented by like reference numerals throughout the several views. Therefore, for the sake of brevity, the description of elements that have been described in one example may be omitted in the examples described later.

Referring to fig. 1, the semiconductor package includes a package substrate 100, a flip chip 200, a micro bump 210, a first underfill film 220, an interposer 300, an adhesive film 310, a bonding wire 340, and a molding layer 400.

The package substrate 100 may receive the flip chip 200 and the interposer 300 on its upper surface. Specifically, the flip chip 200 and the interposer 300 may be stacked on the upper surface of the package substrate 100 in order. The package substrate 100 may be, for example, a Printed Circuit Board (PCB) or may include a ceramic substrate integrated with conductive elements. However, the inventive concept is not limited thereto. In any case, the term "package substrate" as generally understood by those of ordinary skill in the art refers to a substrate (non-conductive plate-like body) integrated with conductive elements (e.g., terminals at the top and/or bottom surfaces of the substrate and internal wires (vias, internal redistribution wiring layers) extending through/in the substrate to provide an electrical path from the top surface to the bottom surface of the substrate).

In an example where the package substrate 100 is a PCB, the substrate may be made of at least one layer of material selected from phenol resin, epoxy resin, and polyimide. For example, the substrate may comprise at least one layer of material selected from FR4, tetrafunctional epoxy, polyphenylene oxide, epoxy/polyphenylene oxide, BT (bismaleimide triazine), polyamide staple fiber matting (thermo), cyanate ester, polyimide, and liquid crystal polymer. The upper surface of the substrate may be covered with a solder resist.

For conductive elements, the package substrate 100 may include wire bond terminals 110 and micro bump terminals 130. The wire bonding terminals 110 and the micro bump terminals 130 may be arranged at an upper surface of the package substrate 100. The wire bond terminal 110 and the micro bump terminal 130 may be exposed without being covered by the solder resist.

Further, although not shown, the package substrate 100 may include lower terminals on a lower surface of the substrate thereof. The lower terminal may be a portion on which the first solder ball 120 abuts.

The lower terminals, the wire bond terminals 110, and the micro-bump terminals 130 may be formed of at least one material selected from the group consisting of copper, nickel, stainless steel, and beryllium copper. After the Cu foil is applied to the upper and lower surfaces of the body of the substrate of the package substrate 100, the lower terminals, the wire bonding terminals 110, and the micro bump terminals 130 may be exposed through the solder resist of the patterned circuit wiring.

For conductive elements, the package substrate 100 may also include internal wiring (i.e., conductive elements extending within the body of the package substrate 100) electrically connected to the wire bond terminals 110, the micro bump terminals 130, and the lower terminals. The internal wiring may electrically connect corresponding ones of the wire-bond terminal 110, the micro-bump terminal 130, and the lower terminal, respectively, along separate paths.

The wire bonding terminal 110 may be electrically connected to the interposer 300 through a bonding wire 340. The wire bonding terminals 110 may be disposed on the outer side of the upper surface of the package substrate 100, as compared to the micro bump terminals 130. This is because the micro bump terminals 130 are connected to the flip chip 200, and the wire bonding terminals 110 are connected to the interposer 300 via the bonding wires 340.

The first solder balls 120 may be disposed on the lower surface of the package substrate 100. The first solder balls 120 may be in contact with the lower terminals. The first solder balls 120 may protrude in a downward direction (i.e., the third direction Z). The first solder balls 120 may be used to electrically connect the package substrate 100 to external electronic components/devices.

The micro bump terminals 130 may be located on the inner side of the package substrate 100 as compared to the wire bond terminals 110. A plurality of micro bump terminals 130 may be provided and the plurality of micro bump terminals 130 may be arranged at regular intervals, but the inventive concept is not limited thereto.

The upper surface of the micro bump terminal 130 may contact the micro bump 210. The micro bump terminal 130 may be a portion where the package substrate 100 and the flip chip 200 are electrically connected to each other. The micro-bump terminals 130 are disposed adjacent to each other and may be disposed relatively far from the wire-bonding terminals 110.

The flip chip 200 may be a logic semiconductor chip as a microprocessor. For example, the flip chip 200 may be a Central Processing Unit (CPU), a controller, an Application Specific Integrated Circuit (ASIC), or the like.

The micro bumps 210 may be disposed under the flip chip 200. The micro bumps 210 may electrically and physically connect the flip chip 200 with the package substrate 100, and may fix the flip chip 200 to the upper surface of the package substrate 100. Each micro bump 210 may be coupled with a micro bump terminal 130.

For example, the micro bumps 210 may be micro solder balls or solder paste. The micro bumps 210 may be electrically connected to circuitry of the flip chip 200, i.e., may be electrically connected to an Integrated Circuit (IC) inside the body of the flip chip 200.

The first underfill film 220 may surround side surfaces of the micro bumps 210. The first underfill film 220 may fill a space between the flip chip 200 and the package substrate 100. The bonding strength between the flip chip 200 and the package substrate 100 may be enhanced by the first underfill film 220. In addition, the first underfill film 220 may counteract the tendency of other constituent elements, such as the flip chip 200, the package substrate 100, and the micro bumps 210, to be deformed by external environmental conditions, so that the package maintains good physical strength. For example, the first underfill film 220 may occupy a space that would otherwise be penetrated by impurities and moisture, and may prevent electromigration between vertically adjacent metal layers.

The first underfill film 220 may include an underfill resin such as an epoxy, a silica filler, or a flux.

Although not shown, the first underfill film 220 may have an air gap therein. The air gap may be a void formed when the first underfill film 220 is formed.

The interposer 300 may be stacked on the flip chip 200. The interposer 300 may be longer than the flip chip 200 in the first direction X. The interposer 300 may be centered on the flip chip 200. As a result, the lower surface of the periphery of the interposer 300 may extend laterally (horizontally outward) with respect to the flip chip 200 and be evenly spaced apart from the package substrate 100.

The insert 300 may comprise at least one of a silicon, glass, ceramic, or plastic substrate. However, the inventive concept is not limited thereto. For simplicity, the interposer 300 is described below as having a silicon substrate.

The interposer 300 may include a first terminal 320 and a second terminal 330 on an upper surface of its substrate. The first terminal 320 and the second terminal 330 may be connected to internal wiring of the interposer 300 (wiring that is internal and forms a conductive path through the substrate of the interposer 300).

The first terminal 320 may be electrically connected to the wire bonding terminal 110 of the package substrate 100 through a bonding wire 340. The first terminal 320 may electrically connect the package substrate 100 with the interposer 300.

The second terminal 330 may be a portion of another package stacked on the interposer 300 that is electrically connected to the package of the inventive concept. The second terminal 330 may be a conductive pad on which a solder ball is disposed and electrically connected to another package.

An adhesive film 310 may be disposed on the lower surface of the insert 300. Specifically, the adhesive film 310 may be disposed between the lower surface of the interposer 300 and the upper surface of the flip chip 200. The adhesive film 310 may fix the interposer 300 and the flip chip 200 to each other. The interposer 300 may be fixed to the upper portion of the flip chip 200 using the adhesive film 310.

The dimension of the interposer 300 in the first direction X and the second direction Y may be larger than the dimension of the flip chip 200 in the first direction X and the second direction Y. That is, the surface area or footprint of the interposer 300 may be greater than the surface area or footprint of the flip chip 200. As a result, a portion of the lower surface of the interposer 300 does not cover the upper surface of the flip chip 200. Similarly, because the adhesive film 310 is formed along the lower surface of the interposer 300, a portion of the adhesive film 310 is in contact with the upper surface of the flip chip 200, and another portion of the adhesive film 310 is not in contact with the upper surface of the flip chip 200.

The bonding wires 340 may connect the wire-bond terminals 110 of the package substrate 100 with the first terminals 320 of the interposer 300. The bond wire 340 is conductive. The bonding wire 340 may be formed of at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), cobalt (Co), chromium (Cr), and titanium (Ti), and may be disposed in a package by a wire bonding apparatus. Thus, the bonding wire 340 is a signal transmission medium that electrically connects the wire bonding terminal 110 and the first terminal 320.

The molding layer 400 may cover the upper surface of the package substrate 100, the side surface of the first underfill film 220, the side surface of the flip chip 200, the upper surface and the side surface of the interposer 300, the lower surface and the side surface of the adhesive film 310, and the bonding wires 340.

For example, the molding layer 400 may be formed of a silicon-based material, a thermosetting material, a thermoplastic material, a UV-treated material, or the like. In addition, the molding layer 400 may be formed of a polymer such as a resin, and may be formed of, for example, EMC (epoxy molding compound).

The molding layer 400 includes a signal hole 410 and a dummy hole 420 in an upper surface thereof. For the present specification only, that is, considering the order of the respective examples of the semiconductor package according to the inventive concept described herein, the dummy hole 420 will be referred to as a first dummy hole 420. The signal hole 410 is formed in a portion of the molding layer 400 located above the upper surface of the insert 300. The signal hole 410 leads from the upper surface of the molding layer 400 to the second terminal 330 located on the upper surface of the interposer 300 and is opened therein. Accordingly, the signal hole 410 may expose the second terminal 330 to the outside. A plurality of signal holes 410 may be provided, and each of the plurality of signal holes 410 may have the same size and shape and open to and open at a corresponding one of the second terminals 330. However, the inventive concept is not limited to signal holes of the same size and shape. The signal holes 410 may receive solder balls adjacent to the second terminals 330, which will be described later in connection with another example of the inventive concept.

The first dummy hole 420 may also be formed in a portion of the molding layer 400 located above the upper surface of the insert 300. Unlike the signal hole 410, the first dummy hole 420 does not expose any terminal. Furthermore, the "dummy holes" may be filled or completely occupied by a non-conductive dielectric, and in this case, may be empty or filled with an insulating material. Thus, since the term "dummy" will be understood by those of ordinary skill in the art in this context, the first dummy hole 420 does not define any path involving signal transmission, i.e., is not occupied by any conductors that make up the operative circuitry in the package.

The first dummy hole 420 may be a recess in the upper surface of the molding layer. In this example, the first dummy hole 420 does not extend completely through the portion of the molding layer 400 located above the insert 300. Accordingly, the upper surface of the insert 300 can be prevented from being damaged. In addition, a plurality of first dummy holes 420 may be provided. The plurality of first dummy holes 420 may be surrounded by the signal holes 410.

The first dummy hole 420 may prevent or reduce warpage of the package. A semiconductor package according to an example of the inventive concept will typically include elements of multiple materials having different Coefficients of Thermal Expansion (CTE). As a result, the thermal expansion volumes of each element due to temperature changes may differ from each other.

For example, the thermal expansion coefficients of the molding layer 400 and the package substrate 100 may be different from each other, and thus the thermal expansion volumes thereof may be different from each other. For example, considering the first direction X, the molding layer 400 may undergo a first thermal expansion E1, and the package substrate 100 may undergo a second thermal expansion E2. In this case, a dimensional change of the molding layer 400 in the first direction X as a result of the first thermal expansion E1 may be much larger than a dimensional change of the package substrate 100 in the direction X as a result of the second thermal expansion E2. As a result, the semiconductor package may be distorted, which is referred to as warpage.

Fig. 2 shows an example of a semiconductor package having a warp W generated due to a difference between the first thermal expansion E1 and the second thermal expansion E2 described above with reference to fig. 1. In this example, the center portion of the package is bent upward in the direction (a), and the outer portion is bent downward in the direction (b). In this example, the semiconductor package exhibits a warp in an arc shape. Of course, the warpage W exemplarily considers only the molding layer 400 and the package substrate 100. Since the semiconductor package includes many other materials in addition to the materials of the molding layer 400 and the substrate of the package, various and very complicated forms of warpage may occur.

However, the semiconductor package having the first dummy hole 420 according to the inventive concept may prevent or minimize the occurrence of such warpage. The first dummy hole 420 formed in the upper portion of the molding layer 400 serves to relax the molding layer 400 along a tendency of the molding layer 400 to undergo thermal expansion. Specifically, the molding layer 400 does not undergo thermal expansion in the region of the first dummy hole 420, and thus, a difference in the degree of thermal expansion between the molding layer 400 and elements of other materials may be minimized.

As a result, semiconductor packages according to the inventive concept will exhibit a relatively low amount of warpage and a corresponding increase in durability and reliability.

Referring to fig. 3, the signal hole 410 and the first dummy hole 420 may have substantially the same size. Specifically, the signal hole 410 may have a first width W1 in the first direction X. The first dummy hole 420 may have a second width W2 in the first direction X. The first width W1 may be the same as the second width W2. Here, the term "substantially the same" is used to describe a slight difference caused by inherent accuracy characteristics of the manufacturing process.

Additionally, the signal hole 410 may have a first depth d 1. The first dummy hole 420 may have a second depth d 2. The first depth d1 and the second depth d2 may be substantially the same. In other words, the signal hole 410 and the first dummy hole 420 may have substantially the same depth.

Due to the second terminal 330 formed on the upper surface of the interposer 300, the signal hole 410 may penetrate a portion of the molding layer 400 to expose the upper surface of the second terminal 330. On the other hand, the first dummy holes 420 having the same depth as the signal holes 410 will not penetrate the portion of the molding layer 400 above the insert 300 because the first dummy holes 420 and the upper surface of the insert 300 are spaced apart from each other by the thickness of the second terminal 330. Accordingly, the upper surface of the insert 300 may not be exposed by the first dummy hole 420.

Referring to fig. 4, the horizontal region of the molding layer 400 may include a first region R1 and a second region R2. The first region R1 may be a region surrounding the second region R2.

Specifically, the first region R1 may be an outer region in which the second terminals 330 of the interposer 300 are disposed, and the second region R2 may be a central region in which the second terminals 330 of the interposer 300 are not disposed.

The second terminals 330 may be arranged along the outer side of the interposer 300 to stabilize an upper package stacked on the package of the inventive concept. Specifically, when solder balls are formed on the second terminals 330 and the upper package is stacked thereon, the upper package will be stably supported because the solder balls will occupy a wide area corresponding to a large area where the second terminals 330 are arranged.

The second region R2 may be a region in which the first dummy hole 420 is disposed. Importantly, the first dummy holes 420 may be disposed in the second region R2 because the second region R2 is a region in which the signal holes 410 are not disposed. Since the first dummy holes 420 serve to minimize or reduce warpage of the package, the first dummy holes 420 should be formed in an area that does not interfere with the functions of other constituent elements, and the second region R2 may be such an area.

In fig. 4, an array of a plurality of dual aligned signal holes 410 and nine first dummy holes 420 is shown. In addition, the first dummy holes 420 may be symmetrically arranged with respect to a geometric center of the upper surface (footprint area) of the molding layer 400. However, the inventive concept is not limited to these numbers and arrangements of the signal holes 410 and the first dummy holes 420.

The shape (as shown in a plan view) of the first dummy hole 420 may be the same as that of the signal hole 410. In addition, referring to fig. 3 and 4, the first dummy hole 420 and the signal hole 410 may have the same shape, size and depth. This may be due to the fact that the processes of forming the first dummy holes 420 and the signal holes 410 may be the same. Accordingly, a process of manufacturing the semiconductor package according to the inventive concept may be extremely easy and simple. That is, since the first dummy holes 420 may be formed in the same process as the process of forming the signal holes 410, the process of forming the first dummy holes 420 does not burden the manufacturing process. Therefore, according to an aspect of the inventive concept, warpage of the semiconductor package can be suppressed without significantly increasing the cost of manufacturing the package.

Referring again to fig. 1, the molding layer 400 of the semiconductor package according to this example substantially has a large thickness above the level of the upper surface of the interposer 300. This is because the bend in the bonding wire 340 must be provided in the bonding wire above the level of the upper surface of the interposer 300. Accordingly, the molding layer 400 may not be formed only to the level of the upper surface of the insert 300 and thus expose the upper surface of the insert 300, or have a very small thickness only above the level of the upper surface of the insert 300.

Thus, utilizing the greater thickness of the molding layer 400 above the level of the upper surface of the interposer (i.e., by forming dummy holes therein) in the manner described above is an effective and efficient solution to the package warpage problem addressed by the present inventive concept. Further, the effect of the inventive concept can be enhanced by forming the plurality of first dummy holes 420, because the warpage relates not only to the volume of the molded layer but also to the surface area thereof.

Hereinafter, another example of a semiconductor package according to the inventive concept will be described with reference to fig. 5 and 6.

The semiconductor package of fig. 5 and 6 is similar to the package of fig. 1, 3 and 4, but further includes a protective film 430.

The protective film 430 may be formed on the upper surface of the interposer 300. The protective film 430 may be formed in the second region R2 of the molding layer 400. The protective film 430 may be exposed to the outside through the first dummy hole 420. The protective film 430 may not occupy any of the first regions R1 where the signal holes 410 are formed.

The protective film 430 may be disposed laterally of the first and second terminals 320 and 330. For example, the first and second terminals 320 and 330 are disposed on the periphery of the upper surface of the interposer 300, and the protective film 430 is disposed at the central portion of the upper surface of the interposer 300.

The thickness of the protective film 430 may be the same as that of the second terminal 330. Accordingly, when the first dummy holes 420 also have the same depth as the signal holes 410, the first dummy holes 420 may penetrate the portion of the molding layer 400 covering the protective film 430. The protective film 430 may thus prevent damage to the insert 300 when the first dummy hole 420 is formed. The protective film 430 may be, but is not limited to, an insulating film such as a Polyimide (PI) film or a polystyrene film.

Hereinafter, another example of a semiconductor package according to the inventive concept will be described with reference to fig. 7.

Referring to fig. 7, the semiconductor package of this example includes dummy holes 421 deeper than the signal holes 410. For purposes of this description only, the dummy hole 421 will be referred to as the second dummy hole.

The second dummy hole 421 may completely penetrate the portion of the molding layer 400 on the insert 300. Therefore, the semiconductor package can be accurately and effectively prevented from warping.

That is, the second dummy hole 421 effectively removes a portion of the molding layer 400 on the insert 300 in the third direction Z, thereby maximally reducing the degree of thermal expansion. As a result, warpage of the entire semiconductor package can be effectively suppressed.

Another version of a signal hole and dummy hole layout of a semiconductor package according to the inventive concept is shown in fig. 8.

Referring to fig. 8, an example of a semiconductor package according to the inventive concept includes dummy holes 422 having a shape different from that of the signal holes 410. For example, the dummy holes 422 may have a rectangular horizontal cross section. For purposes of this description only, the dummy holes 422 will be referred to as third dummy holes.

In the case where the entire shape of the molding layer 400 is square, the rectangular third dummy holes 422 may uniformly relax the molding layer in a horizontal plane. Therefore, the warpage can be effectively suppressed by the third dummy holes 422.

Although the shape of the horizontal cross section of the third dummy hole 422 is illustrated as a square in fig. 8, the horizontal cross section of the third dummy hole 422 may have other shapes. For example, the shape of the horizontal front surface of the third dummy hole 422 may be triangular or elliptical. In other words, the shape of the horizontal front face of the dummy hole is not particularly limited as long as it is suitable for the shape of the molded layer to effectively prevent warpage.

Another version of the layout of the dummy holes and signal holes of the semiconductor package according to the inventive concept is shown in fig. 9.

Referring to fig. 9, the semiconductor package includes dummy holes 423 having a size different from that of the signal holes 410. For example, the dummy holes 423 may be smaller than the signal holes 410. Only for the present specification, the dummy holes 423 are referred to as fourth dummy holes.

In this example, a suitable number of fourth dummy holes 423, each of which is smaller in size than each of the signal holes 410 and is formed in the second region R2, is particularly effective in preventing warpage.

In the example of fig. 9, all the fourth dummy holes 423 are shown as the same size, but they may have different sizes from each other. In other words, the size of the fourth dummy holes 423 is not limited, but the size of the fourth dummy holes 423 is different from that of the signal holes to effectively prevent warpage.

A layout of another version of signal holes and dummy holes of a semiconductor package according to the inventive concept is shown in fig. 10.

Referring to fig. 10, the semiconductor package includes dummy holes 424 arranged in rows and columns together with the signal holes 410, but the number of dummy holes is different and/or positions in the rows and columns are different from each other. For purposes of this specification only, the pseudohole 424 will be referred to as a fifth pseudohole.

In some cases, the semiconductor packages may tend to warp into an asymmetric shape, i.e., may tend to warp differently in each direction. In other words, warpage in a particular direction may tend to be more severe than warpage in other directions. In this example, the fifth dummy hole 424 is arranged at a position designed to alleviate the warpage. For this reason, more fifth dummy holes 424 may be arranged in the semiconductor package in a direction in which warpage would otherwise be relatively severe, and fewer fifth dummy holes 424 may be arranged in a direction in which warpage would otherwise be less severe. The fifth dummy holes 424 may be asymmetrically arranged with respect to a geometric center of the upper surface (occupied area) of the molding layer 400.

The arrangement pattern of the fifth dummy holes 424 shown in fig. 10 is only an example, that is, the semiconductor package of fig. 10 based on the inventive concept is not limited to the arrangement of the fifth dummy holes shown in the drawing.

Therefore, warpage of the semiconductor package can be effectively prevented.

A layout of another version of a semiconductor package according to the inventive concept is shown in fig. 11.

Referring to fig. 11, the semiconductor package includes only one dummy hole 425. For purposes of this specification only, this pseudohole will be referred to as the sixth pseudohole.

The sixth dummy hole 425 may be larger than each signal hole 410. The sixth dummy hole 425 may be located at the center of the second region R2. However, the inventive concept is not limited thereto. Further, the relative shape and size of the sixth dummy hole 425 shown in fig. 11 are only examples.

In any case, since only one sixth dummy hole 425 is formed, the process of manufacturing the semiconductor package according to this example of the inventive concept may be relatively simple. Therefore, the manufacturing cost can be low. Therefore, the semiconductor package can be easily manufactured at low cost and still effectively prevented from warping.

A layout of signal holes and dummy holes of another version of a semiconductor package according to the inventive concept is shown in fig. 12.

Referring to fig. 12, the semiconductor package includes a single dummy hole 426 that is asymmetrical with respect to a geometric center of an upper surface (footprint) of the molding layer 400. For purposes of this specification only, this pseudo-aperture will be referred to as the seventh pseudo-aperture.

The size of the seventh dummy hole 426 may be larger than that of the signal hole 410. The seventh dummy hole 426 may be disposed in a specific portion of the second region R2.

Since only one seventh dummy hole 426 is formed, the process of manufacturing the semiconductor package according to this example of the inventive concept may be relatively simple. In addition, as described above, in some cases, the semiconductor package may tend to warp into an asymmetric shape, that is, may tend to warp to different degrees in various directions. In this example, the seventh dummy hole 426 is formed to compensate for the asymmetric warpage.

That is, the shape of the seventh dummy hole 426 may be more significant in a direction in which warpage of the semiconductor package would otherwise tend to be relatively severe, and less significant in a direction in which warpage would otherwise tend to occur but is less severe. In this example, the seventh pseudo aperture 426 is shown as triangular and occupies about half of the region R2. However, the shape, position, and size of the seventh dummy hole 426 shown in fig. 12 are only examples, and the inventive concept is not limited thereto.

In any case, the semiconductor package according to this example can be easily manufactured at low cost, and it can still effectively prevent warpage.

A layout of signal holes and dummy holes of another version of a semiconductor package according to the inventive concept is shown in fig. 13.

Referring to fig. 13, semiconductor packages according to some embodiments of the present invention include dummy holes of different sizes. For purposes of this specification only, these pseudo-holes will be referred to as eighth pseudo-holes.

In this example, the first 427a of the eighth dummy holes may be the largest. The second 427b and third 427c of the eighth dummy holes may be smaller than the dummy holes 427 a.

The eighth dummy holes 427a, 427b and 427c may have different sizes, and the number of a set of medium-sized eighth dummy holes may be different from the number of another-sized eighth dummy holes. The eighth dummy holes 427a, 427b and 427c may also be asymmetric with respect to the geometric center of the upper surface (occupied area) of the molding layer 400.

However, the shapes, relative positions, numbers, and sizes of the eighth dummy holes 427a, 427b, and 427c shown in fig. 13 are only examples, that is, the inventive concept is not limited thereto.

In the illustrated example, the larger first hole 427a is offset from the geometric center (footprint) of the upper surface of the molding layer 400 in a direction in which warpage of the semiconductor package would otherwise be relatively severe, whereas the second hole 427b and/or the third hole 427c may be offset from the geometric center (footprint) of the upper surface of the molding layer 400 in a direction in which warpage would otherwise occur but is less severe.

As a result, the semiconductor package according to this example can effectively prevent warpage.

Another example of a semiconductor package according to the inventive concept will be described with reference to fig. 14.

The semiconductor package shown in fig. 14 includes an upper package 20 and a lower package 10.

The upper package 20 may be stacked on the lower package 10. Different types of chips may be provided in the upper and lower packages 20 and 10. For example, the lower package 10 may include a logic semiconductor chip, and the upper package 20 may include a memory chip. However, the inventive concept is not limited thereto.

The lower package 10 includes a package substrate 100, a flip chip 200, micro bumps 210, a first underfill film 220, an interposer 300, an adhesive film 310, bonding wires 340, and a molding layer 400. The lower package 10 may be similar to any of the semiconductor packages described above with reference to fig. 1 to 13.

The upper package 20 may include an upper package substrate 1100, second solder balls 1120, first bumps, first memory chips 1200, second underfill films 1250, second bumps, second memory chips 1300, third underfill films 1330, and an upper mold layer 1400.

The first memory chip 1200 and the second memory chip 1300 may be stacked on the upper package substrate 1100. The upper package substrate 1100 supports the first and second memory chips 1200 and 1300, and may be electrically connected to the first and second memory chips 1200 and 1300.

For example, the upper package substrate 1100 may be a Printed Circuit Board (PCB) or a ceramic substrate. However, the inventive concept is not limited thereto.

The lower package substrate terminal 1110 may be disposed at a lower surface of the upper package substrate 1100. The lower package substrate terminal 1110 is in contact with the second solder ball 1120 and may be electrically connected to the lower package 10.

The lower package substrate terminal 1110 may be formed of at least one material selected from the group consisting of copper, nickel, stainless steel, and beryllium copper.

The second solder balls 1120 may be formed in the signal holes 410 of the lower package 10. The second solder balls 1120 may be in contact with the second terminals 330. The second solder balls 1120 may protrude above the level of the upper surface of the molding layer 400 through which the signal holes 410 extend.

The second solder balls 1120 may constitute conductive paths that electrically connect the lower package 10 and the upper package 20 to each other.

The upper package substrate 1100 may include a first TSV (through silicon via) 1130 connected to the lower package substrate terminal 1110. The first TSV1130 may extend through the upper package substrate 1100. The first TSV1130 can transmit a signal most quickly.

The first TSV1130 may be formed of a double film of a core plug and a barrier metal. The core plug may comprise Cu or W. For example, the core plug may be made of, but not limited to, Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloys.

Further, the core plug may include one or more of Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr, and may include one or two or more stacked structures.

The barrier metal may include at least one material selected from the group consisting of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB, and may be composed of a single layer or multiple layers.

The core plug and the barrier metal may be formed through a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, but the inventive concept is not limited thereto. A spacer insulating layer (not shown) may be interposed between the first TSV1130 and the upper package substrate 1100. The spacer insulating layer may prevent direct contact between the semiconductor element in the upper package substrate 1100 and the first TSV 1130. The spacer insulating layer may be composed of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. In some embodiments, the spacer insulating layer may be formed using a CVD process. The spacer insulating layer may be formed of an O3/TEOS (ozone/tetraethylorthosilicate) -based HARP (high aspect ratio process) oxide film formed by a low-pressure CVD (sub-atmospheric CVD) process.

The upper package substrate terminal 1140 may be formed at an upper surface of the upper package substrate 1100. The upper package substrate terminal 1140 may be connected to the lower package substrate terminal 1110 through the first TSV 1130.

The first connection portion 1220 may be formed on the upper package substrate terminal 1140. The first connection part 1220 may be an alloy of tin (Sn) and silver (Ag), and copper (Cu), palladium (Pd), bismuth (Bi), antimony (Sb), or the like may be added, if necessary. Further, the first connection portion 1220 may be a solder ball or a bump, and may further include a pillar layer made of metal such as copper, nickel, and gold, as necessary.

The first connection portion 1220 may electrically connect the upper package substrate terminal 1140 with the first lower memory chip terminal 1210.

The first memory chip 1200 may be stacked on the first connection portion 1220. The first memory chip 1200 may be electrically connected to the upper package substrate 1100 through the first connection part 1220. For example, the first memory chip 1200 may be a memory semiconductor chip. The first memory chip 1200 may be a volatile memory semiconductor chip such as a DRAM (dynamic random access memory) or an SRAM (static random access memory), or may be a non-volatile memory semiconductor chip such as a PRAM (phase change random access memory), MRAM (magnetoresistive random access memory), FeRAM (ferroelectric random access memory), or RRAM (resistive random access memory). However, the inventive concept is not limited thereto.

The first memory chip 1200 may include a first lower memory chip terminal 1210, a second TSV 1230, and a first upper memory chip terminal 1240.

The first lower memory chip terminal 1210 may be formed at a lower surface of the first memory chip 1200. The first lower memory chip terminal 1210 may be in contact with the first connection portion 1220. The first memory chip 1200 may be electrically connected to the upper package substrate 1100 through the first lower memory chip terminal 1210, the first connection portion 1220, and the upper package substrate terminal 1140.

The second TSV 1230 may be formed through the first memory chip 1200. Since the second TSV 1230 extends in the third direction Z, it can most quickly transmit a signal.

The material and structure forming the second TSV 1230 may be the same as those of the first TSV 1130. That is, the second TSV 1230 may include a core plug and a barrier metal like the first TSV 1130. The process of forming the second TSV 1230 may be the same as the process used to form the first TSV 1130. Here, "the same" means the same method performed at different time points.

The first upper memory chip terminal 1240 may be formed on the upper surface of the first memory chip 1200. The first upper memory chip terminals 1240 may make contact with the second connection portions 1320. The first memory chip 1200 may be electrically connected to the second memory chip 1300 through the first upper memory chip terminal 1240, the second connection unit 1320, and the second lower memory chip terminal 1310.

The second connection portion 1320 may be formed at the first upper memory chip terminal 1240. Like the first connection part 1220, the second connection part 1320 may be an alloy of tin (Sn) and silver (Ag), and copper (Cu), palladium (Pd), bismuth (Bi), antimony (Sb), or the like may be added if necessary. Further, the second connection portions 1320 may be solder balls or bumps, and may further include a post layer made of metal such as copper, nickel, and gold, as necessary.

The second connection portion 1320 may electrically connect the first upper memory chip terminal 1240 and the second lower memory chip terminal 1310.

The second memory chip 1300 may be stacked on the second connection portion 1320. The second memory chip 1300 may be electrically connected to the first memory chip 1200 through a second connection portion 1320.

The second memory chip 1300 may be the same type of memory chip as the first memory chip 1200. Alternatively, the second memory chip 1300 may be a different type of memory chip from the first memory chip 1200.

For example, the second memory chip 1300 may be a volatile memory semiconductor chip such as a DRAM or an SRAM, or a non-volatile memory semiconductor chip such as a PRAM, MRAM, FeRAM, or RRAM. However, the inventive concept is not limited thereto.

The second lower memory chip terminal 1310 may be formed at a lower surface of the second memory chip 1300. The second lower memory chip terminal 1310 may be in contact with the second connection portion 1320. The second memory chip 1300 may be electrically connected to the first memory chip 1200 via the second lower memory chip terminal 1310, the second connection portion 1320, and the first upper memory chip terminal 1240.

The second underfill film 1250 may fill a space between the upper package substrate 1100 and the first memory chip 1200. As such, the second underfill film 1250 may serve to reinforce the coupling of the upper package substrate 1100 to the first memory chip 1200 or may serve to prevent deformation. In addition, the intrusion of foreign substances or moisture can be prevented.

The second underfill film 1250 may protrude from a space between the first memory chip 1200 and the upper package substrate 1100 to the outside of the side surface of the first memory chip 1200. In addition, the second underfill film 1250 may be integrally connected to a third underfill film 1330, which will be described later. However, the present invention is not limited to these specific cases.

Here, the expression "integrally connected" may mean that the second underfill film 1250 and the third underfill film 1330 are continuous without a boundary or interface.

The third underfill film 1330 may fill a space between the first memory chip 1200 and the second memory chip 1300. The third underfill film 1330 may protrude from a space between the first and second memory chips 1200 and 1300 to the outside of the side surfaces of the first and second memory chips 1200 and 1300. In addition, the third underfill film 1330 may be integrally connected to the second underfill film 1250. However, the inventive concept is not limited thereto.

The upper mold layer 1400 may cover the upper package substrate 1100, the first memory chip, the second underfill portion, and the third underfill film 1330.

For example, the upper mold layer 1400 may be formed of a silicon-based material, a thermosetting material, a thermoplastic material, a UV-treated material, or the like. Further, the molding layer 400 may be formed of a polymer such as a resin, and may be formed of, for example, EMC.

Fig. 14 illustrates the upper package 20 having two memory chips stacked, but the inventive concept is not limited thereto. That is, the semiconductor package according to the inventive concept may include an upper package in which three or more memory chips are stacked. Alternatively, the upper package 20 may have only the memory chip without the upper package substrate 1100.

In the semiconductor packages according to these examples, since the lower package 10 includes the dummy hole, occurrence of warpage can be prevented. Accordingly, reliability and durability of the lower package 10 are improved, and the operational performance of the semiconductor package may be improved.

Hereinafter, another example of a semiconductor package according to the inventive concept will be described with reference to fig. 15.

The semiconductor package of the example of fig. 15 includes a fourth underfill film 1500 between the upper package 20 and the lower package 10.

The fourth underfill film 1500 may surround side surfaces of the second solder balls 1120. The fourth underfill film 1500 may fill a space between the upper package 20 and the lower package 10. The fourth underfill film 1500 may include an underfill resin such as an epoxy, a silica filler, or a flux.

In the semiconductor package according to this example, since the coupling between the upper package 20 and the lower package 10 is rigid and the upper package 20 coupled to the lower package 10 by the fourth underfill film 1500 resists the warpage of the lower package 10, a semiconductor package having high reliability and durability can be provided.

Hereinafter, another example of a semiconductor package according to the inventive concept will be described with reference to fig. 16.

The semiconductor package according to the example of fig. 16 includes an air gap 1510.

The air gap 1510 may be located inside the fourth underfill film 1500. An air gap 1510 may be formed between the upper package 20 and the lower package 10.

In the semiconductor package according to this example, the air gap 1510 mitigates warpage that would otherwise be caused in the package by thermal expansion of the fourth underfill film 1500. Therefore, the semiconductor package has improved durability.

Finally, while the inventive concept has been particularly shown and described with reference to various examples thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims. It is therefore to be understood that the foregoing examples are illustrative and not limiting, and that reference is made to the appended claims, rather than to the foregoing description, as indicating the true spirit and scope of the invention.