阅读说明：本技术 包含具有几何属性的过孔的制品及其制造方法 (Article comprising via having geometric properties and method of making the same ) 是由 黄甜 金宇辉 M·E·威廉 于 2018-05-22 设计创作，主要内容包括：公开了包括基于玻璃的基板的制品和半导体封装件及其形成方法。制品包括基于玻璃的基板,该基板包括彼此隔开一段距离并彼此平行的第一和第二主表面,以及通过基板延伸的锥形过孔。锥形过孔包括内壁和关于平面对称的横截面,所述平面在基于玻璃的基板的第一主表面和第二主表面之间并且与这两个主表面等距,所述内壁具有位于第一主表面与所述平面之间的第一锥形区域和第二锥形区域。第一锥形区域和第二锥形区域各自的斜度是恒定的,并且第一锥形区域的斜度不等于第二锥形区域的斜度。(Articles and semiconductor packages including glass-based substrates and methods of forming the same are disclosed. The article includes a glass-based substrate including first and second major surfaces spaced apart from and parallel to each other, and a tapered via extending through the substrate. The tapered via includes an inner wall and a cross-section that is symmetrical about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate, the inner wall having a first tapered region and a second tapered region that are between the first major surface and the plane. The respective slopes of the first tapered region and the second tapered region are constant, and the slope of the first tapered region is not equal to the slope of the second tapered region.)

1. An article of manufacture, comprising:

a glass-based substrate comprising a first major surface, a second major surface spaced a distance from the first major surface, and a tapered through-hole extending through the substrate from the first major surface to the second major surface, the tapered through-hole comprising:

a cross-section that is symmetrical about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate; and

an inner wall having a first tapered region and a second tapered region between a first major surface and the plane, wherein:

the slope of the first tapered region is constant,

the slope of the second conical region is constant, and

the slope of the first tapered region is not equal to the slope of the second tapered region.

2. The article of claim 1, wherein:

the slope of the first tapered region comprises a height to length ratio of 3:1 to 100: 1; and

the slope of the second tapered region comprises a height to length ratio of 3:1 to 100: 1.

3. The article of any preceding claim, wherein the first tapered region extends from the first major surface toward the second major surface by a distance of 15 microns to 360 microns.

4. The article of any preceding claim, wherein the second tapered region extends from the intersection with the first tapered region toward the second major surface by a distance of 35 microns to 175 microns.

5. The article of any of claims 1-3, wherein the second tapered region extends from the second major surface toward the first major surface at a distance of 35 microns to 175 microns.

6. The article of any preceding claim, wherein the tapered via has a diameter of 10 to 250 microns at the first major surface.

7. The article of any preceding claim, wherein the tapered via has a diameter at the plane of 5 to 200 microns.

8. The article of any preceding claim, further comprising a transition region between the first tapered region and the second tapered region, wherein the transition region comprises a region that transitions from the slope of the first tapered region to the slope of the second tapered region such that the slope of the tangent line relative to the inner wall changes by at least 0.57 degrees.

9. The article of claim 8, wherein the transition region is a point or an extended region.

10. The article of any preceding claim, wherein the distance between the first major surface and the second major surface is in the range of 25 micrometers to 3,000 micrometers.

11. The article of any preceding claim, wherein:

the inner wall further comprises a third tapered region; and is

The slope of the third tapered region is different from at least one of the slope of the first tapered region and the slope of the second tapered region.

12. The article of any preceding claim, wherein the glass-based substrate is chemically strengthened.

13. The article of any preceding claim, wherein the glass-based substrate is a laminate.

14. The article of any preceding claim, wherein the tapered via is filled with a conductive material.

15. An article of manufacture, comprising:

a glass-based substrate comprising a first major surface, a second major surface spaced a distance from the first major surface, and a tapered via extending through the substrate from the first major surface to the second major surface, the tapered via comprising:

a cross-section that is asymmetric about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate; and

an inner wall having a first tapered region and a second tapered region between a first major surface and the plane, wherein:

the slope of the first tapered region is constant,

the slope of the second conical region is constant, and

the slope of the first tapered region is not equal to the slope of the second tapered region.

16. The article of manufacture of claim 15, wherein the tapered via comprises a through hole.

17. The article of claim 15, wherein the tapered via comprises a blind via.

18. The article of any one of claims 15-17, wherein:

the slope of the first tapered region comprises a height to length ratio of 3:1 to 100: 1; and

the slope of the second tapered region comprises a height to length ratio of 3:1 to 100: 1.

19. The article of any of claims 15-18, wherein the first tapered region extends from the first major surface toward the second major surface by a distance of 15 microns to 360 microns.

20. The article of any one of claims 15-19, wherein the second tapered region extends from the intersection with the first tapered region toward the second major surface by a distance of 35 microns to 175 microns.

21. The article of any one of claims 15-19, wherein the second tapered region extends from the second major surface toward the first major surface at a distance of 35 microns to 175 microns.

22. The article of any of claims 15-21, wherein the tapered via has a diameter of 10 microns to 250 microns at the first major surface.

23. The article of any of claims 15-22, wherein the tapered via has a diameter at the plane of 5 to 200 microns.

24. The article of any one of claims 15-23, further comprising a transition region between the first tapered region and the second tapered region, wherein the transition region comprises a region that transitions from the slope of the first tapered region to the slope of the second tapered region such that the slope of the tangent line relative to the inner wall changes by at least 0.57 degrees.

25. The article of claim 24, wherein the transition region is a point or an extended region.

26. The article of any one of claims 15-25, wherein the distance between the first major surface and the second major surface is in a range from 25 micrometers to 3,000 micrometers.

27. The article of any one of claims 15-26, wherein:

the inner wall further comprises a third tapered region; and is

The slope of the third tapered region is different from at least one of the slope of the first tapered region and the slope of the second tapered region.

28. The article of any one of claims 15-27, wherein the glass-based substrate is chemically strengthened.

29. The article of any one of claims 15-28, wherein the glass-based substrate comprises a laminate.

30. The article of any of claims 15-29, wherein the tapered via is filled with a conductive material.

31. A semiconductor package, comprising:

a glass-based substrate comprising a first major surface, a second major surface spaced a distance from the first major surface, and a tapered through-hole extending through the substrate from the first major surface to the second major surface, the tapered through-hole comprising:

a cross-section that is symmetrical about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate; and

an inner wall having a first tapered region and a second tapered region between a first major surface and the plane, wherein:

the slope of the first tapered region is constant,

the slope of the second conical region is constant, and

the slope of the first tapered region is not equal to the slope of the second tapered region,

a conductive material disposed in the tapered via; and

a semiconductor device electrically connected to the conductive material disposed in the tapered via.

32. A semiconductor package, comprising:

a glass-based substrate comprising a first major surface, a second major surface spaced a distance from the first major surface, and a tapered via extending through the substrate from the first major surface to the second major surface, the tapered via comprising:

a cross-section that is asymmetric about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate; and

an inner wall having a first tapered region and a second tapered region between a first major surface and the plane, wherein:

the slope of the first tapered region is constant,

the slope of the second conical region is constant, and

the slope of the first tapered region is not equal to the slope of the second tapered region,

a conductive material disposed in the tapered via; and

a semiconductor device electrically connected to the conductive material disposed in the tapered via.

33. A method of forming a glass-based substrate including at least one via, the method comprising:

etching a glass-based article having at least one damage track with a first etchant at a first etch rate;

etching the glass-based article with a second etchant at a second etch rate,

wherein the second etchant comprises an etchant concentration different from the first etchant concentration to form a glass-based substrate including at least one via, an

Wherein the at least one via includes a first tapered region having a first constant slope and a second tapered region having a second constant slope, the first and second constant slopes being unequal.

34. The method of claim 33, wherein the first etchant comprises a higher concentration of an acid etchant or a base etchant than the second etchant.

35. The method of claim 33 or 34, wherein the first etchant comprises a lower concentration of an acid etchant or a base etchant than the second etchant.

36. The method of claim 35, wherein the first etchant and the second etchant each comprise an acid etchant or a base etchant.

37. The method of any of claims 33-36, wherein the first etch rate is greater than the second etch rate.

38. The method, as recited in any of claims 33-36, wherein the first etch rate is less than the second etch rate.

39. The method of any of claims 33-38, further comprising forming the at least one damage track, wherein the energy delivered to the planar glass-based article is above a damage threshold along an entire width of the glass-based article.

40. The method of claim 39, wherein forming the at least one damage track comprises forming a damage track such that energy delivered to the glass-based article is above the damage threshold along a first side of the glass-based article and below the damage threshold along a second side of the glass-based article.

41. The method of any of claims 33-40, wherein the method further comprises:

applying a first etch-resistant coating to a first side of the glass-based article prior to etching the glass-based article with a first etchant;

removing the first etch-resistant coating from the first side of the glass-based article after etching the glass-based article with a second etchant;

applying a second etch-resistant coating to a second side of the glass-based article;

etching the glass-based article with the second etch-resistant coating applied to the second side of the glass-based article with a third etchant bath; and

the second etch-resistant coating is removed from the second side of the planar glass-based article.

42. The method of any of claims 33-41, wherein the method further comprises:

etching the planar glass-based article in a third etchant to form a glass-based substrate including at least one via.

43. The method of any of claims 33-42, further comprising adjusting at least one of a temperature, an etchant concentration, and a degree of agitation of at least one of the first etchant and the second etchant.

44. The method of any of claims 33-43, wherein each of the at least one via comprises a through hole or a blind hole.

45. The method of any of claims 33-44, wherein the at least one via comprises a cross-section that is symmetrical about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate.

46. The method of any of claims 33-44, wherein the at least one via comprises a cross-section that is asymmetric about a plane that is between and equidistant from the first and second major surfaces of the glass-based substrate.

47. A method of forming a glass-based substrate including at least one via, the method comprising:

etching a glass-based article having at least one damage track in an etchant; and

adjusting at least one of a temperature, a concentration, and a degree of agitation of the etchant to form a glass-based substrate including at least one through-hole such that the at least one through-hole includes a continuously varying sidewall taper and a cross-section that is symmetrical about a plane that is between and equidistant from a first major surface and a second major surface of the glass-based substrate.

48. A method of forming a glass-based substrate including at least one blind via, the method comprising:

etching a glass-based article having at least one damage track in an etchant; and

adjusting at least one of a temperature, a concentration, and a degree of agitation of the etchant to form a glass-based substrate including at least one blind via such that the at least one blind via includes a continuously varying sidewall taper.

Technical Field

Substrates such as silicon have been used as interposers between electronic components (e.g., printed circuit boards, integrated circuits, etc.). The metallized through-substrate vias provide a path through the interposer for electrical signals to pass between opposite sides of the interposer. Glass is a substrate and is highly advantageous for electrical signal transmission because of its dimensional stability, tunable coefficient of thermal expansion ("CTE"), very good low electrical losses at high frequency electrical performance, high thermal stability, and the ability to be formed with a certain thickness and larger panel dimensions. However, the formation and metallization of glass vias ("TGVs") present challenges in the development of the glass interposer market.

The geometric properties of the vias play an important role in their ability to properly metallize the vias within the glass-based substrate. For example, during sputter metallization, the taper angle of the via sidewall may increase the field of view of the via sidewall relative to the sputtered material, thereby preventing bubbles from being trapped against the glass surface and toward the via centerline. These bubbles create processing problems during high temperature redistribution layer ("RDL") operations and may reduce the reliability of the substrate.

Thus, there is a need for a substrate having a particular via geometry and a method of forming the same.

SUMMARY

According to one embodiment, an article includes a glass-based substrate having a first major surface, a second major surface spaced a distance from the first major surface, and a tapered through-hole (through via) extending through the substrate from the first major surface toward the second major surface. The tapered through-hole includes a cross-section that is symmetrical about a plane between and equidistant from a first major surface and a second major surface of the glass-based substrate, and an inner wall having a first tapered region and a second tapered region between the first major surface and the plane. The slope of the first tapered region is constant and the slope of the second tapered region is constant. The slope of the first tapered region is not equal to the slope of the second tapered region.

In another embodiment, an article includes a glass-based substrate having a first major surface, a second major surface spaced a distance from the first major surface, and a tapered via extending through the substrate from the first major surface toward the second major surface. The tapered through-hole includes a cross-section that is asymmetric about a plane between and equidistant from a first major surface and a second major surface of the glass-based substrate, and an inner wall having a first tapered region and a second tapered region between the first major surface and the plane. The slope of the first tapered region is constant and the slope of the second tapered region is constant. The slope of the first tapered region is not equal to the slope of the second tapered region.

In another embodiment, a semiconductor package includes a glass-based substrate having a first major surface, a second major surface spaced a distance from the first major surface, and a tapered via extending through the substrate from the first major surface toward the second major surface. The tapered via includes a cross-section that is symmetric about a plane between and equidistant from a first major surface and a second major surface of the glass-based substrate, and an inner wall having a first tapered region and a second tapered region between the first major surface and the plane. The slope of the first tapered region is constant and the slope of the second tapered region is constant. The slope of the first tapered region is not equal to the slope of the second tapered region. The semiconductor package also includes a conductive material disposed within the tapered via and a semiconductor device electrically connected to the conductive material disposed within the tapered via.

In another embodiment, a semiconductor package includes a glass-based substrate having a first major surface, a second major surface spaced a distance from the first major surface, and a tapered via extending through the substrate from the first major surface toward the second major surface. The tapered via includes a cross-section that is asymmetric about a plane between and equidistant from a first major surface and a second major surface of the glass-based substrate, and an inner wall having a first tapered region and a second tapered region between the first major surface and the plane. The slope of the first tapered region is constant and the slope of the second tapered region is constant. The slope of the first tapered region is not equal to the slope of the second tapered region. The semiconductor package also includes a conductive material disposed within the tapered via and a semiconductor device electrically connected to the conductive material disposed within the tapered via.

In another embodiment, a method of forming a glass-based substrate having at least one via includes: etching the glass-based article having the at least one damage track with a first etchant at a first etch rate and etching the glass-based article with a second etchant at a second etch rate forms a glass-based substrate having at least one via. The second etchant bath includes an etchant concentration that is different from the etchant concentration in the first etchant bath. The at least one via includes a first tapered region having a first constant slope and a second tapered region having a second constant slope, the first and second constant slopes being unequal.

In another embodiment, a method of forming a glass-based substrate having at least one via includes: etching the glass-based article in an etchant and adjusting at least one of the temperature, concentration and degree of agitation of the etchant to: forming a glass-based substrate having the at least one via such that the at least one via has a continuously varying sidewall taper and a symmetrical profile about a center of the glass-based substrate.

In another embodiment, a method of forming a glass-based substrate having at least one blind via (die via) includes: etching a glass-based article in an etchant bath, and adjusting at least one of a temperature, a concentration, and a degree of agitation of the etchant bath to form a glass-based substrate having at least one blind via such that the at least one blind via includes a continuously varying sidewall taper.

Additional features and advantages of methods of forming glass-based structures (e.g., interposer and interposer components) will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments described herein, including the detailed description which follows, the claims, and the appended drawings.

It is to be understood that both the foregoing general description and the following detailed description describe various embodiments, and are intended to provide an overview or framework for understanding the nature and character of the claimed subject matter. The accompanying drawings are included to provide a further understanding of the various embodiments, and are incorporated into and constitute a part of this specification. The drawings illustrate various embodiments described herein and together with the description serve to explain the principles and operations of the claimed subject matter.

Brief description of the drawings

The embodiments presented in the figures are illustrative and exemplary in nature and are not intended to limit the subject matter defined by the claims. The following detailed description of illustrative embodiments can be understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals, and in which:

fig. 1 schematically depicts an exemplary semiconductor assembly including a glass interposer, according to one or more embodiments illustrated and described herein;

fig. 2A schematically depicts an exemplary article of manufacture configured as a wafer having vias therein according to one or more embodiments illustrated and described herein;

fig. 2B schematically depicts a top view of a portion of an exemplary wafer having vias therein according to one or more embodiments illustrated and described herein;

fig. 3A schematically depicts a cross-sectional side view of an exemplary via geometry in accordance with one or more embodiments illustrated and described herein;

FIG. 3B schematically depicts a detailed view of a change in slope between two tapered regions of an inner wall of the via shown in FIG. 3A, according to one or more embodiments illustrated and described herein;

fig. 3C schematically depicts a cross-sectional side view of another exemplary via geometry, according to one or more embodiments illustrated and described herein;

fig. 3D schematically depicts a cross-sectional side view of yet another via geometry in accordance with one or more embodiments illustrated and described herein;

fig. 3E schematically depicts a cross-sectional side view of yet another via geometry in accordance with one or more embodiments illustrated and described herein;

fig. 3F schematically depicts a cross-sectional side view of yet another via geometry in accordance with one or more embodiments illustrated and described herein;

fig. 3G schematically depicts a cross-sectional side view of an exemplary tapered via having a particular via geometry, according to one or more embodiments illustrated and described herein;

fig. 4 schematically depicts a cross-sectional side view of a portion of an exemplary taper showing the length of various tapered regions of its inner wall, according to one or more embodiments illustrated and described herein.

Fig. 5A depicts a flow diagram of an exemplary method of forming a glass article according to one or more embodiments illustrated and described herein;

fig. 5B schematically depicts a cross-sectional side view of an exemplary tapered via subjected to multiple etching processes, according to one or more embodiments illustrated and described herein;

FIG. 6 depicts an exemplary via radius versus distance from a surface of a glass article formed by the method described in connection with FIG. 5;

fig. 7 depicts a flow diagram of another exemplary method of forming a glass article according to one or more embodiments illustrated and described herein;

FIG. 8 depicts an exemplary via radius versus axial position for one of the glass articles formed by the method described in connection with FIG. 7;

FIG. 9 depicts another exemplary via radius versus axial position for another glass article formed by the method described in connection with FIG. 7;

fig. 10 depicts a flow diagram of another exemplary method of forming a glass article according to one or more embodiments illustrated and described herein;

FIG. 11 depicts an exemplary via profile versus axial position for one of the glass articles formed by the method described in connection with FIG. 10;

fig. 12 depicts a flow diagram of yet another exemplary method of forming a glass article according to one or more embodiments illustrated and described herein;

FIG. 13 depicts an exemplary via radius versus axial position for one of the glass articles formed by the method described in connection with FIG. 12;

fig. 14A depicts an image of a cross-sectional view of an exemplary tapered via, according to one or more embodiments illustrated and described herein;

FIG. 14B schematically depicts computer-assisted tracing of the inner walls of the exemplary tapered via depicted in FIG. 14A;

FIG. 15A graphically depicts a plurality of tapered regions of the exemplary tapered via depicted in FIG. 14A, as determined by a computer program in accordance with one or more embodiments illustrated and described herein; and

fig. 15B graphically depicts absolute values of an exemplary fit residual of the graph depicted in fig. 15A, in accordance with one or more embodiments illustrated and described herein.

Detailed Description

Referring generally to the drawings, embodiments of the present disclosure generally relate to articles having vias (e.g., holes) and surface properties that allow for successful downstream processing, including but not limited to the application of via metallization and redistribution layers (RDLs). The article can be used in semiconductor devices, Radio Frequency (RF) devices (e.g., antennas, switches, etc.), interposer devices, microelectronic devices, optoelectronic devices, micro-electro-mechanical system (MEMS) devices, and other applications that utilize vias.

More particularly, embodiments described herein relate to glass-based articles having vias formed by laser damage and etching processes that include a particular inner wall geometry, such as an inner wall that includes a plurality of regions each having a different slope. Finally, the vias may be coated or filled with a conductive material. Vias with specific inner wall geometries can improve the reliability of downstream processes, such as metallization processes. For example, the particular geometry of the inner wall may prevent the bubbles from being encapsulated against the sidewall surface during metallization.

Embodiments of the present disclosure also relate to laser forming and etching methods that result in glass-based articles having vias with desired geometries. Articles, such as glass articles, having desired via geometries described herein may be used as interposers in semiconductor devices (e.g., RF antennas).

Various embodiments of articles, semiconductor packages, and methods of forming vias in substrates are described in detail below.

The term "interposer" generally refers to any structure through which an electrical connection between, for example, but not limited to, two or more electronic devices disposed on opposite surfaces of an interposer is extended or completed. Two or more electronic devices may be co-located in a single structure, or may be located adjacent to each other in different structures, such that the interposer serves as part of an interconnect node (interconnect node) or the like. As such, the interposer may contain one or more active areas in which glass vias and other interconnect conductors (e.g., power, ground, and signal conductors) are present and formed. The interposer may also include one or more active areas in which blind vias are present and formed. When the interposer is formed of other components such as a die (die), underfill material, encapsulant, and/or the like, the interposer may be referred to as an interposer component. Also, the term "interposer" may further include a plurality of interposers, such as an array of interposers or the like.

Fig. 1 depicts an illustrative example of a semiconductor package, generally designated 10, including an article 15, a conductive material 20, and a semiconductor device 25. The components of the semiconductor package 10 may be arranged such that the conductive material 20 is located on at least a portion of the article 15, for example, within a via of a substrate of the article 15, as described in more detail below. Semiconductor device 25 may be coupled such that semiconductor device 25 is in electrical contact with conductive material 20. In some embodiments, the semiconductor device 25 may directly contact the conductive material 20. In other embodiments, the semiconductor device 25 may indirectly contact the conductive material 20, for example, via bumps 30 and/or the like.

Fig. 2A schematically illustrates a perspective view of an exemplary substrate 100, the exemplary substrate 100 having a plurality of vias 120 disposed therein. Fig. 2B schematically depicts a top view of the exemplary article depicted in fig. 2A. Although fig. 2A and 2B depict the substrate 100 as being configured as a wafer, it should be understood that the article may take any shape, such as, but not limited to, a panel. The substrate 100 may be substantially planar and may have a first major surface 110 and a second major surface 112, the second major surface 112 being opposite the first major surface 110 and planar as the first major surface 110.

The articles described herein are made of a light transmissive material that is capable of passing radiation having a wavelength within the visible spectrum. For example, the substrate 100 may transmit at least about 70%, at least about 75%, at least about 80%, at least about 85%, or at least about 90% of at least one wavelength in the range of about 390nm to about 700 nm. The substrate 100 may be a glass-based substrate. Glass-based substrate materials are materials that are partially or entirely made of glass and include, but are not limited to, glass (including fused silica) and glass-ceramics. In some embodiments, the substrate 100 may be glass, and the glass may include fused silica, alkali-containing glass, or alkali-free glass (e.g., alkali-free alkali aluminoborosilicate glass). In some embodiments, the substrate 100 may be a glass layer, a glass-ceramic layer, or a laminate of a combination of glass and glass-ceramic layers. In some embodiments, the substrate 100 is formed of glass or glass-ceramic, which may be chemically strengthened, such as by an ion exchange process (e.g., "chemically strengthened glass" or "chemically strengthened glass-ceramic"). For example, substrate 100 may be formed from a soda lime glass batch composition, an alkali aluminosilicate glass batch composition, or other glass batch composition that may be strengthened by ion exchange after formation. In a particular example, the substrate 100 may be formed from glass produced by Corning Incorporated.

In some embodiments, the substrate 100 may have a low coefficient of thermal expansion (e.g., less than or equal to about 4 ppm/deg.C), and in other embodiments, the substrate 100 may have a high coefficient of thermal expansion (e.g., greater than about 4 ppm/deg.C).

As described above, the substrate 100 may be used as an interposer in an electronic device to pass electrical signals through the substrate 100, for example, but not limited to, between one or more electronic components connected to the first major surface 110 of the substrate 100 and one or more electronic components connected to the second major surface 112. The vias 120 of the substrate 100 are filled with a conductive material to provide conductive vias through which electrical signals can pass. For example, the via 120 may be a glass through hole or a blind hole. As used herein, a glass via extends through the substrate from the first major surface 110 to the second major surface 112 by a thickness T of 100 a. As used herein, a blind via extends only partially into the thickness T of the substrate 100 from one of the first or second major surfaces 110, 112, but does not extend all the way to the other of the first or second major surfaces 110, 112. Other features may be formed within the first major surface 110 or the second major surface 112 of the substrate 100, such as, but not limited to, vias that may be metallized to provide one or more electrical trace patterns. Other features may also be provided.

The substrate 100 is of any size and/or shape, which may depend, for example, on the end application. By way of example and not limitation, the thickness T of the substrate 100 may be in a range from about 25 microns to about 3,000 microns, including about 25 microns, about 50 microns, about 75 microns, about 100 microns, about 200 microns, about 300 microns, about 400 microns, about 500 microns, about 600 microns, about 700 microns, about 800 microns, about 900 microns, about 1,000 microns, about 2,000 microns, about 3,000 microns, or a value or range between any two of these values (including endpoints).

The vias 120 of the substrate 100 can have, for example, an opening diameter D of about 10 microns to about 250 microns, including about 15 microns or less, about 20 microns or less, about 25 microns or less, about 30 microns or less, 35 microns or less, about 40 microns or less, about 50 microns or less, about 60 microns or less, about 70 microns or less, about 80 microns or less, about 90 microns or less, about 100 microns or less, about 110 microns or less, about 120 microns or less, about 130 microns or less, about 140 microns or less, about 150 microns or less, about 160 microns or less, about 170 microns or less, about 180 microns or less, about 190 microns or less, about 200 microns or less, about 210 microns or less, about 220 microns or less, about 230 microns or less, about 240 microns or less, about 250 microns or less, or any two or more of these values, inclusive. As used herein, the opening diameter D refers to the diameter of the opening of the via 120 at the first major surface 110 or at the second major surface 112 of the substrate 100. The opening of the via 120 is typically at a location marking the transition between the substantially horizontal major surfaces 110, 112 and the inclined surface of the wall of the via 120. The opening diameter D of the via 120 may be determined by: the diameter of the least squares best fit circle of the entrance edge of the through hole 120 is found by optical microscopy imaging.

Similarly, the via 120 of the substrate 100 may have an opening radius R of about 5 microns to about 150 microns. As used herein, the opening radius R refers to a radius from a center point C of the opening of the via 120 at the first or second major surface 110, 112 of the substrate 100.

The pitch Z of the vias 120 is the center-to-center pitch between adjacent vias 120, which may be any size depending on the desired application, such as, but not limited to, about 10 microns to about 2,000 microns, including about 10 microns, about 50 microns, about 100 microns, about 250 microns, about 1,000 microns, about 2,000 microns, or any value or range between any two of these values (including endpoints). In some embodiments, the pitch Z may vary between vias 120 on the same substrate 100 (i.e., the pitch Z between the first and second vias may be different than the pitch Z between the first and third vias). In some embodiments, the pitch Z may range from, for example, about 10 microns to about 100 microns, about 25 microns to about 500 microns, about 10 microns to about 1,000 microns, or about 250 microns to about 2,000 microns.

As defined herein, the average thickness T of the substrate 100 is determined by: the thickness measurements are taken outside any recessed regions created on the first or second major surfaces 110, 112 due to the formation of the vias 120, and the results of the three thickness measurements are averaged. As defined herein, thickness measurements are made by an interferometer. As described in more detail below, the laser damage and etching process may create a recessed region around a hole formed in the substrate 100. Therefore, the average thickness T is determined by measuring the thickness of the substrate 100 at three locations outside the recessed region. As used herein, the phrase "outside the recessed region" refers to measurements taken at a distance in the range of about 500 microns to about 2,000 microns from the nearest via 120. Furthermore, in order to obtain an accurate representation of the average thickness of the article, the measurement points should be spaced at least about 100 microns from each other. In other words, no measurement point should be within 100 microns of another measurement point.

As noted above, the conductive material may be filled into the vias 120 (and other features in some embodiments) using any known technique, including but not limited to sputtering, electroless and/or electrolytic plating, chemical vapor deposition, and/or the like. The conductive material may be, for example, copper, silver, aluminum, titanium, gold, platinum, nickel, tungsten, magnesium, or any other suitable material. When the vias 120 are filled, they can be electrically connected to electrical traces of electrical components disposed on the first and second major surfaces 110, 112 of the substrate 100.

The geometry of the via 120 may play a role in the final fill quality of the via 120. The internal shape (i.e., profile) of the via 120 can play an important role in the success of the metallization process. For example, vias that are too "hourglass" shaped can result in poor metallization and inadequate electrical performance after metallization. Metallization processes, such as vacuum deposition coating, often have line-of-sight issues, meaning that the applied coating cannot reach the innermost regions of the rough texture or the lower regions of the hourglass shaped vias because some points on the surface "mask" other points from going through the coating process. The same hourglass shape may also lead to reliability problems after metallization, such as cracking and other failures when the part is subjected to environmental stresses (e.g., thermal cycling). In addition, along the top and bottom surfaces of the article, depressions or hillocks near the entrance and/or exit of the vias 120 may also cause plating, coating, and adhesion problems when the redistribution layer process is applied. Therefore, the topography of the holes should be tightly controlled to produce a technically feasible product. Embodiments of the present disclosure provide articles having desired geometric properties, tolerances, and example methods of manufacture for obtaining articles having such geometric properties and tolerances.

Although specific reference is made herein to vias 120 having different cross-sectional geometries through the thickness of substrate 100, it should be understood that vias 120 may include a variety of other cross-sectional geometries, and thus, the embodiments described herein are not limited to any particular cross-sectional geometry of vias 120. Further, although the vias 120 are depicted as having a circular cross-section in the plane of the substrate 100, it should be understood that the vias 120 may have other planar cross-sectional geometries. For example, the vias 120 may have various other cross-sectional geometries in the plane of the substrate 100, including, but not limited to, an elliptical cross-section, a square cross-section, a rectangular cross-section, a triangular cross-section, and the like. Further, it should be understood that vias 120 having different cross-sectional geometries may be formed in a single interlayer plate.

Fig. 3A-3G schematically depict various illustrative vias within the isolated substrate 100. Fig. 3A, 3C, 3D, 3E, and 3F depict glass through holes, and fig. 3G depicts blind holes, respectively. It should be understood that various portions of the description provided herein may be specifically directed to a particular one of fig. 3A-3G, but generally applies to any of the various embodiments depicted with respect to fig. 3A-3G, unless specifically noted otherwise.

Fig. 3A depicts a cross-sectional side view of an exemplary via 120, according to one embodiment. The vias 120 may typically be glass through holes, as the vias 120 extend the entire distance of the substrate 100 between the first and second major surfaces 110, 112 of the substrate 100. The first and second major surfaces 110, 112 can be generally parallel to each other and/or spaced a distance from each other. In some embodiments, the distance between first major surface 110 and second major surface 112 may correspond to an average thickness T (fig. 2A). The tapered via 120 may generally include an inner wall 122 that extends the entire length of the tapered via 120. That is, the inner wall 122 extends from the first main surface 110 to the second main surface 112 of the substrate 100. The inner wall 122 includes a plurality of tapered regions, wherein each tapered region is distinguished from the other tapered regions by its relative slope, as described in more detail herein. In a non-limiting example, fig. 3A depicts the inner wall 122 as having a first tapered region 124, a second tapered region 126, and a third tapered region 128, wherein the first tapered region 124, the second tapered region 126, and the third tapered region 128 each have a different slope. It should be understood that the inner wall 122 may have more or less tapered regions without departing from the scope of the present disclosure.

Each of the first tapered region 124, the second tapered region 126, and the third tapered region 128 may generally extend in a direction from the first major surface 110 toward the second major surface 112. While in some embodiments, the tapered region may extend along a line perpendicular to the first and second major surfaces 110, 112, this is not always the case. That is, in some embodiments, the tapered region may extend at an angle relative to the first major surface 110, but generally toward the second major surface 112. Such an angle may be referred to as the slope of a particular tapered region.

The slope of each of the plurality of tapered regions of the inner wall 122 (including the first tapered region 124, the second tapered region 126, and the third tapered region 128) is not limited by this disclosure. That is, each tapered region 124, 126, 128 may have any slope calculated by any image processing software specifically configured to obtain an image of the tapered region 124, 126, 128, extract a contour of the tapered region 124, 126, 128 from the obtained image, and determine the slope at a particular point, points, and/or region based on the contour. One illustrative example of such image processing software may include, but is not limited to, Igor Pro [ wavemeters, Inc., Portland OR, Oregon, U.S.A. ].

More specifically, an image 1400 of the outline 1405 of the via 120 may be obtained, as shown in fig. 14A. To obtain such an image 1400, the substrate 100 (fig. 3A) must be sectioned through the vias 120 in a direction extending between the first and second major surfaces 110, 112 (fig. 3A) such that a cross-section of the vias 120 is visible. Then, an image 1400 of the outline 1405 of the via 120 may be obtained using an optical microscope, a Scanning Electron Microscope (SEM), or the like.

Referring to fig. 14A and 14B, a region of interest 1410 (indicated by a dashed box) may be selected. In some embodiments, the region of interest 1410 may include the entire via 120. In other embodiments, the region of interest 1410 may only contain a portion of the via 120. For example, if the via 120 is a symmetric via, only half of the via 120 may be selected as the region of interest 1410 (e.g., the portion of the via 120 that extends from the first major surface 110 to the plane P, as shown in fig. 3A). After selecting the region of interest 1410, the inner wall 122 of the via 120 (including the respective tapered regions 124, 126, 128) can be electronically traced using computer software to obtain a trace 1415. Trace 1415 may be drawn over image 1400 of profile 1405 such that the profile of trace 1415 corresponds to the profile of inner wall 122 of via 120 in image 1400. Such a drawing containing trace 1415 can be accomplished using standard edge detection techniques available from commercially available data/image processing software, as described in more detail herein.

The traces 1415 may then be analyzed to determine the slope of one or more portions of the inner wall 122, including the respective tapered regions 124, 126, 128. For example, as shown in fig. 15A, trace 1415 is graphically depicted and the computer software described herein is used to determine one or more straight regions of trace 1415. The straight regions are defined as follows: (1) the length of this region is not less than 5 μm and may be generally greater than 10 μm; (2) fitting the region to a linear function using a least squares fitting method (y ═ a + bx), where x is the depth (distance from the surface) and y is the radius of the via at depth x, where the absolute value of the least squares fit residual is less than 1 μm (as shown in the corresponding graph in fig. 15B, where the residual is the difference between the actual radius (y) at a given depth (x) and the fitted radius (y) at the given depth (x)); (3) the slopes of the fit function for any adjacent regions should differ by at least 0.01, which means that the cone angle varies by 0.57 degrees. The region satisfying all of the above criteria (1), (2), and (3) is referred to as a region having a constant slope. As shown in fig. 15A, trace 1415 has four distinct straight regions: the region between points a and B, the region between points C and D, the region between points E and F, and the region between points G and H. Thus, the slopes of the regions between the points a and B, between the points C and D, between the points E and F, and between the points G and H are constant. Additionally, as described in more detail herein, the regions of trace 1415 between points B and C, between points D and E, and between points F and G may be transition regions between regions of constant slope.

Referring again to fig. 3A, in some embodiments, the slope of each tapered region may be an angle relative to a particular axis at a particular point. For example, in some embodiments, the slope may be an angle relative to an axis substantially parallel to the first and/or second major surfaces 110, 112. In other embodiments, the slope of each tapered region may be an angle relative to an axis substantially perpendicular to first major surface 110 and/or second major surface 112. In some embodiments, the slope of each tapered region can be expressed as a ratio relative to an axis perpendicular and parallel to first major surface 110 and/or second major surface 112. For example, the slope of a particular tapered region may be expressed as a 3:1 ratio, which generally means that the slope is the hypotenuse of a right triangle having a first right-angled edge extending 3 units in a first direction perpendicular to first major surface 110 and/or second major surface 112 and a second right-angled edge extending one unit in a second direction parallel to first major surface 110 and/or second major surface 112. Exemplary slopes of the tapered regions (including the first tapered region 124, the second tapered region 126, and the third tapered region 128) may be from about 3:1 to about 100:1, including about 3:1, about 4:1, about 5:1, about 6:1, about 7:1, about 8:1, about 9:1, about 10:1, about 20:1, about 30:1, about 40:1, about 50:1, about 60:1, about 70:1, about 80:1, about 90:1, about 100:1, or any value or range between any two of these values, including endpoints.

In various embodiments, a transition zone may occur between the slopes of each tapered region at any instance where the constant slope region of the inner wall 122 ends. Examples of transition zones are the areas on trace 1415 between points B and C, points D and E, and points F and G. In some embodiments, the slope of the transition region varies by greater than or equal to about 0.57 degrees, greater than or equal to about 1 degree, greater than or equal to about 2 degrees, greater than or equal to about 3 degrees, greater than or equal to about 4 degrees, or greater than or equal to about 5 degrees relative to the slope of the constant slope region. For example, as shown in FIG. 3B, the transition from the slope of the second tapered region 126 to the slope of the third tapered region 128 may occur at a point where the slope of the tangent 155 to the inner wall 122 changes at least 0.57 degrees from the constant slope of the second tapered region 126. The position of this point can be determined generally with the image processing software described above as follows: successive points on the inner wall 122 are traversed in a direction away from one of the tapered regions, each successive point is measured, and it is determined whether each successive point changes by at least 0.57 degrees relative to the slope of the tapered region preceding the particular successive point. In some embodiments, such a transition zone may be bounded by a particular point 150. In other embodiments, such a transition region may be an extended region. That is, the transition region is gradual such that the transition between the slope of the second tapered region 126 to the slope of the third tapered region 128 does not occur at a particular point, but rather occurs in a region where the average slope of the inner wall 122 within the transition region changes by greater than or equal to about 0.57 degrees relative to the second tapered region 126 and the third tapered region 128.

In some embodiments, the transition between tapered regions may be significant, as shown in fig. 3A, 3C, 3F, and 3G. That is, the transition zone may be a particular point 150 (fig. 3B) or a region of relatively short length, making it easier to discern where each tapered region begins and ends relative to the other tapered regions. In other embodiments, the transition between tapered regions may be larger, as shown in fig. 3D and 3E, such that the slope of the inner wall 122 appears to change continuously, and it may be more difficult to discern where each tapered region begins and ends relative to the other tapered regions. For example, as shown in fig. 3D, the transition between the slopes of the first tapered region 124 and the second tapered region 126 may be longer relative to the transition between the slopes of the first tapered region 124 and the second tapered region 126 shown in fig. 3A.

The length of each tapered region may vary and is generally not limited by the present disclosure. The length of each tapered region may be based on the number of tapered regions, the distance between first major surface 110 and second major surface 112, the slope of each tapered region, the size of the transition between tapered regions, and the like. The length of each particular region may be based on the endpoints of each particular region, as described in more detail herein. For example, first tapered region 124 may have a first endpoint at the intersection of inner wall 122 and first major surface 110 and a second endpoint, which is a point on inner wall 122 at which the constant slope of inner wall 122 ends, e.g., the slope varies by at least 0.57 degrees relative to the slope of first tapered region 124. Similarly, the second tapered region 126 may extend from the intersection with the first tapered region 124 toward the second major surface 112. It should be understood that the length as used herein with respect to the various tapered regions (including the total length of all tapered regions combined) refers to the length of the inner wall 122 that is spanned along the boundary line/contour of the inner wall 122 from the beginning to the end.

In some embodiments, the length of a particular tapered region (including first tapered region 124, second tapered region 126, and/or third tapered region 128) may be about 15 microns to about 360 microns, including about 15 microns, about 25 microns, about 50 microns, about 75 microns, about 100 microns, about 150 microns, about 200 microns, about 250 microns, about 300 microns, about 350 microns, about 360 microns, or any value or range between any two of these values (including endpoints).

The vias 120 may be symmetric or asymmetric about a plane P that is located between the first and second major surfaces 110, 112 and that is equidistant between the first and second major surfaces 110, 112 (e.g., at half height of the first and second major surfaces 110, 112). Additionally, the plane P can be further substantially parallel to the first and second major surfaces 110, 112.

When the vias 120 are symmetrical about the plane P, the respective tapered regions of the inner wall 122 in the first portion 130 between the plane P and the first major surface 110 may be mirror images of the respective tapered regions of the inner wall 122 in the second portion 140 between the plane P and the second major surface 112. That is, at any given distance relative to plane P in the first portion 130, the diameter of the via 120 will be substantially equal to the diameter of the via 120 at the corresponding distance relative to plane P in the second portion 140. For example, as shown in fig. 3A and 3D, a first diameter D of the via 120 at the opening of the via 120 on the first major surface 110 in the first portion 130₁Is substantially equal to the second diameter D of the via 120 at the opening of the via 120 on the second main surface 112₂. As used herein with respect to symmetrical shapes, the term "substantially equal" refers to equal diameters within tolerance limits. Tolerance limits canLess than or equal to 3 microns, less than or equal to about 2 microns, less than or equal to 1 micron, less than or equal to about 0.5 microns, less than or equal to about 0.25 microns, less than or equal to about 0.1 microns, or equal to about 0 microns.

In contrast, as shown in fig. 3C, 3E and 3F, when the further via 120' is asymmetric about the plane P, the tapered regions of the inner wall 122 in the first portion 130 are not mirror images of the tapered regions of the inner wall 122 in the second portion 140. That is, as shown in fig. 3C, 3E and 3F, the first diameter D of the via 120' at any given location on the first portion 130₁Is not equal to the second diameter D of the via 120' at the corresponding location in the second portion 140₂. As particularly shown in the blind hole of fig. 3G, the via 120' is asymmetric in that the first portion 130 on one side of the plane P is not a mirror image of the second portion 140 below the plane P. Furthermore, the via 120' does not comprise an opening on the second main surface 112 due to being a blind hole. Rather, the via 120' contains an opening only on the first major surface 110.

As shown in fig. 4, the via 120 may have a particular waist diameter W at the plane P. In some embodiments, the waist diameter W may be greater than or equal to the first diameter D₁And about 80% of the largest of the second diameters (not shown). In other embodiments, the waist diameter W may be at the first diameter D₁And about 20% to about 100% of the largest of the second diameters. In other embodiments, the waist diameter W may be the first diameter D₁And about 85% of the largest of the second diameters, the first diameter D₁And about 90% of the largest of the second diameters, the first diameter D₁And 30% to about 100% of the largest of the second diameters, the first diameter D₁And about 40% to about 100% of the largest of the second diameters, the first diameter D₁And about 50% to about 100% of the largest of the second diameters, the first diameter D₁And about 60% to about 100% of the largest of the second diameters, the first diameter D₁And about 70% to about 100% of the largest of the second diameters, the first diameter D₁And about 80% to about 100% of the largest of the second diameters, the first diameter D₁And about 90 of the largest of the second diameters% to about 100%. In some embodiments, the waist diameter may be about 5 microns to about 200 microns, including about 5 microns, about 10 microns, about 25 microns, about 50 microns, about 100 microns, about 200 microns, or any value or range between any two of these values (including endpoints).

Fig. 5A depicts an illustrative method of forming a glass-based substrate including at least one symmetrical tapered via in accordance with one or more embodiments. The steps shown in fig. 5A are merely exemplary, and steps may be eliminated or additional steps included. In some embodiments, a glass-based substrate formed by the method described in connection with fig. 5A may include a through-hole having an inner wall with a plurality of tapered regions and a cross-section that is symmetrical with respect to a plane, as described in more detail herein.

In step 505, a planar glass-based substrate may be provided. As described herein, the glass-based substrate may generally be any glass-based substrate suitable for creating vias therethrough. The glass-based substrate can have any suitable thickness and/or shape, such as a wafer 0.7 millimeters (mm) thick and 150mm in diameter.

In step 510, one or more laser damage regions or guide holes may be formed in the glass-based substrate. The laser damaged regions create damaged regions within the substrate 100 that etch at a faster etch rate when an etching solution is applied than the undamaged regions. The one or more damage tracks may be formed via a line focused laser, such as described in U.S. patent publication No. 2015/0166395, which is incorporated herein by reference in its entirety. However, the present disclosure is not limited to such lasers, and one or more damage tracks may be formed with other lasers without departing from the scope of the present disclosure. The energy density of the laser (e.g., the energy delivered to the glass-based substrate) may be selected such that it is above the damage threshold along at least a portion of the glass-based substrate (e.g., along the entire width of the glass-based substrate if a glass via is desired) and along the entire axis of the laser. In embodiments where blind vias are desired, forming one or more damage tracks may include forming a first set of damage tracks on the first major surface of the substrate and forming a second set of damage tracks on the second major surface such that energy delivered to the glass-based substrate is above a damage threshold of the first set of damage tracks and below a damage threshold of the second set of damage tracks. Other means of forming one or more damage tracks on a glass-based substrate are generally understood and intended to be included within the scope of the present disclosure.

Forming the damage tracks may include any forming technique, and the present disclosure is not limited to any particular technique. Exemplary formation techniques may include, but are not limited to, mechanical drilling, etching, laser ablation, laser assisted processes, laser damage and etching processes, sand blasting, abrasive water jet machining, focused electrical thermal energy, or any other suitable formation technique.

In step 515, at least a portion of the via is formed, for example, by placing in an etchant bath (e.g., a first etchant bath), exposing the glass-based substrate to the etchant, and etching at a particular etch rate (e.g., a first etch rate) to remove the laser damage region and/or enlarge the pilot hole. In other embodiments, exposure to the etchant may be accomplished by any conventional means, including but not limited to spraying or applying an etchant cream with the etchant. The first etchant may be, for example, an acid etchant or a base etchant. Illustrative examples of acid etchants include, but are not limited to, those containing an amount of nitric acid (HNO)₃) An etchant containing hydrofluoric acid (HF), and/or the like. Illustrative examples of alkaline etchants include, but are not limited to, alkaline etchants such as sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH)₄OH), and the like. In some embodiments, the first etchant bath may be a static (e.g., unstirred) bath of about 9.8% (w/w) aqueous hydrofluoric acid. However, other etchant baths now known or later developed may also be used without departing from the scope of the present disclosure. The first etch rate is similarly not limited by the present disclosure and can be any etch rate. In some embodiments, the first etch rate can be from about 2.8 nanometers per minute (nm/min) to about 3.2nm/min, including about 2.8nm/min, about 2.9nm/min,about 3.0nm/min, about 3.1nm/min, about 3.2nm/min, or any value or range between any two of these values (including endpoints). In a particular embodiment, the first etch rate may be about 3 nm/min. In some embodiments, step 515 may create a first tapered region of the via, as described in more detail herein.

After a period of time has elapsed and/or after a specific amount of glass-based substrate has been removed, the glass-based substrate may be removed from the etchant (e.g., etchant bath) in step 520. In some embodiments, a particular amount of time can be, for example, about 5 minutes to about 120 minutes, including about 5 minutes, about 15 minutes, about 30 minutes, about 60 minutes, about 120 minutes, or any value or range between any two of these values (including endpoints). In particular embodiments, the particular amount of time may be about 75 minutes. In another particular embodiment, the particular amount of time may be about 14 minutes. Other times may be contemplated without departing from the scope of the present disclosure. In some embodiments, the particular amount of the glass-based substrate removed from one of the first major surface and the second major surface measured can be, for example, about 10 microns of material to about 200 microns of material, including 10 microns of material, about 50 microns of material, about 100 microns of material, about 150 microns of material, about 200 microns of material, or any value or range between any two of these values (including endpoints). In particular embodiments, it is measured that about 42 microns or about 180 microns of material can be removed from one of the first major surface and the second major surface.

In step 525, the etchant material may be washed from the glass-based substrate. In some embodiments, the glass-based substrate can be rinsed with a solution containing hydrochloric acid (HCl), such as a 0.5M HCl solution. In some embodiments, the glass-based substrate may be rinsed with deionized water. In some embodiments, the glass-based substrate may be rinsed with a first rinse solution and then rinsed with a second rinse solution. For example, the glass-based substrate may be rinsed with a 0.5M HCl solution and then rinsed with a deionized water solution. In some embodiments, the glass-based substrate may be rinsed for a specific time to ensure that all etchant material has been removed and/or to separate all wafer material removed from the etchant, e.g., for about 10 minutes. In a particular embodiment, the glass-based substrate may be rinsed in a 0.5M HCl solution for 10 minutes, followed by a 10 minute rinse with deionized water.

In step 535, the glass-based substrate is exposed to an etchant, such as an etchant bath (e.g., a second etchant bath), and etched at a particular etch rate (e.g., a second etch rate). In other embodiments, exposure to the etchant may be accomplished by any conventional means, including but not limited to spraying or applying an etchant cream with the etchant. The second etchant may be, for example, an acid etchant or a base etchant. The second etchant may generally have a different concentration than the first etchant. For example, the first etchant may have a higher concentration of acid or base etchant than the second etchant, as described above. In other embodiments, the first etchant may have a lower concentration of acid or base etchant than the second etchant. In particular embodiments, the second etchant bath may be a 6M NaOH solution. However, other etchants now known or later developed may also be used without departing from the scope of this disclosure. The second etch rate is similarly not limited by the present disclosure and may be any etch rate. In a particular embodiment, the second etch rate may be about 30 nm/min. In some embodiments, the first etch rate, as described above, may be greater than the second etch rate. In other embodiments, the first etch rate may be less than the second etch rate. In some embodiments, step 535 can create a second tapered region of the via, as described in more detail herein.

After a period of time has elapsed and/or after a particular number of glass-based substrates have been removed, the glass-based substrates may be removed from the etchant (e.g., etchant bath) in step 540. In some embodiments, the particular amount of time may be, for example, about 3 days. In other embodiments, the particular amount of time may be about 6 hours. Other times may be contemplated without departing from the scope of the present disclosure. In some embodiments, the particular amount of glass-based substrate that is removed, as measured from one of the first major surface and the second major surface, may be, for example, about 65 microns of material.

The etchant may have one or more other characteristics not specifically described herein. For example, in some embodiments, the etchant bath may be maintained at a particular temperature. One such exemplary temperature is about 85 ℃.

In step 545, the glass-based substrate may be rinsed to remove the etchant material. For example, the glass-based substrate may be rinsed with deionized water. The resulting glass-based substrate includes at least one symmetric via having one or more geometric features. For example, the resulting via may have a diameter of about 100 microns at the first and second major surfaces, a waist diameter of about 40 microns, and an inner wall having a first tapered region extending from the first major surface toward the second major surface at a 3:1 taper of about 115 microns and a second tapered region extending between its intersection with the first tapered region and the center of the substrate at a 30:1 taper.

To create additional tapered regions, for example, as shown in FIG. 5B, the process described in connection with steps 535-545 may be repeated for each additional tapered region. It is to be understood that altering one or more characteristics of the etchant bath and/or altering the etch rate may result in additional tapered regions having particular characteristics.

Example 1 below describes a specific example of a via created using the steps described herein in connection with fig. 5A:

example 1

A glass via having a symmetrical segmented taper can be formed by the following steps.

Initially a 1064nm picosecond laser was used to form damage tracks in a 0.7 mm thick, 150mm diameter glass-based wafer. The energy density is selected to be above the damage threshold of the glass-based wafer along the entire axis of the laser.

The wafer was placed in a static water bath of 9.8% (w/w) hydrofluoric acid in water for 75 minutes (about 180 microns removed). The etch rate of this process is about 3 (e.g., 2.8-3.2).

The wafers were then rinsed in 0.5M HCl for 10 minutes and then in deionized water for 10 minutes.

The wafers were then immersed in a 6M sodium hydroxide bath at 85 ℃ for 3 days (about 65 microns removed). The etch rate for this process is about 30.

The process support is then removed from the alkaline bath and rinsed with copious amounts of deionized water.

This resulted in the via opening on the substrate with an entrance diameter of 100 microns, a waist diameter of 40 microns, a taper of 3:1 deep 115 microns from the surface and a taper of 30:1 for the remaining distance to the center of the substrate.

In some embodiments, at least a portion of the process described with reference to fig. 5A may also be used to create blind vias. Example 2 below describes such an illustrative process: