阅读说明：本技术 对接接触结构 (Butt contact structure ) 是由 徐永昌 潘昇良 于 2019-07-10 设计创作，主要内容包括：提供一种对接接触结构。在一实施例中,结构包含位于基底上的第一晶体管,第一晶体管包含第一源极或漏极区域、第一栅极、以及设置于第一栅极和第一源极或漏极区域之间的第一栅极间隔物。此结构包含位于基底上的第二晶体管,第二晶体管包含第二源极或漏极区域、第二栅极、以及设置于第二栅极和第二源极或漏极区域之间的第二栅极间隔物。此结构包含对接接触件,设置于第一源极或漏极区域上方并从第一源极或漏极区域延伸至第一栅极或第二栅极的至少之一,第一栅极间隔物的一部分延伸一距离至对接接触件中以隔开对接接触件的第一底表面与对接接触件的第二底表面。(A mating contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor including a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region. The structure includes a mating contact disposed over and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the mating contact to space a first bottom surface of the mating contact from a second bottom surface of the mating contact.)

1. A butt contact structure comprising:

a first transistor on a substrate, the first transistor including a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region;

a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region; and

a mating contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the mating contact to space a first bottom surface of the mating contact from a second bottom surface of the mating contact.

Technical Field

Embodiments of the present invention relate to semiconductor structures and methods of fabricating the same, and more particularly, to butted contact structures and methods of fabricating the same.

Background

Contacts are typically vertical metal interconnects formed in integrated circuits that connect various components of a semiconductor device, such as active regions and gate electrodes, to interconnect metal layers. The individual semiconductor devices formed in the semiconductor substrate are electrically coupled to each other through contacts to form a functional integrated circuit. As the semiconductor industry has progressed to nanotechnology process nodes, such as the 5 nm node, new challenges have arisen in pursuit of higher device densities. Accordingly, there is a need for improved contact structures and methods.

Disclosure of Invention

According to an embodiment of the present invention, there is provided a mating contact structure, including: a first transistor on the substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region; a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region; and a mating contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the mating contact to space a first bottom surface of the mating contact from a second bottom surface of the mating contact.

According to another embodiment of the present invention, there is provided a mating contact structure, including: a first transistor on the substrate, the first transistor including a source or drain region; a conductive member contacting the source or drain region; a gate electrode of a gate structure of the second transistor on the substrate; a docking contact comprising (i) a first surface contacting the gate electrode, (ii) a second surface contacting the conductive feature, (iii) a third surface extending from the first surface at a first angle, and (iv) a fourth surface extending from the second surface at a second angle, the third surface intersecting the fourth surface at a third angle; and a gate spacer disposed between the source or drain region and the gate structure, a portion of the gate spacer being laterally disposed between the third surface and the fourth surface.

According to another embodiment of the present invention, a method for manufacturing a semiconductor includes: forming a source or drain region on the substrate, a gate on the substrate, and a gate spacer on a side of the gate, wherein the source or drain region has a conductive feature formed thereon, the gate has a first dielectric layer formed thereon, and the gate spacer is laterally disposed between the gate and the source or drain region; depositing a second dielectric layer over the conductive feature, the first dielectric layer, and the gate spacer, wherein the second dielectric layer is different from the first dielectric layer; depositing a first mask layer over the second dielectric layer; depositing a second mask layer over the first mask layer; etching a first contact opening through the second masking layer, the first masking layer, the second dielectric layer, and the first dielectric layer to expose the gate, the etching the first contact opening comprising using a first etch recipe to etch the second masking layer, using the second etch recipe to etch the first masking layer, using a third etch recipe to etch the second dielectric layer, and using a fourth etch recipe to etch the first dielectric layer, wherein the first, second, third, and fourth etch recipes are different from one another; etching a second contact opening through the second masking layer, the first masking layer, and the second dielectric layer to expose the conductive feature, the etching the second contact opening comprising etching the second masking layer using a first etch recipe, etching the first masking layer using a second etch recipe, etching the second dielectric layer using a third etch recipe, the first contact opening and the second contact opening being connected at the gate spacer, and the first etch recipe and the second etch recipe shaping a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material.

Drawings

The embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A depicts an illustrative circuit diagram according to some embodiments.

FIG. 1B depicts a top view schematic diagram of an integrated circuit layout corresponding to a portion of the circuit diagram shown in FIG. 1A.

Fig. 2 depicts a semiconductor device that may be used to form a portion of the circuit diagram shown in fig. 1A, according to some embodiments.

Fig. 3-16, 17A, and 17B are cross-sectional schematic diagrams illustrating a portion of a semiconductor device corresponding to various stages of fabrication, according to some embodiments.

Fig. 18 depicts a portion of the cross-sectional schematic of fig. 17A to further illustrate additional details, according to some embodiments.

Wherein the reference numerals are as follows:

100-SRAM cell

101. 106, 121, 152, 153 to gate

104. 115, 292 source/drain regions

110. 120-pass gate transistor

112. 116, 114, 118 transistors

140-first inverter

142-second inverter

150-integrated circuit layout

154. 155 active region

156. 157-drain region

158. 159-Butt contact

158A, 158B, 159A, 159B, 277, 291:pattern

160. 162 contact

160A, 162A-contact pattern

201 first transistor region

203 to second transistor region

214 silicide region

215. 223, 1702, 1704 to the bottom

220-interface dielectric

222-Gate dielectric layer

224 conformal layer

225. 1814, 1816 to the side wall

226-gate conductive fill material

227-conductive filler

228a, 228 b-replacement gate structure

229. 234, 236, 1801 to the top surface

231-first self-aligned contact

233-second self-aligned contact

235. 237 hard mask layer

238 butt contact opening

239. 261-three layer (mask) structure

240-semiconductor device

241. 263 to bottom layer

243. 265 intermediate layer

245. 267 top layer

246-conductive Material

247-first opening

248-groove

249 to first photomask

250-protective lining

251-grid structure

253-groove

255-first pattern

257-radiation beam

259 first contact opening

269 to second photomask

270 to the substrate

271 second pattern

273 to second opening

274-fin

275. 289 scheme of drawings

278 isolation region

279a, 279b, 279c, 279d, 293a, 293b, 293c, 293 d-part

280-interface dielectric

281 second contact opening

282-dummy gate

284 mask

286-gate spacer

286' to tapered tip

297 to first interlayer dielectric

1800-butt contact structure

1802 left V-shaped section

1804-right V-shaped part

1818-first side wall

1820 to second side wall

A. B, E, F, G-angle

A-A. section

BL-bit line

BLB-complementary bit line

D1, D2, D3, D4, D5 and D6

WL word line

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of embodiments of the invention. Specific examples of components and arrangements are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first feature being formed on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Moreover, embodiments of the present invention may repeat reference numerals and/or letters in the various examples, for purposes of simplicity and clarity, and do not represent a particular relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein to facilitate describing the relationship of element(s) or component(s) to another element(s) or component(s) as shown. These spatially relative terms encompass different orientations of the device in use or during a procedure, and the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

Various embodiments described below provide methods for forming a common contact structure that enables a source or drain region of a transistor to be connected to the gate of the same or another transistor on a substrate without the use of a horizontal metal interconnect layer. A tapered gate spacer is laterally disposed between the source or drain region and the gate. The tapered gate spacers extend a distance between sloped sidewalls inside the common contact structure into the bottom of the common contact structure. The tapered gate spacers and sloped sidewalls may ensure good metal filling capability so that subsequently deposited metal fills are void free or seam free (seams). The common contact structure may be formed by a double patterning process using two separate masks, each mask having a portion of a pattern corresponding to the common contact structure.

The foregoing has outlined broadly some aspects of embodiments of the present invention. The concepts of the embodiments of the present invention are contemplated as being useful in planar transistor devices or in three-dimensional transistor devices such as the semiconductor device 240 described in the embodiments of the present invention. Some example devices that may achieve aspects described herein include fin field effect transistors (finfets), Horizontal Gate All (HGAA) field effect transistors, Vertical Gate All (VGAA) field effect transistors, nanowire channel field effect transistors, strained semiconductor devices, silicon-on-insulator (SOI) devices, or other devices that may benefit from aspects of the present invention.

FIG. 1A shows an example of an illustrative circuit diagram of a 6T (6 transistor) Static Random Access Memory (SRAM) cell 100, according to some embodiments. The 6T sram cell 100 includes a first inverter 140 cross-coupled with a second inverter 142. The first inverter 140 includes a pull-up transistor 112 and a pull-down transistor 114. The second inverter 142 includes a pull-up transistor 116 and a pull-down transistor 118. Sram cell 100 also includes pass gate transistors 110, 120. The gates (e.g., gate 101) of pass-gate transistors 110, 120 are coupled to and controlled by a word line WL, and the sources/drains of pass-gate transistors 110, 120 are coupled to a bit line BL and a complementary bit line BLB, respectively.

Common contacts or so-called butted contacts may be used for the various connections in the circuit diagram of fig. 1A. For example, the connection between the source/drain region 104 of the pull-up transistor 112 and the gates 106 of the pull-up and pull-down transistors 116 and 118, and the connection between the source/drain region 115 of the pull-up transistor 116 and the gates 121 of the pull-up and pull-down transistors 112 and 114. Other connections may be formed by mating contacts.

FIG. 1B illustrates a top view of an Integrated Circuit (IC) layout 150 corresponding to a portion of the SRAM cell 100 shown in FIG. 1A. The integrated circuit layout 150 includes two pull-up transistors 112 and 116. For clarity, pull-up transistor 112 is represented by components having dashed lines, and pull-up transistor 116 is represented by components having solid lines. Pull-up transistor 112 includes a gate 152 formed over a portion of an active region 154, and pull-up transistor 116 includes a gate 153 formed over a portion of an active region 155. The gates 152 and 153 may comprise a metal-containing species, as described below. Each pull-up transistor (112, 116) includes a drain region 156, 157 within an active region 154 and 155, respectively. The mating contacts 158, 159 may extend along a length from a first end to a second end. For example, a first end of the mating contact 158 may contact the gate 152, the gate 152 corresponding to the pull-up transistor 112 within a first inverter (e.g., the first inverter 140 of fig. 1A). A second end of the mating contact 158 contacts a drain region 157, the drain region 157 corresponding to the pull-up transistor 116 within a second inverter (e.g., the second inverter 142 of fig. 1A). Thus, the butting contact connects the gate of the transistor in one inverter to the source/drain of the transistor in a cross-coupled inverter, as shown in SRAM cell 100. Integrated circuit layout 150 also includes contacts 160 and 162. Contacts 160 and 162 may be any suitable internal connection or contact features desired in semiconductor device 240. For example, contacts 160 and 162 may be disposed on the active regions 154, 155, respectively, and may be configured to provide a voltage Vcc to source terminals (terminations) of the pull-up transistors 112 and 116, respectively.

It is contemplated that the transistors and contact features depicted in fig. 1B are for illustrative purposes and should not be considered limiting. The configuration and/or number of transistors and contact members may vary depending on the application. Other applications of common or abutting contacts include other memory applications, power devices, and any other semiconductor, where adjacent elements may be electrically connected at the transistor level. For example, although embodiments of the present invention discuss gate-to-drain mating contacts, other mating contacts are also contemplated, such as source-to-drain of adjacent transistors, gate-to-source, source-to-body (body), drain-to-body, and other mating contacts of adjacent transistors.

Some embodiments use multiple patterning techniques to form the mating contact, such as a double patterning process. For example, a rectangular pattern corresponding to a mating contact (e.g., mating contact 158 of fig. 1B) may be split (split) or into two square patterns 158A and 158B. The two square patterns 158A, 158B are then recombined in successive lithography and etching steps using two separate reticles to form a rectangular butt contact 158 that is to be transferred into the film layer of the device. Because the square patterns 158A and 158B are transferred into the layers of the device by two separate lithography processes, proper critical dimension uniformity may be achieved. By splitting the layout into two different reticles, the minimum line spacing (line spacing) in the combined pattern can be reduced while maintaining good resolution (resolution). In some embodiments, each reticle may also contain a pattern of nominal (nominal) contacts to be transferred to the substrate to ensure that a minimum number of reticles are involved. For example, the first mask may include a square pattern 158A of the mating contact 158, a square pattern 159A of the mating contact 159, and a contact pattern 162A to be formed on the active region 155, while the second mask may include a square pattern 158B of the mating contact 158, a square pattern 159B of the mating contact 159, and a contact pattern 160A to be formed on the active region 154. Various embodiments of forming the mating contact will be discussed in more detail below.

Fig. 2 illustrates a semiconductor device 240, such as a landing contact, that may be used to form a portion of the sram cell 100 of fig. 1A, that provides a connection between the gates 106 of transistors 116 and 118 and the drain 104 of transistor 112, or between the gates 121 of transistors 112, 114 and the drain 115 of transistor 116. The semiconductor device 240 has a fin 274 formed on a semiconductor substrate 270. The semiconductor substrate 270 may be or may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 270 may comprise an elemental semiconductor comprising silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination of the foregoing. Fin 274 provides an active region for one or more transistors of sram cell 100. The fins 274 may be fabricated by suitable processes, including masking, photolithography and/or etching processes, performed on the semiconductor substrate 270 to form the trenches 253 in the substrate 270, leaving the fins 274 extending upwardly from the substrate 270. The trench 253 can then be filled with an insulating material, such as an oxide (e.g., silicon oxide), nitride, similar materials, or a combination of the foregoing. The insulating material may be recessed to form isolation regions 278, for example by using a suitable etch process. The insulating material is recessed such that the fins 274 protrude between adjacent isolation regions 278 and above adjacent isolation regions 278.

The semiconductor device 240 has a gate structure 251 formed over a top surface of the fin 274. As described herein, the gate structure 251 replaces the dummy gate stack in a gate process (replacement gate process), but other examples contemplate implementing a gate-first process. The gate structure 251 is located over the fin 274 and extends perpendicular to the fin 274. Each gate structure 251 includes an interface dielectric 280, a dummy gate 282 over the interface dielectric 280, and a mask 284 over the dummy gate 282, as shown in fig. 2. Various film layers of interface dielectric 280, dummy gate 282, and mask 284 for gate structure 251 may be formed sequentially and then patterned into gate structure 251. For example, the interfacial dielectric 280 may comprise or may be silicon oxide, silicon nitride, similar materials, or a multilayer structure as described above. Dummy gate 282 may comprise or may be silicon (e.g., polysilicon) or other material. The mask 284 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, similar materials, or combinations thereof. These film layers may be formed or deposited by any suitable deposition technique. The film layers for the interface dielectric 280, the dummy gate 282, and the mask 284 may then be patterned using, for example, photolithography and one or more etching processes to form the interface dielectric 280, the dummy gate 282, and the mask 284 for each gate structure 251.

The semiconductor device 240 also includes source/drain regions 292 disposed in opposing regions of the fin 274 relative to the gate structure 251. One of the source/drain regions 292 and the gate structure 251 (or a corresponding replacement gate structure subsequently formed) defines at least a first transistor in the first transistor region 201. The expression "source/drain" as used in embodiments of the present invention is used to denote a source or drain region of a transistor, such as a first transistor in the first transistor region 201. The first transistor in the first transistor region 201 can be, for example, a pull-up transistor, such as pull-up transistor 112 of fig. 1B. The other gate structure 251 (or a corresponding replacement gate structure subsequently formed) is part of a second transistor in the second transistor region 203, and the second transistor may be, for example, a pull-up transistor, such as pull-up transistor 116 of fig. 1B. Fig. 2 further shows the reference profile used in subsequent figures. Section a-a lies along a plane that follows the channel in the fin 274 between, for example, opposing source/drain regions 292. For clarity, the subsequent figures refer to this reference section.

Fig. 3 illustrates the formation of gate spacers 286 along the sidewalls of the gate structure 251 (e.g., sidewalls of the interface dielectric 280, the dummy gate 282, and the mask 284) and over the fins 274. For example, the gate spacer 286 may be formed by conformally depositing one or more layers for the gate spacer 286 and anisotropically etching the one or more layers. The material for one or more layers of gate spacer 286 may be different than the material for gate structure 251. In some embodiments, the gate spacers 286 may comprise or be a dielectric material, such as silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, similar materials, a multi-layer structure of the foregoing, or a combination of the foregoing, and the gate spacers 286 may be deposited by any suitable deposition technique. An anisotropic etch process is then performed to remove portions of the spacer layer to form the gate spacers 286.

Fig. 4 illustrates the formation of epitaxial source/drain regions 292 in the recesses in the fins 274. Recesses are formed in the fins 274 on opposite sides of the gate structure 251. The recess etching may be performed by an etching process. The etch process may be isotropic (isotropic) or anisotropic, or further, may be selective to one or more crystal planes (crystalloneplanes) of the substrate 270. Thus, the recess may have various cross-sectional profiles depending on the etch process performed.

Epitaxial source/drain regions 292 are epitaxially grown in the recesses. The material of the epitaxial source/drain regions 292 may be selected to comprise or be silicon germanium, silicon carbide, silicon phosphorous, silicon carbon phosphorous, germanium, group III-V compound semiconductors, group II-VI compound semiconductors, or similar materials depending on the conductivity type of the transistor. The epitaxial source/drain regions 292 may be raised relative to the fins 274 and may have facets (facets) that may correspond to the crystal plane of the semiconductor substrate 270 and the orientation of the fins 274 relative to the crystal plane of the substrate. In some examples, the epitaxial source/drain regions 292 may also be doped, for example, by in-situ (in situ) doping during epitaxial growth and/or by implanting dopants into the epitaxial source/drain regions 292 after epitaxial growth.

Fig. 5 illustrates the formation of a first interlayer dielectric (ILD) 297 and subsequent planarization. A first interlayer dielectric 297 is formed over the exposed surfaces of source/drain regions 292, the sidewalls and top surface of gate spacers 286, the top surface of mask 284, and the top surface of isolation region 278 using any suitable deposition technique. An optional Contact Etch Stop Layer (CESL) (not shown) may be deposited between the first interlayer dielectric 297 and the surface of the source/drain regions 292 and the sidewalls of the gate spacers 286. The first interlayer dielectric 297 may comprise or be Tetraethoxysilane (TEOS) oxide, silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant less than that of silicon dioxide), or the like. The contact etch stop layer may comprise or may be silicon nitride, silicon carbonitride, carbon nitride, similar materials, or combinations of the foregoing. A planarization process, such as Chemical Mechanical Planarization (CMP), removes the first interlayer dielectric 297 until the top surface of the dummy gate 282 is exposed, which also removes the mask 284.

Fig. 6 illustrates removing the remaining gate structure 251 and forming replacement gate structures 228a, 228 b. The gate structure 251 is removed using one or more etching processes. After removing gate structure 251, a recess is formed between gate spacers 286 where the gate stack is removed, and the channel region of fin 274 is exposed through the recess. Next, replacement gate structures 228a, 228b are formed in the recesses from which the gate structure 251 was removed. Each replacement gate structure 228a, 228b may include an interfacial dielectric 220, a gate dielectric layer 222, one or more optional conformal layers 224, and a gate conductive fill material 226. The replacement gate structures 228a, 228b may have a thickness of between about 8 nm and about 25 nm, such as between about 12 nm and about 20 nm.

An interfacial dielectric 220 is formed on the top surface of the fin 274 along the channel region. The interfacial dielectric 220 may be an oxide (e.g., silicon oxide) formed by thermal or chemical oxidation of the fins 274.

Gate dielectric layer 222 may be conformally deposited in the recess created by the removal of the gate stack (e.g., on interface dielectric 220 and on the sidewalls of gate spacer 286) and on the top surfaces of first interlayer dielectric 297 and gate spacer 286. The gate dielectric layer 222 may be or may include silicon oxide, silicon nitride, high dielectric constant (high-k) dielectric materials, multi-layer structures as described above, or other dielectric materials. The high-k dielectric material may have a dielectric constant value greater than about 7.0 and may comprise a metal oxide or metal silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), a multi-layer structure of the foregoing, or a combination of the foregoing.

One or more optional conformal layers 224 may be conformally deposited over the gate dielectric layer 222. The one or more optional conformal layers 224 may include one or more barrier layers and/or cap layers and one or more work-function tuning layers (work-function tuning layers). The one or more barrier layers and/or cap layers may comprise tantalum nitride, titanium nitride, similar materials, or combinations thereof. The one or more work function adjusting layers may include or may be aluminum titanium carbide, aluminum titanium oxide, aluminum titanium nitride, similar materials, or combinations of the foregoing. The materials for the one or more work function adjusting layers, barrier layers, and/or cap layers may be selected to achieve a desired threshold voltage (Vt) for a transistor, which may be a p-type field effect transistor (pFET) or an n-type field effect transistor (nFET). A gate conductive fill material 226 is formed over the one or more conformal layers 224 (if implemented) and/or the gate dielectric layer 222. The gate conductive fill material 226 may fill the recess left by the removal of the gate stack. The gate conductive fill material 226 may be or may include a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, a multi-layer structure thereof, combinations thereof, or the like.

A planarization process, such as chemical mechanical planarization, may remove the film for the gate conductive fill material 226, the one or more conformal layers 224, and the portion of the gate dielectric layer 222 that is over the top surfaces of the first interlayer dielectric 297 and the gate spacers 286. Accordingly, replacement gate structures 228a, 228b comprising a gate conductive fill material 226, one or more conformal layers 224, a gate dielectric layer 222, and an interfacial dielectric 220 as illustrated in fig. 6 may be formed.

Fig. 7 illustrates the formation of a first self-aligned contact (SAC) 231 on each replacement gate structure 228a, 228b and the formation of conductive features to the epitaxial source/drain regions 292. After forming the replacement gate structures 228a, 228b, portions of the replacement gate structures 228a, 228b, such as the top of the gate dielectric layer 222, the one or more conformal layers 224, and the gate conductive fill material 226, are removed using one or more etch processes. After removing the top of the replacement gate structures 228a, 228b, recesses are formed between the gate spacers 286. Next, each first self-aligned contact 231 is formed in a recess at the top of the gate dielectric layer 222, the one or more conformal layers 224, and the gate conductive fill material 226 removed. The first self-aligned contact 231 protects the replacement gate structures 228a, 228b during formation of subsequent openings configured to receive (accmod) mating contacts, respectively, for subsequent electrical connection to the source/drain regions 292. The first self-aligned contact 231 may comprise or may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, any suitable dielectric material, or any combination of the foregoing. In some embodiments, the first self-aligned contact 231 is silicon oxycarbonitride. The first self-aligned contact 231 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), any suitable deposition technique or combination of the foregoing, and subsequent planarization (e.g., chemical mechanical planarization).

After forming the first self-aligned contacts 231, source/drain contact openings are formed through the first interlayer dielectric 297 to the source/drain regions 292 to expose at least portions of the source/drain regions 292. Next, a conductive feature is formed in the source/drain contact opening. The conductive features may include silicide regions 214 formed on the source/drain regions 292 and conductive material 246 formed over the silicide regions 214. The first interlayer dielectric 297 may be patterned using openings, for example, using photolithography and one or more etching processes, such as dry etching or any suitable anisotropic etching process. Although not shown, each conductive material 246 can comprise, for example, an adhesion layer conformally deposited in the source/drain contact openings and over the first interlayer dielectric 297, a barrier layer conformally deposited on the adhesion layer, and a conductive fill material deposited on the barrier layer. The silicide regions 214 may be formed by thermally reacting the upper portions of the source/drain regions 292 with an adhesion layer, which may be titanium, tantalum, or the like. The barrier layer may be or may comprise titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, any suitable transition metal nitride or oxide, similar materials, or any combination of the foregoing. The conductive fill material may be or may contain cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys of the foregoing, similar materials, or combinations of the foregoing. After depositing the conductive fill material, excess conductive fill material, barrier layer, and adhesion layer may be removed by using a planarization process (e.g., chemical mechanical planarization). Thus, the top surfaces of conductive material 246 and first interlayer dielectric 297 may be coplanar.

Fig. 8 shows that conductive material 246 is etched back, thereby forming recesses 248. The etch back may comprise using one or more etch processes that are selective to the conductive material 246. The recess 248 is formed such that the top surface of the conductive material 246 is below the top surfaces of the first interlayer dielectric 297, the first self-aligned contact 231, and the gate spacer 286.

Fig. 9 illustrates the formation of a protective liner 250. After forming the recess 248, a protective liner 250 is conformally deposited in the recess 248 (e.g., on the exposed surfaces of the first interlayer dielectric 297 and the conductive material 246) and on the top surfaces of the first interlayer dielectric 297, the first self-aligned contacts 231, and the gate spacers 286. The protective liner 250 may prevent device components thereunder from being damaged during etching of the contact openings. In some embodiments, the protective liner 250 may be formed of a material having a relatively high etch selectivity (as compared to the gate spacers 286). For example, the protective liner 250 may be a dielectric that may include or may be aluminum oxide (AlO)_x) Aluminum oxynitride (AlON), aluminum nitride (AlN), titanium oxide (TiO)_x) Titanium oxynitride (TiON), titanium nitride (TiN), and the like. In one example, the protective liner 250 is aluminum oxynitride (AlON). Can be used forThe protective liner 250 is deposited by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or any suitable deposition technique.

Fig. 10 illustrates the formation of second self-aligned contacts 233. After forming the protective liner 250, a second self-aligned contact 233 is formed over the protective liner 250. The second self-aligned contact 233 may be formed of a different material than the first self-aligned contact 231. The second self-aligned contacts 233 may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, any suitable dielectric material, or any combination of the foregoing. In some embodiments, the second self-aligned contact 233 is silicon nitride. The second self-aligned contact 233 can be formed by chemical vapor deposition, physical vapor deposition, any suitable deposition technique, or a combination of the foregoing. If desired, a planarization process, such as chemical mechanical planarization, may be used to planarize the top surface of the second self-aligned contact 233.

FIG. 10 further illustrates the sequential formation of a first hard mask layer 235, a second hard mask layer 237, and a trilayer mask structure 239 over the second self-aligned contact 233. The first hard mask layer 235 and the second hard mask layer 237 are configured to provide etch selectivity with respect to the second self-aligned contact 233 and the first hard mask layer 235, respectively, during one or more etch processes. The first hard mask layer 235 may be made of a metal compound, such as titanium nitride (TiN), tungsten carbide (WC), tantalum nitride (TaN), tungsten nitride (WN), or other materials. The second hard mask layer 237 may comprise or may be a silicon oxide layer or any suitable oxide material. The first and second hard mask layers 235, 237 may be deposited by any suitable deposition technique, such as physical vapor deposition, chemical vapor deposition, or the like. The trilayer mask structure 239 includes a bottom layer 241, a middle layer 243, and a top layer 245. A three-layer structure (also referred to as a three-layer mask structure) 239 suitable for Deep Ultraviolet (DUV) or Extreme Ultraviolet (EUV) lithography may be selected. The bottom layer 241 may be a bottom anti-reflective coating (BARC) layer, such as a silicon rich oxide (silicon rich oxide) or silicon oxycarbide (SiOC). The intermediate layer 243 may be a silicon-or metal-containing polymer. The top layer 245 may be a radiation sensitive layer, such as a photoresist. The bottom layer 241, the intermediate layer 243, and the top layer 245 may be deposited by any suitable deposition technique, such as physical vapor deposition, chemical vapor deposition, spin-on coating (spin-on coating), or the like.

Fig. 11 illustrates the formation of a first opening 247 through the top 245 and middle 243 layers of the tri-layer mask structure 239 during a first lithographic and etch process. The first opening 247 formed in the top layer 245 is generally aligned with the replacement gate 228 b. A first lithography process is performed by positioning a first mask 249 over the structure of fig. 10. The first mask 249 may be adapted for exposure to deep ultraviolet radiation, such as an ArF excimer laser (193 nm) or a KrF excimer laser (248 nm). The first mask 249 has a first pattern 255 that may be various features such as squares, lines, holes, grids, or any desired shape (e.g., polygons) depending on the features to be formed in the target layer. In some embodiments, the first pattern 255 comprises a square pattern.

Insert 289 in fig. 11 is an enlarged top view schematic diagram illustrating a portion of the pattern 291 of the first mask 249 used to pattern the top layer 245, according to some embodiments. The pattern 291 comprises a plurality of features 293a, 293b, 293c, 293d, which may be lines, squares, grids, or any desired shape (e.g., polygons), depending on the features to be formed in the top layer 245. In some embodiments, the features 293a, 293b, 293c, 293d are square patterns. It is contemplated that the four components and their configuration are shown for illustrative purposes. Depending on the application and the components to be formed in the semiconductor device 240, the components 293a, 293b, 293c, 293d may be repeated on the first mask 249. The members 293a, 293b, 293c, 293d may provide openings for contacts that provide electrical connections to the source/drain regions and/or gates of the semiconductor device 240. For example, the component 293a may be a square pattern corresponding to a portion of the first mating contact (e.g., pattern 158A of mating contact 158, as shown in fig. 1B). The feature 293B may be a square pattern corresponding to a portion of the second mating contact (e.g., the pattern 159A of the mating contact 159, as shown in fig. 1B). Features 293c, 293d may be square patterns corresponding to contact features (e.g., contact pattern 162A as shown in fig. 1B). Features 293a, 293B of first mask 249 and features 279a, 279B from second mask 269 (discussed below in fig. 14) recombine to produce rectangular mating contacts (e.g., mating contacts 158, 159 as shown in fig. 1B) that will be transferred to the target layer (e.g., second self-aligned contacts 233). Depending on the application, the dimensions of the members 293a, 293b, 293c, 293d may range from about 10 nanometers to about 80 nanometers, such as from about 20 nanometers to about 55 nanometers.

First pattern 255 is transferred to top layer 245 by exposing top layer 245 to radiation beam 257 using first reticle 249. The radiation beam 257 may be extreme ultraviolet radiation (e.g., 13.5 nanometers) or deep ultraviolet radiation such as ArF excimer laser (193 nanometers) or KrF excimer laser (248 nanometers). Other suitable radiation, such as electron beams, x-rays, or ion beams, may also be used depending on the masking material. The exposed or unexposed portions of the top layer 245 can then be removed, depending on whether a positive or negative photoresist is used.

The middle layer 243 is then patterned using the patterned top layer 245 as a mask. As a result, the first opening 247 of the top layer 245 is transferred to the middle layer 243. The intermediate layer 243 may be patterned using any suitable process, such as a dry etch process. An exemplary dry etch process may be performed in a dual radio frequency power source (dual RF power source) plasma reactor using a chemistry comprising an inert gas (e.g., argon) and a fluorocarbon gas, such as tetrafluoromethane (CF)₄) Trifluoromethane (trifluoromethane; CHF₃) Hexafluorobutadiene (hexafluorobutadine; c₄F₆) Difluoromethane (difluoromethane; CH (CH)₂F₂) Octafluoropropane (octofluoropropane; c₃F₈) Octafluorocyclobutane (octofluorocyclobutane; c₄F₈) Or any combination of the foregoing. In some embodiments, the chemical comprises CF₄And CHF₃. The chamber pressure of the plasma reactor may be maintained at about 5 millitorr (mTorr) to about 20 mTorr, such as about 10 mTorr.During the dry etch process, a source power (source power) is provided at a first power level and a bias power (bias power) is provided at a second power level, and the ratio of the first power level to the second power level may be controlled to be about 30: 1 to about 10: 1, for example about 20: 1. in some embodiments, for example, the first power is about 300W and the second power is about 15W.

FIG. 12 illustrates the formation of a first opening 247 through the base layer 241 and the underlying hard mask layers 235 and 237. The bottom layer 241 is patterned using the patterned top layer 245 and the middle layer 243 as a mask. The patterning of the bottom layer 241 may use any suitable process, such as a dry etch process. A dry etch process may be performed in a dual rf power plasma reactor. An exemplary dry etch process for etching bottom layer 241 may include a first etch process and a second etch process subsequent to the first etch process. In advanced technologies, the margin of misalignment (margin for a misalignment) between the contact opening and the gate electrode is significantly reduced due to the shrinking dimensions of device features. Reduced misalignment margins may result in significant device yield loss or create serious device reliability problems, especially in the butt contact regions, where misalignment may easily cause the connection to the source/drain regions or the gate electrode to be completely broken. Therefore, for the convenience of photolithography, it may be advantageous to form the first opening 247 with a wider diameter, and then trim (tailor)/reduce the diameter of the opening when transferring the tri-layer structure 239. The two-stage etch process allows for a gradual reduction of the critical dimension of the pattern in the bottom layer 241. The reduced pattern critical dimension may avoid the chance of misalignment between the contact opening and the gate electrode.

In some embodiments, the first etch process uses a gas including nitrogen (N)₂) And hydrogen (H)₂) The first chemical substance of (1). Nitrogen is flowed into the plasma reactor at a first volumetric flow rate (volumetric flow rate), hydrogen is flowed into the plasma reactor at a second volumetric flow rate, and a ratio of the first volumetric flow rate to the second volumetric flow rate may be controlled to be about 2: 1 to about 5: 1, for example about 3: 1. the chamber pressure of the plasma reactor may be maintained at about 1 mtorr to about 30 mtorr, for example about 10 mtorrMillitorr. During the first etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level may be controlled to be between about 3: 1 to about 7: 1, for example about 5: 1. in some embodiments, for example, the first power is about 500W and the second power is about 100W.

After the first etching process, a gas containing carbon dioxide (CO) is used₂) And oxygen (O)₂) The second chemical species performs a second etch process in the same plasma reactor. Carbon dioxide is flowed into the plasma reactor at a first volumetric flow rate, oxygen is flowed into the plasma reactor at a second volumetric flow rate, and a ratio of the first volumetric flow rate to the second volumetric flow rate may be controlled to be in a range of about 2: 1 to about 6: 1, for example about 3: 1. the chamber pressure of the plasma reactor may be maintained at about 1 mtorr to about 30 mtorr, for example about 10 mtorr. During the second etch process, the power supply power is provided at the first power level and the bias power is provided at the second power level, and the ratio of the first power level to the second power level may be controlled to be between about 2: 1 to about 6: 1, for example about 4: 1. in some embodiments, for example, the first power is about 200W and the second power is about 50W. Upon completion of the second etch process, the opening of the top layer 245 may have a first diameter and the opening of the bottom layer 241 may have a second diameter that is smaller than the first diameter.

Next, the second hard mask layer 237 is patterned using the patterned triple-layer structure 239 as a mask. The patterning of the second hard mask layer 237 may use any suitable process, such as a dry etch process. A dry etch process may be performed in a dual rf power plasma reactor. An exemplary dry etch process for etching the second hard mask layer 237 may include using a chemistry comprising an inert gas, such as argon, and a fluorocarbon gas, such as tetrafluoromethane (CF)₄) Trifluoromethane (CHF)₃) Hexafluorobutadiene (C)₄F₆) Hexafluoroethane (hexafluoroethane; c₂F₆) Difluoromethane (CH)₂F₂) Octafluoropropane (C)₃F₈)、Octafluorocyclobutane (C)₄F₈) Or any combination of the foregoing. In some embodiments, the chemical comprises CF₄And argon gas. The chamber pressure of the plasma reactor may be maintained at about 5 mtorr to about 20 mtorr, such as about 10 mtorr. During the dry etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level may be controlled to be between about 2: 1 to about 6: 1, for example about 3.5: 1. in some embodiments, for example, the first power is about 500W and the second power is about 150W.

A dry etch process and/or a strip (strip) process, such as an ashing process, may then be performed to sequentially remove the patterned top layer 245, the patterned intermediate layer 243, and the patterned bottom layer 241. A wet clean may be performed after the stripping process.

Then, an etching process is performed to transfer the first opening 247 from the second hard mask (also referred to as a second hard mask layer) 237 to the first hard mask layer 235. The etch process may be a dry etch process performed in a dual rf power plasma reactor. An exemplary dry etch process for etching the first hard mask layer 235 may include using a chemistry comprising an inert gas (e.g., argon) and a fluorocarbon gas, such as tetrafluoromethane (CF)₄) Trifluoromethane (CHF)₃) Hexafluorobutadiene (C)₄F₆) Hexafluoroethane (C)₂F₆) Difluoromethane (CH)₂F₂) Octafluoropropane (C)₃F₈) Octafluorocyclobutane (C)₄F₈) Or any combination of the foregoing. In some embodiments, the chemical comprises C₄F₈And argon gas. The chamber pressure of the plasma reactor may be maintained at about 5 mtorr to about 20 mtorr, such as about 10 mtorr. During the dry etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level may be controlled to be between about 2: 1 to about 6: 1, for example about 4: 1. in some embodiments, for example, the first power is about 200W and the second power is about 50W. Can be driedThe wet cleaning process is performed after the wet etching process to remove the residue.

Fig. 13 illustrates the formation of a first contact opening 259 through the second self-aligned contact 233, the protective liner 250, the first self-aligned contact 231, and a portion of the gate spacer 286 using the patterned second hard mask 237 and the patterned first hard mask layer 235 as masks. The first contact opening 259 may be formed by using one or more etching processes. An exemplary etch process may include a first dry etch process performed in a dual rf-powered plasma reactor that removes a portion of the second self-aligned contact 233 using the patterned second hard mask 237 and the patterned first hard mask layer 235 as masks. The first dry etch process may use a chemistry comprising a fluorine-containing gas and an inert gas, such as argon. Suitable fluorine-containing gases may include, but are not limited to, CF₄、CHF₃、CH₃F、C₄F₆、C₂F₆、CH₂F₂、C₄F₈Or any combination of the foregoing. In some embodiments, the chemical comprises C₄F₈And CH₃F. The fluorine-containing gas is flowed into the plasma reactor at a first volumetric flow rate, the argon gas is flowed into the plasma reactor at a second volumetric flow rate, and a ratio of the first volumetric flow rate to the second volumetric flow rate can be controlled to be in a range of about 1: 1 to about 3: 1, for example about 2: 1. the chamber pressure of the plasma reactor may be maintained at about 5 mtorr to about 200 mtorr, for example about 10 to 50 mtorr. During the dry etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level may be controlled to be between about 1: 1 to about 2: 1, in the above range. In some embodiments, for example, the first power is about 300 to 500W and the second power is about 100W.

After removing the second self-aligned contact 233, a portion of the protective liner 250 is exposed. Next, a second dry etch process may be performed in the dual RF power plasma reactor using the patterned second hard mask 237 and the patterned first hard mask layer 235 as masks to remove the exposed protective liner 250.The second dry etch process may use a chemistry comprising a chlorine-containing gas and an inert gas, such as helium or argon. Suitable chlorine-containing gases may include, but are not limited to: chlorine (Cl)₂) And boron trichloride (boron trichloride; BCl₃) Fluoromethane (methyl fluoride; CH (CH)₃F) And the like. The chamber pressure of the plasma reactor may be maintained at about 10 mtorr to about 300 mtorr, such as about 100 mtorr. During the second dry etch process, the power supply power is provided at the first power level and the bias power is provided at the second power level, and the ratio of the first power level to the second power level may be controlled to be between about 3: 1 to about 6: 1, for example about 5: 1. in some embodiments, for example, the first power is about 800W and the second power is about 150W.

After removal of the protective liner 250, a portion of the first self-aligned contact 231 and a portion of the gate spacer 286 are exposed. A third dry etch process may be performed in the dual rf power plasma reactor using the patterned second hard mask 237 and the patterned first hard mask layer 235 as masks to remove the exposed first self-aligned contact 231. In some cases, the exposed first self-aligned contact 231 may be removed using the gate spacer 286 as a mask. In any case, the result of the third dry etch process exposes the top surfaces of gate spacers 286, gate dielectric layer 222, the one or more optional conformal layers 224, and gate conductive fill material 226. The third dry etch process may use a chemistry comprising a fluorine-containing gas and a hydrogen-containing gas. Suitable fluorine-containing gases may include, but are not limited to, F₂、CF₄、CHF₃、C₄F₆、C₂F₆、CH₂F₂、C₄F₈、SF₆Or any combination of the foregoing. Suitable hydrogen-containing gases may include, but are not limited to, CH₄、H₂、NH₃A hydrocarbon or any molecule having an extractable hydrogen atom or any combination of the foregoing. The chemical species may further comprise an oxygen-containing gas, such as O₂、NO、N₂O, and the like. In some embodiments, the chemical comprises CF₄And CH₄. The chamber pressure of the plasma reactor may be maintained at about 5 mtorr to about 200 mtorr, for example about 50 mtorr. During the dry etch process, the power supply power is provided at a first power level and the bias power is provided at a second power level, and the ratio of the first power level to the second power level may be controlled to be between about 2: 1 to about 6: 1, for example about 4: 1. in some embodiments, for example, the first power is about 1600W and the second power is about 350W.

The first contact opening 259 has a bottom 215 and a sidewall 217 extending upward from the bottom 215. The bottom 215 may be substantially coplanar with the top surfaces of the gate conductive fill material 226, the gate dielectric layer 222, and the one or more optional conformal layers 224. In some embodiments, bottom 215 may extend further into a portion of gate spacers 286. The sidewall 217 may be at an angle "a" relative to the bottom 215. In some embodiments, angle "a" is in the range of 91 ° to about 100 °, such as about 92 ° to about 95 ° (e.g., about 93 ° to about 94 °). The angle "a" may vary depending on the application and/or parameters used by the etching process during the formation of the first contact opening 259.

Fig. 14 illustrates the formation of a three-layer structure 261 over the structure of fig. 13. Trilayer structure 261 (which may use the same or similar processes to achieve the same or similar materials as trilayer structure 239) includes a bottom layer 263, an intermediate layer 265, and a top layer 267. The first contact opening 259 is filled with the bottom layer 263 and is over-loaded (overburied) to a predetermined thickness. In one example, the top surface of the bottom layer 263 is higher than the top surface of the second hard mask layer 237. Then, an intermediate layer 265 and a top layer 267 are sequentially deposited over the bottom layer 263.

After the three-layer structure 261 is formed, a second lithography process is used to pattern the top layer 267. A second lithography process is performed by positioning a second mask 269 over the semiconductor device 240. The second mask 269 has a second pattern 271. The second pattern 271 may have similar features to the first pattern 255 described above. In some embodiments, the second pattern 271 comprises a square pattern. Similarly, the second pattern 271 can be transferred to the top layer 267 by exposing the top layer 267 to a radiation beam 257, removing the exposed portions of the top layer 267. As a result, a second opening 273 is formed in the top layer 267. The second opening 273 formed in the top layer 267 is generally aligned with the source/drain region 292, as shown in fig. 14. The width of the second opening 273 may be similar to, greater than, or less than the width of the first opening 247, depending on the application.

Inset 275 in fig. 14 is an enlarged top view schematic diagram illustrating a portion of a pattern 277 of a second mask 269 for patterning the top layer 267, according to some embodiments. The second mask 269 may be adapted for exposure to deep ultraviolet radiation, such as an ArF excimer laser (193 nm) or a KrF excimer laser (248 nm). The pattern 277 includes a plurality of components 279a, 279b, 279c, 279d, which may be lines, squares, grids, or any desired shape (e.g., polygons), depending on the components to be formed in the top layer 267. In some embodiments, the components 279a, 279b, 279c, 279d are square patterns. It is contemplated that the four components and their configuration are shown for illustrative purposes. Depending on the application and the components to be formed in semiconductor device 240, components 279a, 279b, 279c, 279d may be repeated on second mask 269. The features 279a, 279b, 279c, 279d may provide openings for contacts that provide electrical connection to source/drain regions and/or gates of the semiconductor device 240. For example, the component 279a may be a square pattern corresponding to a portion of the first mating contact (e.g., the pattern 158B of the mating contact 158, as shown in fig. 1B). The portion 279B may be a square pattern corresponding to a portion of the second mating contact (e.g., the pattern 159B of the mating contact 159, as shown in fig. 1B). The portions 279c, 279d may be square patterns corresponding to contact members (e.g., contact pattern 160A as shown in fig. 1B). Features 279a, 279B of second mask 269 and features 293a, 293B from first mask 249 recombine to produce rectangular mating contacts (e.g., mating contacts 158, 159 as shown in FIG. 1B) that will be transferred to the target layer (e.g., second self-aligned contacts 233). By separating the layout into multiple different masks (e.g., first mask 249 and second mask 269), features can be formed separately (partially) on a single layer using multiple masks in succession. Therefore, the minimum line pitch in the combined pattern can be reduced while maintaining good resolution.

It should be understood that the components 293a, 293b, 293c, 293d and the components 279a, 279b, 279c, 279d discussed in embodiments of the present invention may be any shape and/or configured in any desired pattern shape so long as the combination of the components 293a, 293b, 293c, 293d and the components 279a, 279b, 279c, 279d produces the predetermined complete shape of the mating contacts and/or other contact components required for the semiconductor device 240.

After patterning the top layer 267, the middle layer 265 and the bottom layer 263 can be patterned in a similar manner as discussed above with reference to fig. 11 and 12, using the patterned top layer 267 as a mask, thereby transferring the second openings 273 to the bottom layer 263. Thereafter, the second hard mask layer 237 may be patterned in a similar manner as discussed above with reference to fig. 11 and 12, using the patterned structure (also referred to as a tri-layer structure) 261 as a mask. The bottom layer 263 remains in the first contact opening 259 at this stage. An etch process may then be performed to transfer the modified second opening 273 from the second hard mask layer 237 to the first hard mask layer 235, in a manner similar to that discussed above with reference to fig. 12.

Fig. 15 shows the formation of a second contact opening 281 through the second self-aligned contact 233 and the protective liner 250. Next, one or more etching processes are performed using the patterned second hard mask 237, the patterned first hard mask layer 235 (and, in some cases, the remaining portion of the bottom layer 263 in the first contact opening 259) as a mask to remove portions of the second self-aligned contact 233 and the protective liner 250, thereby forming a second contact opening 281 with an angled profile. Second contact opening 281 exposes at least a top surface of conductive material 246. The second self-aligned contact 233 may be removed using a first etch process, such as a first dry etch process for removing the second self-aligned contact 233 as discussed above with reference to fig. 13. The protective liner 250 may be removed using a second etch process, such as a second dry etch process for removing the protective liner 250 as discussed above with reference to FIG. 13. After the etching process, the bottom layer 263 remaining in the first contact opening 259 may be removed using a suitable stripping process, such as an ashing process.

The second contact opening 281 has a bottom 223 and a sidewall 225 extending upward from the bottom 223. The sidewall 225 may be at an angle "B" relative to the bottom 223. In some embodiments, angle "B" is in the range of 91 ° to about 100 °, such as about 92 ° to about 95 ° (e.g., about 93 ° to about 94 °). The angle "B" may vary depending on the application and/or parameters used by the etching process during the formation of the second contact opening 281.

Fig. 15 shows the first contact opening 259 and the second contact opening 281. Together, the first contact opening 259 and the second contact opening 281 expose portions of the conductive material 246, the first interlayer dielectric 297, the gate conductive fill material 226, the gate dielectric layer 222, the one or more optional conformal layers 224, and the gate spacers 286. The combination of the first contact opening 259 and the second contact opening 281 provides a contact opening for a mating contact, such as the mating contacts 158 and 159 shown in fig. 1B. In particular, the gate spacers 286 remaining between the replacement gate structure 228b and the source/drain regions 292 form tapered tops 286' due to the sloped sidewalls of the first and second contact openings 259, 281.

Fig. 16 illustrates filling the first and second contact openings 259, 281 (collectively referred to as the mating contact openings 238) with a conductive filler 227, such as a contact metal. The conductive filler 227 may be or may include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys of the foregoing, similar materials, or combinations of the foregoing, and the conductive filler 227 may be deposited by physical vapor deposition, Electrochemical Plating (ECP), atomic layer deposition, chemical vapor deposition, or any suitable deposition technique. In some cases, a barrier/adhesion layer (not shown) may be conformally deposited over the exposed surfaces of the landing contact openings 238. The barrier/adhesion layer may comprise or be titanium nitride, titanium-silicon nitride, titanium-carbon nitride, titanium-aluminum nitride, tantalum-silicon nitride, tantalum-carbon nitride, tungsten carbide, tungsten-carbon nitride, similar materials, or combinations of the foregoing, and may be deposited by atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), Molecular Beam Deposition (MBD), or any suitable deposition technique. After depositing the conductive filler 227, the excess conductive filler 227 may be removed by using a planarization process (e.g., chemical mechanical planarization). The planarization process may remove the excess conductive filler 227, the second hard mask layer 237, the first hard mask layer 235, and the second self-aligned contact 233 until the top surface 229 of the protective liner 250 is exposed. Fig. 17A shows that the top surface 229 of the protective liner 250, the top surface 234 of the conductive fill 227, and the top surface 236 of the second self-aligned contact 233 are substantially coplanar after the planarization process. The landing contact opening 238 generally has a first bottom 1702 above the source/drain region 292 and extending across the source/drain region 292 and a second bottom 1704 above the replacement gate structure 228b and extending across the replacement gate structure 228 b. Tapered features (e.g., tapered top 286' of gate spacer 286) are disposed between first bottom 1702 and second bottom 1704 and extend upwardly from between source/drain region 292 and replacement gate structure 228 b. Although the first bottom 1702 is shown as being higher than the second bottom 1704, the first bottom 1702 may be at the same height as the second bottom 1704, or even lower than the second bottom 1704, depending on the manufacturing applications (receipts) and/or the application. FIG. 17B illustrates an embodiment where the first base 1702 and the second base 1704 are at the same height. The conductive fill 227 in the landing contact opening 238 enables the conductive material 246 contacting the source/drain regions 292 to electrically connect between the gate conductive fill material 226 of the replacement gate structure 228b without the use of a horizontal metal interconnect layer. As a result, a common or mating contact, such as mating contacts 158 and 159 shown in fig. 1B, is obtained.

After the conductive filler 227 is formed in the landing contact opening 238, the structure may undergo further processing to form the various components and regions required to complete the sram memory cell. For example, subsequent processing may form additional contacts/vias (vias)/conductive lines and multi-layer interconnect features (e.g., metal layers and interlayer or inter-metal dielectrics) on the substrate 270 that are configured to connect the various features to form a functional circuit that may include one or more devices.

Fig. 18 illustrates a portion of the cross-sectional schematic of fig. 17A to further illustrate additional details according to some embodiments. It should be understood that fig. 18 is not drawn to scale for purposes of illustration. The butt contact structure 1800 may be considered a W-shaped structure having a left V-shaped section 1802 and a right V-shaped section 1804. The mating contact structure 1800 has a first dimension D1 along a top surface 1801 of the mating contact structure 1800. The left V-shaped portion 1802 has a second dimension D2 along a bottom 1702 of the left V-shaped portion 1802. The right V-shaped portion 1804 has a third dimension D3 along the bottom 1704 of the right V-shaped portion 1804. The ratio of the second dimension D2 to the first dimension D1 may be between about 1: 1.5 to about 1: 3, and the ratio of the third dimension D3 to the first dimension D1 may be in a range of about 1: 1.5 to about 1: 3, or a salt thereof. The bottom 1702 of the left V-shaped portion 1802 and the bottom 1704 of the right V-shaped portion 1804 may be non-coplanar. In the embodiment shown in FIG. 18, the bottom 1702 of the left V-shaped portion 1802 is raised a fourth dimension D4 relative to the bottom 1704 of the right V-shaped portion 1804. The fourth dimension D4 may be in a range of about-5 nanometers to about 5 nanometers. In other words, the bottom 1702 of the left V-shaped portion 1802 may also be lower than the bottom 1704 of the right V-shaped portion 1804. The left V-shaped portion 1802 has a fifth dimension D5 measured from the top surface 1801 to a bottom 1702 of the left V-shaped portion 1802. The right V-shaped portion 1804 has a sixth dimension D6 as measured from the top surface 1801 to the bottom 1704 of the right V-shaped portion 1804. The ratio of the fifth dimension D5 to the sixth dimension D6 may be between about 0.9: 1 to about 1.2: 1, for example about 1: 1.

the left V-shaped section 1802 has sidewalls 1814 that extend between the top surface 1801 of the mating contact structure 1800 and the bottom 1702 of the left V-shaped section 1802. The right V-shaped portion 1804 has sidewalls 1816 that extend between the top surface 1801 of the mating contact structure 1800 and the bottom 1704 of the right V-shaped portion 1804. Gate spacers 286 are disposed between source/drain regions 292 and replacement gate structure 228 b. Gate spacer 286 has a tapered portion (also referred to as a tapered top) 286' that separates left 1802 and right 1804V-shaped portions. In other words, the bottom 1702 of the left V-shaped portion 1802 and the bottom 1704 of the right V-shaped portion 1804 are not continuous. The tapered portion 286' has a first sidewall 1818 and a second sidewall 1820, the second sidewall 1820 intersects (intersecting) the first sidewall 1818 at an angle "E" greater than 0 °, for example, about 2 ° to about 20 °. The first sidewall 1818 is at an angle "F" relative to the bottom 1704 of the right V-shaped portion 1804. The second sidewall 1820 is at an angle "G" relative to the bottom 1702 of the left V-shaped portion 1802. Angle "F" may range from 91 ° to about 100 °, such as from about 92 ° to about 95 °. Angle "G" may be in the range of 91 ° to about 100 °, for example about 92 ° to about 95 °.

Various embodiments described herein may provide a number of advantages. It is to be understood that not all advantages need be described herein, and that not all embodiments need have a particular advantage, other embodiments may provide different advantages. By way of example, embodiments described herein provide improved butting contact structures that enable one or more gates to be connected to one or more active regions without the use of horizontal metal interconnect layers. The butting contact structure between the gate contact and the source or drain contact can be formed by a double patterning process using two separate masks, each mask having a pattern corresponding to half of the common or butting contact structure. By reducing the total number of reticles to two, the number of reticle alignments is reduced, and yield degradation caused by misaligning another reticle is suppressed. As a result, the manufacturing cost can be reduced and the yield (throughput) can be improved. In addition, the improved butting contact structure has tapered gate spacers that protrude into the bottom of the butting contact structure. The tapered gate spacers and the sloped sidewalls of the butting contact structure may ensure good metal filling capability for subsequently deposited metal fills. Thus, the metal filler can be completely deposited in the butt contact structure without voids or seams.

In one embodiment, a structure is provided. The structure includes a first transistor on a substrate, the first transistor including a first source or drain region, a first gate, and a first gate spacer disposed between the first gate and the first source or drain region. The structure also includes a second transistor on the substrate, the second transistor including a second source or drain region, a second gate, and a second gate spacer disposed between the second gate and the second source or drain region. The structure further includes a mating contact disposed over the first source or drain region and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the mating contact to space a first bottom surface of the mating contact from a second bottom surface of the mating contact.

In some embodiments, the portion of the first gate spacer has a tapered profile. In some embodiments, the portion of the first gate spacer has a first sidewall and a second sidewall that intersects the first sidewall. In some embodiments, the first sidewall contacts the first bottom surface of the mating contact at an angle in the range of 91 ° to 100 °. In some embodiments, the first bottom surface and the second bottom surface are at the same height. In some embodiments, the first bottom surface and the second bottom surface are located at different heights.

In another embodiment, a structure comprises: a first transistor on the substrate, the first transistor including a source or drain region; a conductive member contacting the source or drain region; a gate electrode of a gate structure of the second transistor on the substrate. The structure also includes a mating contact including (i) a first surface contacting the gate electrode, (ii) a second surface contacting the conductive feature, (iii) a third surface extending from the first surface at a first angle, and (iv) a fourth surface extending from the second surface at a second angle, the third surface intersecting the fourth surface at the third angle. The structure further includes a gate spacer disposed between the source or drain region and the gate structure, a portion of the gate spacer being laterally disposed between the third surface and the fourth surface.

In some embodiments, the first surface and the second surface are coplanar. In some embodiments, the first surface and the second surface are located at different heights. In some embodiments, the first angle is in the range of 91 ° to 100 °, the second angle is in the range of 91 ° to 100 °, and the third angle is greater than 0 °. In some embodiments, the portion of the gate spacer has a tapered profile. In some embodiments, the mating contact comprises tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys of the foregoing, or combinations of the foregoing.

In another embodiment, a method of manufacturing a semiconductor is provided. The method includes forming a source or drain region of a first transistor on a substrate, forming a gate of a second transistor on the substrate, and forming a gate spacer on one side of the gate, wherein the source or drain region has a conductive feature formed thereon, the gate has a first dielectric layer formed thereon, and the gate spacer is laterally disposed between the gate and the source or drain region; depositing a second dielectric layer over the conductive feature, the first dielectric layer, and the gate spacer, wherein the second dielectric layer is different from the first dielectric layer; depositing a first mask layer over the second dielectric layer; depositing a second mask layer over the first mask layer; etching a first contact opening through the second mask layer, the first mask layer, the second dielectric layer, and the first dielectric layer to expose the gate, the etching the first contact opening comprising using a first etch recipe (recipe) to etch the second mask layer, and using a fourth etch recipe to etch the first dielectric layer, wherein the first, second, third, and fourth etch recipes are different from one another; etching a second contact opening through the second masking layer, the first masking layer, and the second dielectric layer to expose the conductive feature, the etching the second contact opening comprising etching the second masking layer using a first etch recipe, etching the first masking layer using a second etch recipe, etching the second dielectric layer using a third etch recipe, the first contact opening and the second contact opening being connected at the gate spacer, and the first etch recipe and the second etch recipe shaping a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material.

In some embodiments, a method of manufacturing a semiconductor includes: forming a source or drain region on the substrate, a gate on the substrate, and a gate spacer on a side of the gate, wherein the source or drain region has a conductive feature formed thereon, the gate has a first dielectric layer formed thereon, and the gate spacer is laterally disposed between the gate and the source or drain region; depositing a second dielectric layer over the conductive feature, the first dielectric layer, and the gate spacer, wherein the second dielectric layer is different from the first dielectric layer; depositing a first mask layer over the second dielectric layer; depositing a second mask layer over the first mask layer; etching a first contact opening through the second masking layer, the first masking layer, the second dielectric layer, and the first dielectric layer to expose the gate, the etching the first contact opening comprising using a first etch recipe to etch the second masking layer, using the second etch recipe to etch the first masking layer, using a third etch recipe to etch the second dielectric layer, and using a fourth etch recipe to etch the first dielectric layer, wherein the first, second, third, and fourth etch recipes are different from one another; etching a second contact opening through the second masking layer, the first masking layer, and the second dielectric layer to expose the conductive feature, the etching the second contact opening comprising etching the second masking layer using a first etch recipe, etching the first masking layer using a second etch recipe, etching the second dielectric layer using a third etch recipe, the first contact opening and the second contact opening being connected at the gate spacer, and the first etch recipe and the second etch recipe shaping a portion of the gate spacer into a tapered profile; and filling the first contact opening and the second contact opening with a conductive material.

In some embodiments, the first contact opening is defined by a first pattern transferred from a first mask using a first lithography process, and the second contact opening is defined by a second pattern transferred from a second mask using a second lithography process. In some embodiments, the first mask further comprises a third pattern and the second mask further comprises a fourth pattern, the third pattern and the fourth pattern being combined to create contact features in the substrate after the first and second lithographic processes. In some embodiments, the first lithography process is performed as follows: depositing a first mask layer stack over a second mask layer; and forming a first opening corresponding to the first pattern in the first top layer, the first middle layer and the first bottom layer, wherein the size of the first opening in the first top layer is larger than that of the first opening in the first bottom layer. Wherein, in some embodiments, depositing a first masking layer stack over a second masking layer comprises: depositing a first underlayer over the second masking layer; depositing a first intermediate layer over the first bottom layer, the first intermediate layer and the first bottom layer having different materials; and deposition ofThe first top layer is on the first middle layer, and the first top layer and the first middle layer are made of different materials. In some embodiments, the method further comprises: after etching the first contact opening, performing a second photolithography process as follows: depositing a second mask layer stacked on the first contact opening; and forming second openings corresponding to the second patterns in the second top layer, the second middle layer and the second bottom layer, wherein the size of the second openings in the second top layer is larger than that of the second openings in the second bottom layer. Wherein, in some embodiments, depositing a second masking layer stack over the first contact opening comprises: depositing a second underlayer in the first contact opening and over the second masking layer; depositing a second intermediate layer on the second bottom layer, the second intermediate layer and the second bottom layer having different materials; and depositing a second top layer on the second intermediate layer, the second top layer and the second intermediate layer having different materials. In some embodiments, the first top layer, the first intermediate layer, and the first bottom layer are of the same material as the second top layer, the second intermediate layer, and the second bottom layer, respectively. In some embodiments, the first dielectric layer and the second dielectric layer are selected from the group consisting of: silicon carbon oxynitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride. In some embodiments, the first etch recipe is a photoresist composition using a photoresist composition comprising CF₄And argon, and a second etch recipe is a dry etch process using a chemistry comprising C₄F₈And argon, and a third etch recipe is a dry etch process using a chemistry comprising C₄F₈And CH₃F, and a fourth etch recipe using a chemical comprising CF₄And CH₄The chemical dry etching process of (1).

The components of several embodiments are summarized above so that those skilled in the art to which the present invention pertains can more clearly understand the orientation of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.