Semiconductor package
阅读说明:本技术 半导体封装件 (Semiconductor package ) 是由 李智贤 崔正坤 河京武 于 2019-07-05 设计创作,主要内容包括:本发明提供一种半导体封装件,所述半导体封装件包括:半导体芯片;包封剂,覆盖半导体芯片的至少一部分;连接结构,设置在半导体芯片的有效表面上,并包括电连接到半导体芯片的连接焊盘的一个或更多个重新分布层;表面处理层,设置在连接结构的一个或更多个重新分布层中的最下重新分布层的表面上;以及钝化层,设置在连接结构上,覆盖最下重新分布层和表面处理层中的每个的至少一部分,并且具有暴露表面处理层的至少一部分的开口。最下重新分布层的设置有表面处理层的第一表面的表面粗糙度大于最下重新分布层的与第一表面相对的第二表面的表面粗糙度,并且表面处理层具有与最下重新分布层的第一表面的表面粗糙度相对应的凹凸度。(The present invention provides semiconductor packages including a semiconductor chip, an encapsulant covering at least portions of the semiconductor chip, a connection structure disposed on an active surface of the semiconductor chip and including or more redistribution layers electrically connected to connection pads of the semiconductor chip, a surface treatment layer disposed on a surface of a lowermost redistribution layer of the or more redistribution layers of the connection structure, and a passivation layer disposed on the connection structure, covering at least portions of each of the lowermost redistribution layer and the surface treatment layer, and having an opening exposing at least portions of the surface treatment layer.)
A semiconductor package of the kind , comprising:
a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface;
an encapsulant covering at least portions of the semiconductor chip;
a connection structure disposed on the active surface of the semiconductor chip and including or more redistribution layers electrically connected to the connection pads;
a surface treatment layer disposed on a surface of a lowermost redistribution layer of the or more redistribution layers of the connection structure, and
a passivation layer disposed on the connection structure covering at least portions of each of the lowermost redistribution layer and the surface treatment layer and having an opening exposing at least portions of the surface treatment layer,
wherein a surface roughness of an th surface of the lowermost redistribution layer on which the surface treatment layer is disposed is greater than a surface roughness of a second surface of the lowermost redistribution layer opposite to the th surface on which the surface treatment layer is disposed, and
the surface treatment layer has a relief corresponding to a surface roughness of the th surface of the lowermost redistribution layer.
2. The semiconductor package according to claim 1, wherein the surface treatment layer has a plurality of conductor layers, and
each of the conductor layers has a concavity and convexity corresponding to a surface roughness of the th surface of the lowermost redistribution layer.
3. The semiconductor package according to claim 2, wherein the th surface of the lowermost redistribution layer on which the surface treatment layer is disposed has a surface roughness of 1 μ ι η to 3 μ ι η.
4. The semiconductor package according to claim 2, wherein each of the conductor layers has a concavity and convexity of 1 μm to 3 μm.
5. The semiconductor package of claim 1, wherein the lowermost redistribution layer comprises a copper layer, and
the surface treatment layer includes a nickel layer disposed on the copper layer of the lowermost redistribution layer and a gold layer disposed on the nickel layer.
6. The semiconductor package according to claim 5, wherein a surface of the copper layer has a surface roughness,
the nickel layer has a roughness corresponding to a surface roughness of the copper layer, and
the gold layer has a relief corresponding to the relief of the nickel layer.
7. The semiconductor package of claim 5, wherein the copper layer is thicker than the nickel layer and the gold layer.
8. The semiconductor package of claim 7, wherein the nickel layer is thicker than the gold layer.
9. The semiconductor package of claim 1, further comprising: an electrical connection structure disposed on the opening of the passivation layer and connected to the surface treatment layer exposed through the opening of the passivation layer.
10. The semiconductor package of claim 9, wherein the electrical connection structure is a solder ball.
11. The semiconductor package of claim 9, wherein the surface treatment layer is disposed directly between the electrical connection structure and the lowermost redistribution layer.
12. The semiconductor package of claim 1, further comprising: a frame having a through-hole,
wherein the semiconductor chip is disposed in the through-hole, and
the encapsulant fills at least portions of the through-hole.
13. The semiconductor package of claim 12, wherein the frame comprises an th insulating layer, a th wiring layer embedded in the th insulating layer to expose a lower surface, a second wiring layer disposed on an upper surface of the th insulating layer, a th wiring via penetrating the th insulating layer and electrically connecting the th wiring layer to the second wiring layer, a second insulating layer disposed on an upper surface of the th insulating layer and covering at least a portion of the second wiring layer, a third wiring layer disposed on an upper surface of the second insulating layer, and a second wiring via penetrating the second insulating layer and electrically connecting the second wiring layer to the third wiring layer, and
the routing layer, the second routing layer, and the third routing layer are electrically connected to the connection pads.
14. The semiconductor package according to claim 12, wherein the frame comprises an th insulating layer, a th wiring layer provided on a lower surface of the 0 th insulating layer, a second wiring layer provided on an upper surface of the 1 th insulating layer, a 2 th wiring via penetrating the th insulating layer and electrically connecting the th wiring layer to the second wiring layer, a second insulating layer provided on a lower surface of the th insulating layer and covering at least an portion of the th wiring layer, a third wiring layer provided on a lower surface of the second insulating layer, a second wiring via penetrating the second wiring layer and electrically connecting the th wiring layer to the third wiring layer, a third insulating layer provided on an upper surface of the th insulating layer and covering at least a portion of the second wiring layer, a fourth wiring layer provided on an upper surface of the third insulating layer, and a third wiring via penetrating the third insulating layer and electrically connecting the second wiring layer to the fourth wiring layer and electrically connecting the third wiring layer
The routing layer, the second routing layer, the third routing layer, and the fourth routing layer are electrically connected to the connection pads.
15, A semiconductor package, comprising:
a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface;
an encapsulant covering at least portions of the semiconductor chip;
a connection structure disposed on the active surface of the semiconductor chip and including or more redistribution layers electrically connected to the connection pads;
a surface treatment layer including a th conductor layer and a second conductor layer, the th conductor layer being disposed on a surface of a lowermost redistribution layer of the or more redistribution layers, the second conductor layer being disposed on the th conductor layer, and
a passivation layer disposed on the connection structure covering at least portions of each of the lowermost redistribution layer and the surface treatment layer and having an opening exposing at least portions of the surface treatment layer,
wherein the th conductor layer and the second conductor layer have concavities and convexities corresponding to each other.
16. The semiconductor package of claim 15, further comprising: an electrical connection structure disposed on the opening of the passivation layer, in contact with the passivation layer through a sidewall of the opening, and connected to the surface treatment layer exposed through the opening of the passivation layer.
17. The semiconductor package of claim 16, wherein the surface treatment layer is disposed directly between the electrical connection structure and the lowermost redistribution layer.
Technical Field
The present disclosure relates to kinds of semiconductor packages, and more particularly, to kinds of fan-out type semiconductor packages in which connection pads of a semiconductor chip can be redistributed to the outside of a fan-out region.
Background
An important recent trend in the development of technologies involving semiconductor chips is the reduction in size of semiconductor chips. Therefore, in the field of packaging technology, with the rapid increase in demand for small-sized semiconductor chips and the like, it has been required to realize a semiconductor package having a compact size while including a plurality of pins.
The proposed packaging technologies that satisfy the above-described technical demands are fan-out type semiconductor packages that have compact sizes and can realize a plurality of pins by redistributing connection terminals to the outside of a region where a semiconductor chip is disposed.
In another aspect , in the case of a semiconductor package, an Under Bump Metallurgy (UBM) is typically formed on the lowermost side of the redistribution layer to connect the solder balls.
Disclosure of Invention
The aspect of the present disclosure provides fan-out type semiconductor packages capable of ensuring excellent interface adhesion and reliability while omitting an under bump metal layer, in a manner similar to the case where the under bump metal layer is provided.
According to the aspect of the present disclosure, the roughness treatment is relatively excessively performed on the surface of the lowermost redistribution layer to form a significant surface roughness, the surface treatment layer is formed on the surface having the surface roughness, and thus the surface treatment layer is provided in the form of a concavity and convexity corresponding to the surface roughness of the surface of the lowermost redistribution layer.
According to aspects of the present disclosure, a kind of semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, an encapsulant covering at least portions of the semiconductor chip, a connection structure disposed on the active surface of the semiconductor chip and including or more redistribution layers electrically connected to the connection pad, a surface treatment layer disposed on a surface of a lowermost redistribution layer of the or more redistribution layers of the connection structure, and a passivation layer disposed on the connection structure, covering at least portions of each of the lowermost redistribution layer and the surface treatment layer, and having an opening exposing at least portions of the surface treatment layer.
According to aspect of the present disclosure, a kind of semiconductor packages includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, an encapsulant covering at least 0 portions of the semiconductor chip, a connection structure disposed on the active surface of the semiconductor chip and including or more redistribution layers electrically connected to the connection pad, a surface treatment layer including a th conductor layer and a second conductor layer, the th conductor layer being disposed on a surface of a lowermost redistribution layer of the or more redistribution layers, the second conductor layer being disposed on the th conductor layer, and a passivation layer disposed on the connection structure covering at least portions of each of the lowermost redistribution layer and the surface treatment layer and having an opening exposing at least portion of the surface treatment layer, the th and the second conductor layer having a degree of concavity and convexity corresponding to each other.
Drawings
The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a block diagram schematically illustrating an example of an electronic device system;
fig. 2 is a schematic perspective view showing an example of an electronic device;
fig. 3A and 3B are schematic sectional views showing states of a fan-in type semiconductor package before and after being packaged;
fig. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package;
fig. 5 is a schematic sectional view showing a case where a fan-in type semiconductor package is mounted on a printed circuit board and is finally mounted on a main board of an electronic device;
fig. 6 is a schematic sectional view showing a case where a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device;
fig. 7 is a schematic sectional view showing a fan-out type semiconductor package;
fig. 8 is a schematic sectional view showing a case where a fan-out type semiconductor package is mounted on a main board of an electronic device;
fig. 9 is a schematic sectional view showing an example of a fan-out type semiconductor package;
fig. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package of fig. 9;
fig. 11A and 11B are schematic process diagrams illustrating a manufacturing example of the fan-out type semiconductor package of fig. 9;
FIG. 12 is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package, and
fig. 13 is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.
This disclosure may, however, be embodied in many different forms and should not be construed as limited to the particular embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Throughout the specification, it will be understood that when an element such as a layer, region, or wafer (substrate) is referred to as being "on," "connected to," or "bonded to" another element, it can be directly "on," "connected to," or "bonded to" another element or another element, or there can be other elements intervening therebetween.
It will be apparent that, although the terms "," "second," "third," etc. may be used herein to describe various members, components, regions, layers and/or sections, any such members, components, regions, layers and/or sections should not be limited by these terms.
For example, if the device in the figures is turned over, elements described as "above" or "above" relative to other elements would then be "below" or "beneath" relative to the other elements.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or groups thereof, but do not preclude the presence or addition of or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Hereinafter, embodiments of the present disclosure will be described with reference to schematic drawings showing embodiments of the present disclosure. In the drawings, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be considered. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include, for example, variations in shapes that result from manufacture. The following embodiments may also be constituted alone, in combination, or in partial combination.
The disclosure described below may have various configurations and only required configurations are set forth herein, but is not limited thereto.
Electronic device
Fig. 1 is a schematic block diagram illustrating an example of an electronic device system.
Referring to fig. 1, an
The chip
Network-
Depending on the type of
The
Fig. 2 is a schematic perspective view showing an example of the electronic device.
Referring to fig. 2, a semiconductor package may be used for various purposes in various
Semiconductor package
Typically, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product, and may be damaged by external physical or chemical impact. Therefore, the semiconductor chip itself may not be used, and the semiconductor chip may be packaged and used in an electronic device or the like in a packaged state.
Here, in terms of electrical connection, a semiconductor package is required because of a difference in circuit width between the semiconductor chip and the main board of the electronic device. In detail, the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip are very fine, while the size of the component mounting pads of the main board and the pitch between the component mounting pads of the main board used in the electronic device are significantly larger than the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technique for alleviating the difference in circuit width between the semiconductor chip and the main board is required.
Semiconductor packages manufactured by the packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.
Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.
Fan-in type semiconductor package
Fig. 3A and 3B are schematic sectional views showing states of the fan-in type semiconductor package before and after being packaged.
Fig. 4 is a schematic sectional view illustrating a packaging process of a fan-in type semiconductor package.
Referring to fig. 3A through 4, the
Accordingly, the
As described above, the fan-in type semiconductor package may have a package form in which all connection pads (e.g., input/output (I/O) terminals) of the semiconductor chip are disposed inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in a fan-in type semiconductor package form. In detail, many elements installed in a smart phone have been developed to achieve fast signal transmission while having a compact size.
However, in the fan-in type semiconductor package, since all the I/O terminals need to be disposed inside the semiconductor chip, the fan-in type semiconductor package has a large spatial limitation. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the above disadvantages, it may not be possible to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. The reason is that, even in the case where the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip are increased by the redistribution process, the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in type semiconductor package on the main board of the electronic device.
Fig. 5 is a schematic sectional view showing a case where a fan-in type semiconductor package is mounted on a printed circuit board and is finally mounted on a main board of an electronic device.
Fig. 6 is a schematic sectional view showing a case where a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.
Referring to fig. 5 and 6, in the fan-in
As described above, it may be difficult to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. Accordingly, the fan-in type semiconductor package may be mounted on a separate printed circuit board and then mounted on the main board of the electronic device through a packaging process, or the fan-in type semiconductor package may be mounted and used on the main board of the electronic device in a state in which the fan-in type semiconductor package is embedded in the printed circuit board.
Fan-out type semiconductor package
Fig. 7 is a schematic sectional view showing a fan-out type semiconductor package.
Referring to fig. 7, in the fan-out
In addition, , the fan-out type semiconductor package has a form in which the I/O terminals of the semiconductor chip are redistributed by the connection structures formed on the semiconductor chip and are disposed outside the semiconductor chip, as described below.
Fig. 8 is a schematic sectional view showing a case where the fan-out type semiconductor package is mounted on a main board of an electronic device.
Referring to fig. 8, the fan-out
As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate printed circuit board, the fan-out type semiconductor package can be implemented in a thickness smaller than that of the fan-in type semiconductor package using the printed circuit board. Therefore, the fan-out type semiconductor package can be miniaturized and slimmed. In addition, the fan-out type semiconductor package has excellent thermal and electrical characteristics, making it particularly suitable for mobile products. Accordingly, the fan-out type semiconductor package can be realized in a more compact form than a general Package On Package (POP) type form using a Printed Circuit Board (PCB), and a problem due to the occurrence of a warpage phenomenon can be solved.
In addition, the fan-out type semiconductor package refers to a packaging technique for mounting a semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from external impact as described above, and is a concept different from that of a Printed Circuit Board (PCB), such as a printed circuit board or the like having a specification, a use, or the like different from that of the fan-out type semiconductor package and having a fan-in type semiconductor package embedded therein.
Hereinafter, the under bump metallurgy may be omitted. However, in a similar manner to the case where the under bump metal layer is provided, a fan-out type semiconductor package capable of ensuring excellent interface adhesion and reliability will be described with reference to the drawings.
Fig. 9 is a schematic sectional view showing an example of a fan-out type semiconductor package.
Fig. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package of fig. 9.
Referring to fig. 9, a fan-out type semiconductor package 100A according to an exemplary embodiment may include a frame 110 having a through hole 110H, a semiconductor chip 120 disposed in the through hole 110H of the frame 110 and having an active surface on which a connection pad 122 is disposed and an inactive surface disposed opposite to the active surface, an encapsulant 130 covering at least portions of each of the frame 110 and the semiconductor chip 120 and filling at least portions of the through hole 110H, a connection structure 140 disposed on the active surfaces of the frame 110 and the semiconductor chip 120 and including redistribution layers 142a and 142b electrically connected to the connection pad 122, and a passivation layer 150 disposed on the connection structure 140 and covering at least portions of a lowermost redistribution layer 142b of the redistribution layers 142a and 142b, a surface roughness of a lower surface of the lowermost redistribution layer 142b covered by the passivation layer 150 may be greater than a surface roughness of an upper surface opposite to the lower surface, in this case, a surface (e.g., a lower surface) of the lowermost redistribution layer 142b is disposed on a surface (e.g., the lower surface) of the lowermost redistribution layer 142b, a surface roughness of which may be formed with a surface treatment P, and a surface treatment layer P, a surface treatment layer 34 may be formed to cover at least a plurality of surface treatment layers P, and P, P treatment layers P, P19 may be disposed on a surface treatment layer P, and P treatment layer P may be disposed to cover a surface treatment layer P, and P treatment layer P.
In addition, in the case of a semiconductor package, an under bump metallurgy layer is generally formed at the lowermost side of a redistribution layer to connect solder balls, in the case of a package having a tape size, scratches may occur on a surface on which the under bump metallurgy layer is formed during a memory stacking process such as a NAND flash memory.
In another aspect, in the case of the fan-out
In another aspect, the
In addition, the thickness of the
Hereinafter, each component included in the fan-out
The
In this case, the insulating material may be a material suitable for the core layer, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin (specifically, a prepreg) in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or a thermosetting resin or a thermoplastic resin is impregnated in a core material such as glass fiber (or glass cloth) together with the inorganic filler , but is not limited thereto.
The
The
The
In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass fiber (or glass cloth) (e.g., prepreg, ABF, FR-4, BT, etc.).
The
The material of the insulating
The redistribution layers 142a and 142b may be substantially used to redistribute the
The surface treatment layer P may include a plurality of conductor layers P1 and P2. the
In addition, if the surface roughness of the lowermost redistribution layer 142b (e.g., a copper (Cu) layer) is less than 1 μm, the surface treatment layer P may have difficulty in having a significant degree of concavity and convexity, if the surface roughness of the lowermost redistribution layer 142b exceeds 3 μm, the surface treatment layer P (e.g., a nickel (Ni) layer and a gold (Au) layer) may have difficulty in growing, in a similar manner, if the th conductor layer P1 (e.g., a nickel (Ni) layer) has a degree of concavity and convexity less than 1 μm, the second conductor layer P2 may have difficulty in having a significant degree of concavity and convexity, if the nickel (Ni) layer has a degree of concavity and convexity more than 3 μm, the growth of the second conductor layer P2 (e.g., a gold (Au) layer) may have a problem, further, if the second conductor layer P2 (e.g., a gold (Au) layer) has a degree of concavity and convexity less than 1 μm, then it may be difficult to improve the adhesion, further, the th conductor layer P1 (e.g., a nickel (Ni) layer has a degree of convexity and convexity less than 3 μm, preferably, if the second conductor layer P2 has a degree of convexity and less than 3 μm.
In addition, the thickness of the
In another aspect, the
The
The
The
For example, the
In addition, although not shown in the drawings, a metal thin film may be formed on the wall surface of the through
Fig. 11A and 11B are schematic process diagrams illustrating a manufacturing example of the fan-out type semiconductor package of fig. 9.
Referring to fig. 11A, a through
Referring to fig. 11B, a surface treatment layer P may then be formed on the lower surface of the lowermost redistribution layer 142B where the surface roughness is formed, the surface treatment layer P may be formed using electroless nickel plating/displacement gold plating, etc. the formed surface treatment layer P may include a plurality of conductor layers P1 and P2, the conductor layers P1 and P2 may be a nickel (Ni) layer and a gold (Au) layer in sequence, and may have a degree of concavity and convexity corresponding to the surface roughness of the lower surface of the lowermost redistribution layer 142B, since the surface treatment layer P is relatively thin and no planarization process is performed on the surface treatment layer P, the surface roughness of the lower surface of the lowermost redistribution layer 142B may be transferred to the surface of the surface treatment layer P, the degree of surface roughness of the lower surface of the surface treatment layer P may be less than or equal to the degree of surface roughness of the lower surface of the lowermost redistribution layer 142B, the present disclosure is not limited thereto, for example, the degree of surface roughness of the lower surface treatment layer P may be greater than the degree of surface roughness of the lower surface treatment layer P142B may be formed on the lower surface treatment layer P connection structure P150, and the passivation layer P may be formed using a series of passivation layer P bonding processes such as a passivation layer 150, and a passivation layer 150 may be formed according to the excellent bonding process, and a passivation layer P may be formed according to the case of a series of passivation layer P processing, abp 150.
Fig. 12 is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.
Referring to fig. 12, in a fan-out
When the
The
The thickness of each of the
In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass fiber (or glass cloth) (e.g., prepreg, ABF, FR-4, BT, etc.).
The
The
In this regard, it may be advantageous in a process in which the th routing via 113a has a tapered shape in which the width of the upper surface is greater than the width of the lower surface, in this case, the th routing via 113a may be integrated with the pad pattern of the
The surface treatment layer PP may be disposed on the
Other components (for example, other components described with reference to fig. 9 to 11) may also be applied to the fan-out
Fig. 13 is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package.
Referring to fig. 13, in a fan-out type semiconductor package 100C according to another example, a frame 110 may include a insulating layer 111a, a 0 wiring layer 112a and a second wiring layer 112b disposed on both sides of a th insulating layer 111a, respectively, a second insulating layer 111b disposed on a lower surface of a insulating layer 111a and covering a th wiring layer 112a, a third wiring layer 112C disposed on a lower surface of the second insulating layer 111b, a third insulating layer 111C disposed on an upper surface of a insulating layer 111a and covering the second wiring layer 112b, a fourth wiring layer 112d disposed on an upper surface of the third insulating layer 111C, a th wiring layer 112a, a second wiring layer 112b, a third wiring layer 112C, and a fourth wiring layer 112d may be electrically connected to a connection pad 122, the connection structure 140 may further be 5-step-thus, the occurrence of defects of the third wiring layer 112a, the third wiring layer 112C, and the fourth wiring layer 112d may be suppressed in a process of forming the connection structure 3877 a via hole 113a, the third wiring layer 112C, the third wiring layer 112a, the third wiring layer 112C, and the fourth wiring layer 112C may be electrically connected to each other via hole 113a via hole 113b, a via hole 113 b.
a thickness of the insulating
The lower surface of the
The thickness of each of the
The surface treatment layer PP may be disposed on the
Other components (for example, other components described with reference to fig. 9 to 12) may also be applied to the fan-out
As described above, according to the exemplary embodiments, the under bump metal layer is omitted, but a fan-out type semiconductor package capable of securing excellent interface adhesiveness and reliability can be provided in a manner similar to the case where the under bump metal layer is provided.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention as defined by the appended claims.
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