阅读说明：本技术 半导体组件 (Semiconductor assembly ) 是由 布川贵史 笹岛裕一 高野贵之 于 2019-06-28 设计创作，主要内容包括：本发明提供能够阻止电极层的变形的半导体组件。本发明的一个方式涉及的半导体组件具有：电介质膜、多个电路部件、电极层、刚性部件和密封层。上述电介质膜具有第一面和与上述第一面相反侧的第二面。上述多个电路部件搭载于上述第一面。上述电极层配置于上述第二面,且具有与上述多个电路部件电连接的多个电极部。上述多个电极部的至少一部分具有一轴方向上为长边的基部。上述刚性部件配置于上述第一面,具有沿着上述一轴方向延伸的至少一个条状部,且隔着上述电介质膜与上述基部相对置。上述密封层设置于上述第一面,覆盖上述多个电路部件和上述刚性部件。(The invention provides a semiconductor module capable of preventing deformation of an electrode layer. A semiconductor module according to one embodiment of the present invention includes: a dielectric film, a plurality of circuit parts, an electrode layer, a rigid part, and a sealing layer. The dielectric film has a first surface and a second surface opposite to the first surface. The plurality of circuit components are mounted on the first surface. The electrode layer is disposed on the second surface and has a plurality of electrode portions electrically connected to the plurality of circuit components. At least a part of the plurality of electrode portions has a base portion having a long side in an axial direction. The rigid member is disposed on the first surface, has at least one stripe portion extending in the axial direction, and is opposed to the base portion with the dielectric film interposed therebetween. The sealing layer is provided on the first surface and covers the plurality of circuit components and the rigid member.)

1. A semiconductor device, comprising:

a dielectric film having a first surface and a second surface opposite to the first surface;

a plurality of circuit components mounted on the first surface;

an electrode layer disposed on the second surface and having a plurality of electrode portions electrically connected to the plurality of circuit members, at least a part of the plurality of electrode portions having a base portion that is long in an axial direction;

a rigid member that is disposed on the first surface, has at least one stripe-shaped portion extending in the axial direction, and is opposed to the base portion with the dielectric film interposed therebetween; and

and a sealing layer provided on the first surface and covering the plurality of circuit members and the rigid member.

2. The semiconductor assembly of claim 1, wherein:

the dielectric film is formed in a rectangular shape having 2 sides parallel to the one-axis direction,

the rigid member has 2 bar-shaped portions extending along the 2 sides of the dielectric film.

3. The semiconductor assembly of claim 2, wherein:

the rigid member is a frame-shaped member that is disposed along the periphery of the dielectric film and surrounds the plurality of circuit members.

4. The semiconductor assembly of claim 2, wherein:

the rigid member is a pair of shaft-like members arranged along the 2 sides of the dielectric film.

5. The semiconductor assembly of claim 1, wherein:

the plurality of circuit components comprise power semiconductor elements,

the base portion is provided in an electrode portion connected to the power semiconductor element among the plurality of electrode portions.

6. The semiconductor assembly of claim 1, wherein:

the dielectric film is made of polyimide.

7. The semiconductor assembly of claim 1, wherein:

the semiconductor module further includes a solder resist layer provided on the second surface and having an opening portion exposing the base portion,

the rigid member is disposed at a position facing the opening portion with the dielectric film interposed therebetween.

8. The semiconductor assembly of claim 1, wherein:

the base portion is a copper-plated layer having a thickness of 20 to 50 [ mu ] m and a width of 1 to 2mm in a direction orthogonal to the axial direction.

9. The semiconductor assembly of claim 1, wherein:

the thickness of the rigid member is thinner than that of the circuit member.

10. A semiconductor device, comprising:

a dielectric film having a first surface and a second surface opposite to the first surface;

a plurality of circuit components mounted on the first surface;

an electrode layer disposed on the second surface and having a plurality of electrode portions electrically connected to the plurality of circuit members, at least a part of the plurality of electrode portions having a base portion that is long in an axial direction; and

and a rigid member disposed on the first surface, having at least one stripe portion extending in the axial direction, and facing the base portion via the dielectric film.

11. The semiconductor assembly of claim 10, wherein:

the thickness of the rigid member is thinner than that of the circuit member.

Technical Field

The present invention relates to a semiconductor module in which a circuit component is disposed on one surface of a dielectric layer and an electrode layer is disposed on the other surface.

Background

In recent years, a surface mount integrated power module called pol (power Over lay) has been known (for example, see patent document 1). Such a semiconductor device typically has: a dielectric film such as polyimide, a circuit component such as a power semiconductor element or a passive component mounted on one surface of the dielectric film, an electrode layer disposed on the other surface of the dielectric film, and a sealing layer covering the circuit component.

According to the above semiconductor module, since the circuit component is electrically connected to the electrode layer via the dielectric film, it is possible to realize a power semiconductor module in which high integration of the component and reduction in wiring length are achieved, and in which a thickness and a size are reduced while securing a dielectric breakdown voltage. Further, the electrode shape has a high degree of freedom in design, and the electrode terminal in the power semiconductor element that controls the conduction of a large current can be formed in any shape and size.

Disclosure of Invention

Technical problem to be solved by the invention

However, when the area of the electrode terminal is increased to cope with a large current, warpage may occur in forming the sealing layer such that a part of the electrode terminal protrudes outward. That is, when the sealing layer is formed by compression molding or transfer molding, the electrode layer, particularly the terminal region having a large area, may be locally deformed by the molding pressure of the resin from one surface of the dielectric film to the other surface. Therefore, the flatness of the electrode layer is reduced, and the height varies depending on the position of the electrode layer, which may reduce the reliability of mounting on the substrate.

In view of the above circumstances, an object of the present invention is to: provided is a semiconductor device capable of preventing deformation of an electrode layer.

Means for solving the technical problem

In order to achieve the above object, a semiconductor module according to one embodiment of the present invention includes: a dielectric film, a plurality of circuit parts, an electrode layer, a rigid part, and a sealing layer.

The dielectric film has a first surface and a second surface opposite to the first surface.

The plurality of circuit components are mounted on the first surface.

The electrode layer is disposed on the second surface and has a plurality of electrode portions electrically connected to the plurality of circuit components. At least a part of the plurality of electrode portions has a base portion having a long side in an axial direction.

The rigid member is disposed on the first surface, has at least one stripe portion extending in the axial direction, and is opposed to the base portion with the dielectric film interposed therebetween.

The sealing layer is provided on the first surface and covers the plurality of circuit components and the rigid member.

In the semiconductor module, since the rigid member is provided so as to face the base portion through the dielectric film, the molding pressure of the resin toward the base portion is blocked by the rigid member when the sealing layer is formed. Whereby deformation of the base can be prevented.

The dielectric film may be formed in a rectangular shape having 2 sides parallel to the one-axis direction, and the rigid member may have 2 stripe portions extending along the 2 sides of the dielectric film.

The rigid member may be a frame-shaped member disposed along the periphery of the dielectric film and surrounded by the plurality of circuit members.

The rigid member may be a pair of shaft-like members arranged along the 2 sides of the dielectric film.

The plurality of circuit members may include a power semiconductor element, and the base portion may be provided in an electrode portion connected to the power semiconductor element among the plurality of electrode portions.

The dielectric film may be made of polyimide.

The semiconductor module may further include a solder resist layer provided on the second surface and having an opening portion exposing the base portion, and the rigid member may be disposed at a position facing the opening portion with the dielectric film interposed therebetween.

The base portion may be a copper-plated layer having a thickness of 20 to 50 μm and a width of 1 to 2mm in a direction perpendicular to the axial direction.

Another aspect of the present invention relates to a semiconductor device including: a dielectric film, a plurality of circuit components, an electrode layer, and a rigid component.

The dielectric film has a first surface and a second surface opposite to the first surface.

The plurality of circuit components are mounted on the first surface.

The electrode layer is disposed on the second surface and has a plurality of electrode portions electrically connected to the plurality of circuit members, and at least a part of the plurality of electrode portions has a base portion having a long side in an axial direction.

The rigid member is disposed on the first surface, has at least one stripe portion extending in the axial direction, and is opposed to the base portion with the dielectric film interposed therebetween.

The thickness of the rigid member may be thinner than the thickness of the circuit member.

Effects of the invention

As described above, according to the present invention, it is possible to prevent deformation of the electrode layer and ensure reliability of mounting on the substrate.

Drawings

Fig. 1 is a perspective view schematically showing the structure of a semiconductor module according to an embodiment of the present invention.

Fig. 2 is a schematic sectional view taken along line a-a of fig. 1.

Fig. 3 is a schematic sectional view taken along line B-B of fig. 1.

Fig. 4 is a schematic rear view of the semiconductor module on the electrode layer side.

Fig. 5 is an equivalent circuit diagram of a main portion of the semiconductor device described above.

Fig. 6 is a schematic cross-sectional view of a main part of an electrode layer for explaining the operation of the semiconductor device.

Fig. 7 is a schematic perspective view showing a modification of the structure of the semiconductor module.

Fig. 8 is a schematic perspective view showing another modification of the structure of the semiconductor module.

Fig. 9 is a view for explaining an outline of a semiconductor module according to an embodiment of the present invention, wherein (a) is a schematic plan view of an electrode layer side, (b) is a schematic sectional view of (a) taken along line C-C, and (C) is a schematic sectional view of (a) taken along line D-D.

Description of the reference numerals

10 … dielectric film

11 … adhesive layer

20 … circuit component

30 … electrode layer

30a … base

40. 401, 402 … rigid member

50 … sealing layer

60 … solder mask

61. 62 … opening part

100 … semiconductor assembly

Detailed Description

[ summary ]

First, an outline of a semiconductor module according to an embodiment of the present invention will be described with reference to fig. 9. Fig. 9 (a) is a schematic plan view of the electrode layer side of the semiconductor element 1, fig. 9 (b) is a schematic sectional view of the line C-C of (a), and (C) is a schematic sectional view of the line D-D of (a).

Reference numeral 10 denotes a dielectric film 10 made of polyimide. The polyimide film is a material excellent in high-temperature and high-voltage resistance characteristics, is thin to about 25 μm in thickness, and is a flexible substrate. A conductive pattern made of a Cu (copper) plated layer having a thickness of about 50 μm is formed on at least the front surface side (the surface on the near side in fig. 9 a) of the dielectric film 10. Since the resistance is low because of handling a large current and also becoming high temperature, a conductive pattern is formed thick as a heat sink or in consideration of heat dissipation characteristics. The conductive pattern is constituted by electrodes, wirings, and the like.

Referring to fig. 9 (a), reference numeral 20A indicated by a rectangular broken line is a control region (one region of the substrate), and reference numeral 21A is a switch region (another region of the substrate). In the control region 20A, although not shown in detail, on the back surface side (the surface on the deep side in fig. 9 (a)) of the dielectric film 10, for example, a control IC is mounted face down. On the front surface side of the dielectric film 10, wirings are provided in a radial shape from the arrangement region of the control IC, and an electrode 30E is provided at the tip. In the switching region 21A, switching elements or diodes 21 and 22 shown by a dotted rectangle are provided on the back surface side of the dielectric film 10. For example, power transistor 21 and protection diode 22 shown in fig. 5 are provided, and are connected to electrode portions 31 and 32 provided on the front surface side of dielectric film 10. In addition, each of the 2 elements represented by rectangles may be a power transistor. For example, a circuit in which 2 transistors are connected in series may be used, as in a three-phase inverter circuit and a push-pull structure.

The power transistor 21 is provided in the comb-shaped portion 30b of the electrode 31, and the source, the drain, and the gate are electrically connected to the comb-shaped portion 30b via a through hole (via) V. A base portion 30a as an electrode for collecting the comb-teeth portions 30b is provided at a position adjacent to the transistor arrangement region.

Although not specifically shown, a plurality of passive components such as chip resistors and chip capacitors are provided on the back surface side of the dielectric film 10. In addition, the entire front surface side of the dielectric film 10 is covered with a solder resist layer (PSR)60 of about 60 to 80 μm so as to expose a part of the electrode to be a conductive pattern (fig. 9 (b), (c)). In order to mount the motherboard, for example, solder or the like is provided in a portion of the electrode exposed from the solder resist layer 60.

The conductive pattern including the electrodes 30E, 31, and 32 is electrically connected to an electrode of an IC or a transistor via a through hole (hole) formed in the dielectric film 10, which will be described later.

On the other hand, as shown in fig. 9 (b) and 9 (c), a sealing layer 50 for protecting a plurality of circuit components including passive elements such as ICs, switching elements 21 and 22, chip capacitors, and the like is provided on the back surface side of the dielectric film 10. The thickness of the sealing layer 50 is limited by the thickest component, for example, a chip capacitor, and is about 1mm to 2mm thick. In addition, the sealing layer 50 is made of epoxy resin, and is generally provided by vacuum printing, compression molding, or transfer molding. The following is a description of the arrangement with attention paid to the size (an example).

Thickness of dielectric film 10: 20-50 mu m

Thickness of solder resist layer 60: 60-80 mu m

Resin thickness of the sealing layer 50: 1 mm-2 mm (1000 μm-2000 μm)

Conductive pattern (electrode and wiring) thickness: 50-100 mu m

Width of base 30 a: 1.2mm (1200 μm)

Width of comb teeth portion 30 b: 0.8mm (800 μm)

Width of another conductive pattern: about 0.3mm (300 μm)

In a glass epoxy substrate generally used, the conductive pattern is generally thinner than the substrate. However, as described above, a film which is substantially the same as or thinner than the conductive pattern is used, and a sealing resin having a thickness of about 100 times the thickness of the dielectric film or the conductive pattern is provided. The semiconductor module of the present embodiment is completely different from a general substrate module made of a glass epoxy substrate in terms of the above-described relationship in terms of mechanical characteristics, stress generation, and the like.

Here, since the sealing layer 50 having a thickness of 1mm to 2mm is provided on the back surface side of the dielectric film 10 having a thickness of 25 μm, warpage may occur in the entire film as shown by a line L1 in fig. 9 (b) and (c) due to curing shrinkage of the resin layer 50.

Further, it was found by analysis that the warping of the electrode indicated by the line L2 in fig. 9 (b) and (c) occurred due to the injection pressure at the time of resin injection. This is because the solder resist layer 60 is in contact with the bottom surface of the mold, and the pressure at the time of sealing is applied from the back surface side to the front surface side of the dielectric film. In particular, in a wide electrode (particularly, a base) having a width of 1.2mm, the electrode warps significantly in the width direction or the longitudinal direction. Further, since the film and the chip are fixed to each other with an adhesive in the portion of the switching region where the transistor is arranged, the comb-teeth portion 30b is less likely to be warped. On the other hand, since the electrode 30a at the wide base portion, where no transistor is disposed, has a wide width, warpage as indicated by L2 is likely to occur.

That is, the portion for fixing the circuit component and the electrode of the semiconductor element is configured to be flat to some extent by the rigidity of the component and the semiconductor element, but as is clear from the above, the entire substrate is warped due to the influence of the sealing resin, and in addition, the portion of the wide base portion 30a is warped because no rigid member is provided. In addition, in the case of a module in which the sealing layer 50 is not provided, a film of 20 μm to 50 μm and a conductive pattern of 20 μm to 50 μm are formed in the same range, but warpage occurs due to a difference in thermal expansion coefficient between the metal and the resin. Moreover, the boundary between the switch region 21A and the control region 20A is a boundary (gap) of 2 rigid regions, and there is a phenomenon that heat is applied by reflow at the time of mounting the motherboard, and the boundary is bent based on the boundary.

In either case, the warpage of the entire substrate causes poor soldering when mounted on a motherboard. Further, it was found that the warpage of the base 30a is in the vicinity of the through hole V of the comb-teeth portion 30b located in the vicinity of the base, and a failure such as separation of the contact portion of the through hole V occurs due to the warpage. It is also known that the warpage of the electrode causes an increase in the resistance value, and also causes a decrease in the switching speed and an increase in the temperature, and it is necessary to consider the whole.

The following describes the present embodiment in detail.

Fig. 1 is a perspective view schematically showing the structure of a semiconductor module 100 according to an embodiment of the present invention, fig. 2 is a sectional view schematically taken along line a-a of fig. 1, fig. 3 is a sectional view schematically taken along line B-B of fig. 1, and fig. 4 is a schematic rear view of the semiconductor module 100. In each drawing, X, Y, and Z axes represent 3 orthogonal axial directions, the X and Y axes corresponding to the in-plane direction of the semiconductor element 100, and the Z axis corresponding to the thickness direction of the semiconductor element 100. Fig. 1 is a view of fig. 9 with the front and back surfaces reversed and the paper surface rotated by 180 degrees.

Semiconductor module 100 includes dielectric film 10, circuit member 20, electrode layer 30, rigid member 40, and sealing layer 50. The rigid member 40 is formed of a frame or a plate having a rectangular, semicircular, semielliptical, or triangular cross section, for example.

[ dielectric film ]

Dielectric film 10 is made of an electrically insulating resin material having a predetermined thickness. In the present embodiment, dielectric film 10 is formed of a polyimide film having a thickness of 25 μm. Polyimide is very advantageous from the viewpoint of processability, dielectric breakdown characteristics, chemical resistance, and the like.

The thickness of the dielectric film 10 is not limited to this, and may be appropriately set according to the dielectric constant of the material, the magnitude of the required dielectric breakdown voltage, and the like, and may be appropriately selected within a range of, for example, about 20 μm to about 50 μm. The dielectric material is not limited to polyimide, and for example, a suitable material such as Polytetrafluoroethylene (PTFE), polysulfone, or a liquid crystal polymer can be used, and the dielectric material is a material having flexibility.

The shape of the dielectric film 10 is also not particularly limited, and is typically formed in a rectangular shape. The size of the plane of the dielectric film 10 is not particularly limited, and in the present embodiment, the long side parallel to the Y-axis direction has a length of 10mm to 20mm, and the short side parallel to the X-axis direction has a length of 5mm to 15 mm.

The dielectric film 10 has a first surface 10a (a surface on the back side in fig. 9 a) and a second surface 10b (a surface on the front side in fig. 9 b) opposite to the first surface 10 a. A plurality of circuit components 20 are mounted on the first surface 10a via an adhesive layer 11, and an electrode layer 30 electrically connected to the plurality of circuit components 20 via a dielectric film 10 is disposed on the second surface 10 b.

The adhesive layer 11 is formed of a liquid or fluid adhesive or a film-like adhesive sheet applied to the first surface 10 a. The type of the adhesive layer 11 is not particularly limited, and may be formed of an appropriate insulating resin material such as epoxy resin, acrylic resin, or the like. The thickness of the adhesive layer 11 is not particularly limited, and is, for example, 15 μm. In addition, the heat resistance is considered in consideration of temperature rise during driving. The adhesive may be provided on the entire surface, or may be selectively provided in the mounting region of the circuit component.

[ Circuit Member ]

The plurality of circuit components 20 are mounted on the adhesive layer 11 on the first surface 10a of the dielectric film 10. Typically, the plurality of circuit components 20 include active components such as semiconductor elements. As the semiconductor element, a control IC, a discrete power switching element, for example, a transistor may be used, and in the present embodiment, the power transistor 21 and the diode 22 through which a large current flows are included. The semiconductor element further includes a control IC23 that controls the power transistor 21. The circuit components 20 also include passive components 24 such as capacitors and resistors. Predetermined circuit components among these circuit components 20 are electrically connected to the electrode layer 30.

The power transistor 21 includes a BiP transistor made of Si, a MOSFET, an IGBT, and the like, and a transistor made of SiC, GaN, or the like. These semiconductor elements are formed of bare chips, and are mounted so that the active surface faces the first surface 10a and is so-called face-down (face-down). A heat sink for heat dissipation may be bonded to the non-active surface (upper surface in the drawing) of the power transistor 21 and the power diode 22 via a bonding material such as solder. The heat sink may be made of Cu or Al as a main material, may be a metal plate, or may be a thick metal or alloy coating film obtained by plating or sputtering. Further, a substrate called dbc (dba) to which Cu is bonded may be bonded to a ceramic substrate to dissipate heat. The transistor may be of a sealed type, not a bare chip, such as a chip size package (chip size package) or a resin-sealed package.

[ electrode layer ]

The electrode layer 30 is disposed on the second surface 10b of the dielectric film 10, and typically is formed of a metal plating layer formed on the second surface 10 b. As the metal plating layer, typically, a plating layer made of a material mainly containing copper (Cu) is used. The electrode layer 30 has a through hole V (see fig. 3) as an interlayer connection portion electrically connected to each circuit component 20 via the dielectric film 10.

In forming the electrode layer 30, first, the electrode terminals of the circuit components 20 mounted on the first surface 10a of the dielectric film 10 are irradiated with laser light from the second surface 10b side. Thereby, the dielectric film 10 and the adhesive layer 11 are perforated, and the electrode terminals are exposed to the second surface 10b side. Next, a conductor layer to be a seed layer is formed on the second surface 10b by a sputtering method, and then a copper plating layer having a predetermined thickness is formed by an electrolytic plating method. Thereby, the electrode layer 30 including the through hole V is formed, and the electrode layer 30 is electrically connected to the circuit component 20.

The formation of the conductor layer to be the seed layer is not limited to the sputtering method, and an electroless plating method may be employed. The thickness of the electrode layer 30 (the thickness from the second surface 10 b) is not particularly limited, and is, for example, about 50 μm to 100 μm. This ensures current characteristics and productivity of the electrode layer 30. Further, the thicker the electrode layer, the larger the current can be handled, and the heat dissipation is improved. Therefore, in the present embodiment, the electrode layer 30 functions as a heat sink for heat generated from the circuit component and also as a heat dissipation electrode. Since the electrode is made of Cu, at least one oxidation-resistant coating film, such as Ni, Ni/Au, or Ni/Pd/Au, is provided on the surface.

As for plating, there are 2 methods as follows: a type in which patterning is performed after formation of the entirety of the dielectric film 10; and forming a plating resist on dielectric film 10 to selectively cover the film. Here, in the former, the electrode layer 30 is patterned into a plurality of electrode portions having a predetermined shape by using a photolithography technique. As shown in fig. 4, the electrode layer 30 has: a first electrode portion 31 and a second electrode portion 32 in comb teeth shape facing each other in the X-axis direction, a third electrode portion 33 arranged between the first and second electrode portions 31, 32 and having a long side in the X-axis direction, and a plurality of fourth electrode portions 34. In fig. 4, the first and second electrode portions 31 and 32 have comb-teeth portions 30b and base portions 30a, respectively.

The first electrode portion 31 is connected to a source terminal (S) of the power transistor 21 and an anode terminal (a) of the power diode 22. The second electrode portion 32 is connected to the drain terminal (D) of the power transistor 21 and the cathode terminal (K) of the power diode 22. The third electrode portion 33 is connected to the gate terminal (G) of the power transistor 21. The fourth electrode portion 34 is connected to the terminal portions of the control IC23 and the passive component 24, respectively. Fig. 5 shows an equivalent circuit diagram of a main part of the semiconductor device 100.

The circuit of fig. 5 is an example, and a circuit in which 2 power transistors used in an inverter circuit are connected in series can be considered as another example. In this case, the reference numerals 21 and 22 are power transistors. In any case, the second mounting region where the transistor is mounted is a portion where a large current flows and high heat generation is performed.

The electrode layer 30 is divided into a region R1 as a switching region for forming the first to third electrode portions 31 to 33 and a region R2 as a control region for forming the fourth electrode portion 34 and a conductive pattern connected to the control IC 23. Although not shown, the conductive patterns are arranged radially from below the control IC23, for example.

As shown in fig. 4, the region R1 and the region R2 correspond to respective regions obtained by dividing the dielectric film 10 into 2 regions in the longitudinal direction, and in the illustrated example, the regions are set so as to have substantially the same area or so that the region R1 is slightly larger than the region R2.

The first electrode portion 31 and the second electrode portion 32 have a base portion 30a extending in a belt shape parallel to the Y-axis direction and a plurality of comb teeth portions 30b extending from the base portion 301 parallel to the X-axis direction. The base portion 30a is formed wider than the comb teeth portion 30b, and the width thereof is, for example, 1mm to 2 mm. Typically, the base portions 30a are disposed along 2 long sides at the peripheral edge of the dielectric film 10. For example, when a current flows from the comb-teeth 30b to the base 30a, the current concentrates on the base 30a, and thus the width thereof is increased.

The semiconductor module 100 also has a solder resist layer 60 (in fig. 4, a formation region of the solder resist layer 60 is indicated by dots). The solder resist layer 60 is provided on the second surface 10b of the dielectric film 10, and has a first opening 61 and a second opening 62 that open predetermined regions of the electrode layer 30.

The first opening 61 partially exposes the electrode layer 30 (the first to third electrode portions 31 to 33) located in the region R1. The second opening 62 partially exposes the electrode layer 30 (fourth electrode portion 34) located in the region R2. The regions of the electrode portions 31 to 34 exposed through the first and second openings 61 and 62 are configured as external connection terminals connected to an external substrate (motherboard), not shown.

In the present embodiment, the first opening 61 is formed along the peripheral edge of the first to third electrode portions 31 to 33. This ensures the opening areas of the first to third electrode portions 31 to 33, and can handle a large current as an external connection terminal. On the other hand, the fourth electrode portion 34 is a normal signal terminal, and the second opening 62 is formed in a rectangular shape in an island shape having a smaller area than the first opening 61. The second openings 62 are formed at predetermined intervals along the longitudinal direction (Y-axis direction) and the upper direction (X-axis direction) of the region R2 of the dielectric film 10 so as to be aligned with the base portions 30a of the first and second electrode portions 31 and 32.

[ sealing layer ]

The sealing layer 50 is provided on the first surface 10a of the dielectric film 10 so as to cover the plurality of circuit components 20. Typically, the sealing layer 50 is made of an epoxy-based synthetic resin material, and prevents external air containing moisture and the like from coming into contact with the circuit member 20.

The method of forming the sealing layer 50 is not particularly limited, and typically, a molding method such as a compression molding method or a transfer molding method is used. The compression molding method is a method in which an upper mold provided with a first surface 10a of a dielectric film 10 on which an electric circuit component 20 is mounted facing downward is superimposed on a lower mold having a cavity for accommodating a molten resin, and the electric circuit component is pressed and cured by being immersed in the resin. On the other hand, the transfer molding method is a method in which an upper mold is superimposed on a lower mold in which the first surface 10a of the dielectric film 10 on which the circuit component 20 is mounted is oriented upward, and molten resin is pressed and filled into a cavity formed between the upper mold and the lower mold by a plunger through a runner and a gate.

In the case of either the compression molding method or the transfer molding method, the dielectric film 10 is also subjected to a pressure of the resin from the first surface 10a side toward the second surface 10b side during the pressurization. The dielectric film 10 is extremely thin to about 25 μm and has flexibility. In the area of the first surface 10a where the circuit component 20 is mounted, the circuit component receives the pressure of the filling resin, and therefore the pressure transmitted to the second surface 10b side is small. On the other hand, since the region where the circuit component 20 is not mounted is directly subjected to the pressure of the filling resin, the pressure of the filling resin is also transmitted to the electrode layer 30 on the second surface 10b side.

In particular, the solder resist layer 60 having a thickness of 60 to 80 μm is provided on the second surface 10b, and the solder resist layer 60 is provided with openings 61 and 62 for partially exposing predetermined regions of the electrode layer 30 (the first to fourth electrode portions 31 to 34). As shown in fig. 6 a, these openings 61 and 62 have a height difference of a predetermined depth (height) G between the electrode layer 30 and the solder resist layer 60. Therefore, when the sealing layer 50 is formed, the electrode layer 30 side of the dielectric film 10 is set on the surface of the flat plate-shaped molding jig (lower mold) 70, and a space layer S having a thickness corresponding to the height difference G is formed between the electrode layer 30 exposed through the openings 61 and 62 and the molding jig 70.

Since the space layer S is provided between the electrode layer 30 and the molding jig 70 at the portions of the openings 61 and 62 corresponding to the non-mounting regions of the circuit component 20, when the filling pressure of the resin is applied to the first surface 10a, the dielectric film 10 and the electrode layer 30 may be deformed so as to bulge toward the molding jig 70 as schematically shown in fig. 6 (B). The amount of deformation depends on the opening width of the openings 61 and 62 and the thickness of the electrode layer 30, and reaches a maximum value corresponding to the thickness of the space layer S (the depth G of the openings 61 and 62). As a result, the flatness of the electrode layer 30 is reduced, and the height of the electrode layer 30 varies between the mounting area and the non-mounting area of the circuit component 20, resulting in deterioration of the mounting reliability to the external substrate (motherboard).

This causes warpage of the entire dielectric film 10 and warpage of the electrode layer 30 itself, and soldering cannot be performed during solder bonding to the motherboard. In addition, since the warpage of the electrode, particularly the base portion 30a warps, a load acts on the through hole in the vicinity of the base portion 30a, and a problem also arises in the connectivity between the transistor and the electrode.

In order to solve such a problem, the semiconductor module 100 of the present embodiment includes the rigid member 40 for preventing deformation of the dielectric film 10 and the electrode layer 30. The rigid member 40 will be described in detail below.

[ rigid Member ]

The rigid member 40 is disposed on the first surface 10a of the dielectric film 10, which is the mounting surface of the sealing layer 50, so as to face the electrode layer 30 with the dielectric film 10 interposed therebetween. As shown in fig. 1, the rigid member 40 is disposed in the non-mounting region of the circuit component 20 on the first surface 10a, and in the present embodiment, is configured by a frame-shaped (frame-shaped) member disposed around the dielectric film 10 so as to surround the plurality of circuit components 20. The rigid member 40 is bonded to the dielectric film 10 via the adhesive layer 11, as in the case of the circuit member 20.

The rigid member 40 has a pair of first strip portions 41 extending along 2 long sides of the dielectric film 10 and a pair of second strip portions 42 extending along 2 short sides of the dielectric film 10. The pair of first stripe portions 41 are disposed at positions corresponding to the base portions 30a of the first and second electrode portions 31 and 32 exposed through the opening portion 61 of the solder resist layer 60 in the electrode layer 30. That is, the first stripe portion 41 is disposed at a position facing the base portion 30a with the dielectric film 10 interposed therebetween (see fig. 2).

The rigid member 40 receives the filling pressure of the resin in the step of forming the sealing layer 50, and has such a rigidity that deformation of the dielectric film 10 and deformation of the base portion 30a do not occur. The material constituting the rigid member 40 is not particularly limited, and may be a conductive material or a nonconductive material. The conductor is typically made of a metal material, and thus a heat dissipation path of the semiconductor module 100 can be formed.

Assuming that the rigid member 40 is made of metal, in the case of fig. 1, in consideration of short-circuiting between the transistor and the electrode around the IC, an insulating material is provided on the adhesive surface of the rigid member 40, or the rigid member 40 is annularly separated into several pieces so as to surround the dielectric film 10, thereby preventing short-circuiting between the rigid members. In particular, the base may be disposed only at a portion corresponding to 2 bases 30a having a large warpage. On the other hand, if the rigid member 40 is made of an insulating material made of ceramic, resin, or the like, the short circuit can be ignored, and therefore, the rigid member is provided in a ring shape as shown in fig. 1.

Since the rigid member 40 is mounted at the same time as mounting a transistor or the like, the surface of the rigid member 40 is preferably at least partially flat. This is because evacuation can be performed.

The metal material constituting the rigid member 40 is not particularly limited, and is preferably a material having high thermal conductivity and a small thermal expansion coefficient. As the rigid member 40, a high-hardness or high-melting material such as W (tungsten) or Mo (molybdenum) may be used, and thus desired rigidity can be easily ensured. On the other hand, the non-conductor is preferably a ceramic material such as alumina or glass.

The widths of the first and second stripe portions 41 and 42 are not particularly limited, but are preferably larger than the opening 61 (opening width) of the solder resist layer 60. This prevents the filling pressure of the resin from being transmitted to the base portion 30a in the opening 61 when the sealing layer 50 is formed, and thus deformation of the base portion 30a can be effectively prevented. In addition, since the opposite ends of the pair of first stripe portions 41 are connected by the pair of second stripe portions 42, the flatness of the rigid member 40 can be maintained.

The height (thickness) of the first and second stripe portions 41 and 42 is not particularly limited, and is set to an appropriate value that can ensure the rigidity required for the rigid member 40. The height of the first and second stripe portions 41 and 42 may be larger than the height of the circuit component 20 or smaller than the height of the circuit component 20. The first and second stripe portions 41, 42 are formed to have the same thickness, respectively, but the first stripe portion 41 opposed to the base portion 30a may be formed thicker than the second stripe portion 42. The cross-sectional shapes of the first and second stripe portions 41 and 42 are also not particularly limited, and are typically rectangular, but may be triangular or hemispherical with the dielectric film 10 side serving as the base.

When mounting under vacuum is considered, if rigid member 40 is provided before circuit member 20 is mounted, flatness of dielectric film 10 can be maintained. Therefore, when considering the mounting of the circuit component 20 later, the rigid member 40 does not contact the suction head when the thickness is thinner than the circuit component 20.

The rigid member 40 of the present embodiment further includes a third stripe portion 43 (see fig. 1 and 3) disposed between the power transistor 21 and the power diode 22, depending on the circuit configuration. The third stripe portion 43 is formed in parallel with the first stripe portion 41 in a length shorter than that of the first stripe portion 41, and one end thereof is integrally connected to the second stripe portion 42 on one side. The third strip portion 43 is disposed between 2 power semiconductor elements, whereby heat dissipation of these elements is improved. In addition, the deformation of the electrode layer located between these 2 elements can also be prevented.

The rigid member 40 may be disposed on the first surface 10a of the dielectric film 10 together with the circuit member 20 and then covered with the sealing layer 50. Since the first stripe 41 of the rigid member 40 is disposed at a position facing the base portion 30a of the electrode layer 30 through the dielectric film 10, the rigid member 40 receives the filling pressure of the resin in the step of forming the sealing layer 50, thereby preventing the transmission to the base portion 30 a. Further, the base portion 30a and the third electrode portions 34 aligned along the longitudinal direction thereof are both shielded by the rigid member 40 (first stripe portion 41). This prevents deformation of the electrode layer 30 exposed from the openings 61 and 62 of the solder resist layer 60.

Since the rigid member 40 is formed of a frame-like member disposed along the periphery of the dielectric film 10, the first and second stripe portions 41 and 42 are disposed so as to straddle the region R1 and the region R2 of the dielectric film 10. This also ensures the flatness of the entire dielectric film 10, and can prevent warping of the dielectric film 10. In addition, warpage of dielectric film 10 due to the density of the size of electrode layer 30 and the density of circuit components 20 can be suppressed. Further, the strength and rigidity of the semiconductor module 100 can be improved, and also, when reflow mounting is performed on an external substrate (motherboard), warpage of the semiconductor module 100 can be effectively prevented, and further improvement in mounting reliability can be achieved. Even if the sealing layer 50 is omitted, warpage of the entire dielectric film 10 can be suppressed, and the mounting property to the motherboard can be improved.

As described above, according to the present embodiment, even when the electrode area is increased in order to secure a desired large current characteristic, the electrode layer can be effectively prevented from being deformed, and the variation in the height position of the electrode surface can be suppressed. In addition, even when the extremely thin dielectric film 10 is used as the support substrate of the circuit component 20, the semiconductor module 100 can be prevented from warping. This ensures the mounting reliability of the semiconductor module 100. Further, a contact located in the vicinity of the base portion 30a, specifically, a contact portion between the comb-teeth portion 30b and the transistor 21 is not applied with an excessive load, and a good contact can be maintained.

While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications may be made.

For example, in the above embodiment, the rigid member 40 is formed of a frame-shaped member having the first to third stripe-shaped portions 41 to 43, but the present invention is not limited thereto, and may be formed in the form shown in fig. 7 and 8.

Fig. 7 shows an example in which a frame-shaped member with the third strip portions 43 omitted is used as the rigid member 401. The same operational effects as those of the above-described embodiment can be obtained by this configuration.

Fig. 8 shows an example in which the rigid member 402 is formed of a pair of shaft-like members. Each shaft-like member is disposed along the longitudinal direction of dielectric film 10, and is disposed at a position facing base portion 30a of electrode layer 30, as in the above-described embodiment. With this configuration, the same operational effects as those of the above-described embodiment can be obtained. In either case, it is preferable to arrange the control area 20A and the switch area 21A so as to straddle them and overlap at least the left and right bases 30A.