阅读说明：本技术 用于减轻底切的触点制造
(Contact fabrication for undercut mitigation
) 是由 N·达沃德
C·D·曼纳克
S·F·帕沃内 于 2019-06-17 设计创作，主要内容包括：本申请公开用于减轻底切的触点制造。所述的示例提供微电子器件和制造方法(200),包括：通过在导电特征上形成(206)钛或钛钨阻挡层来制造触点结构,在阻挡层上形成(208)锡晶种层,在晶圆或管芯的导电特征上方的晶种层上形成铜结构,加热(222)晶种层和铜结构以在阻挡层和铜结构之间形成青铜材料,使用蚀刻过程去除(224)晶种层,该蚀刻过程选择性地去除晶种层的暴露部分,以及去除(226)阻挡层的暴露部分。(The application discloses contact fabrication for mitigating undercut. The described examples provide a microelectronic device and a method of manufacturing (200), comprising: the contact structure is fabricated by forming (206) a titanium or titanium tungsten barrier layer over the conductive feature, forming (208) a tin seed layer over the barrier layer, forming a copper structure over the seed layer over the conductive feature of the wafer or die, heating (222) the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing (224) the seed layer using an etching process that selectively removes exposed portions of the seed layer, and removing (226) exposed portions of the barrier layer.)
1. A method of manufacturing a contact structure, the method comprising:
forming a barrier layer at least partially over the conductive features of the wafer or die;
forming a seed layer at least partially on the barrier layer, the seed layer comprising tin;
forming a copper structure on the seed layer over conductive features of the wafer or die;
heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure;
removing the exposed portion of the seed layer to expose a portion of the barrier layer; and
removing the exposed portion of the barrier layer.
2. The method of claim 1, wherein the barrier layer comprises titanium or titanium tungsten.
3. The method of claim 2, wherein forming the copper structure on the seed layer comprises:
forming a resist layer on the seed layer;
patterning the resist layer to expose a portion of the seed layer over the conductive features of the wafer or die;
depositing a copper material on the exposed portions of the seed layer; and
removing the resist layer prior to heating the seed layer and the copper structure.
4. The method of claim 3 wherein depositing the copper material on the exposed portion of the seed layer comprises performing an electroplating process (700) that deposits the copper material on the exposed portion of the seed layer.
5. The method of claim 2, wherein removing the exposed portion of the seed layer comprises:
an etching process is performed using an acidic stripping solution, the etching process selectively removing the exposed portions of the seed layer from underlying portions of the barrier layer.
6. The method of claim 1, wherein forming the copper structure on the seed layer comprises:
forming a resist layer on the seed layer;
patterning the resist layer to expose a portion of the seed layer over the conductive features of the wafer or die; and
depositing a copper material on the exposed portions of the seed layer; and
removing the resist layer prior to heating the seed layer and the copper structure.
7. The method of claim 6, wherein removing the exposed portions of the seed layer comprises:
an etching process is performed using an acidic stripping solution, the etching process selectively removing the exposed portions of the seed layer from underlying portions of the barrier layer.
8. The method of claim 1, wherein removing the exposed portions of the seed layer comprises:
an etching process is performed using an acidic stripping solution, the etching process selectively removing the exposed portions of the seed layer from underlying portions of the barrier layer.
9. The method of claim 1, further comprising:
solder is formed on or over the copper structure.
10. The method of claim 9, further comprising:
forming a diffusion barrier layer on the copper structure; and
forming the solder on the diffusion barrier layer over the copper structure.
11. A microelectronic device, comprising:
an electronic component disposed on or in a semiconductor substrate of a wafer or die;
a metallization structure comprising conductive features; and
a contact structure, comprising:
a barrier layer at least partially disposed on the conductive feature,
a copper structure extending at least partially outward from a side of the metallization structure, and
a bronze material disposed between the barrier layer and the copper structure.
12. The microelectronic device of claim 11, wherein the barrier layer comprises titanium or titanium tungsten.
13. The microelectronic device of claim 12, wherein the contact structure further comprises solder on or over the copper structure.
14. The microelectronic device of claim 13, wherein the contact structure further comprises a diffusion barrier layer disposed between the copper structure and the solder.
15. The microelectronic device of claim 11, wherein the contact structure further comprises solder on or over the copper structure.
16. The microelectronic device of claim 15, wherein the contact structure further comprises a diffusion barrier layer disposed between the copper structure and the solder.
17. A method of fabricating a microelectronic device, the method comprising:
manufacturing an electronic component on or in a semiconductor substrate;
fabricating a metallization structure over the semiconductor substrate, including fabricating conductive features along sides of the metallization structure;
fabricating a contact structure comprising:
forming a titanium or titanium tungsten barrier layer at least partially over the conductive feature,
forming a tin seed layer at least partially on the barrier layer,
forming a copper structure on the seed layer over the conductive features of the wafer or die,
heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure,
etching the seed layer using an etching process that selectively removes exposed portions of the seed layer to expose a portion of the barrier layer, an
Removing the exposed portion of the barrier layer; and
the contact structure is soldered to a bond wire or a flip chip substrate.
18. The method of claim 17, wherein forming the copper structure on the seed layer comprises:
forming a resist layer on the seed layer;
patterning the resist layer to expose a portion of the seed layer over the conductive features of the wafer or die;
depositing a copper material on the exposed portions of the seed layer; and
removing the resist layer prior to heating the seed layer and the copper structure.
19. The method of claim 17, further comprising:
solder is formed on or over the copper structure.
20. The method of claim 19, further comprising:
forming a diffusion barrier layer on the copper structure; and
forming the solder on the diffusion barrier layer.
Background
Microelectronic devices, such as integrated circuits and discrete devices, include one or more electronic components, such as transistors, capacitors, inductors, and the like. The microelectronic device is packaged with one or more externally accessible connections for eventual soldering to a user's Printed Circuit Board (PCB). Various microelectronic device package types are provided, including structures having pins or pads, and flip chip packages. Conductive contacts on a semiconductor die are soldered to conductive features on a lead frame using bond wires for electrical connection to pins or pads, or die contacts are soldered to a product substrate or chip carrier for flip chip packaging. A low impedance connection of the conductive contacts to the electronics within the semiconductor die is desirable. However, undercutting performed during the formation of conductive contacts on a semiconductor die may increase the resistance and/or reduce the mechanical integrity of the conductive contact structure. Faster etching of sputtered seed copper compared to electroplated copper of die contact posts or pillars may cause undercut problems due to galvanic corrosion of sputtered copper seeds formed on the underlying barrier layer.
Disclosure of Invention
Described examples provide methods of fabricating contact structures including forming a titanium or titanium tungsten barrier layer on a conductive feature of a wafer or die, forming a tin seed layer on the barrier layer, and forming a copper structure on the seed layer over the conductive feature. The method also includes heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing exposed portions of the seed layer, and removing exposed portions of the barrier layer. Further description provides a microelectronic device comprising an electronic component, a metallization structure and a contact structure provided on or in a semiconductor substrate of a wafer or die. The contact structure includes a barrier layer disposed at least partially over the conductive features of the metallization structure, a copper structure extending at least partially outward from the sides of the metallization structure, and a bronze material disposed between the barrier layer and the copper structure.
Drawings
Fig. 1 is a partial cross-sectional side view of a microelectronic device having a contact structure with a bronze material between a barrier layer and a copper pillar structure.
Fig. 2 is a flow chart of a method of fabricating a microelectronic device and its contact structure.
Fig. 3-13 are partial cross-sectional side views of a microelectronic device undergoing a fabrication process according to the method of fig. 2.
Fig. 14 is a partial cross-sectional side view of a microelectronic device with bond wires soldered to a contact structure.
Fig. 15 is a partial cross-sectional side view of a microelectronic device in which a contact structure is soldered to a flip-chip substrate.
Fig. 16 is a partial cross-sectional side view of a packaged integrated circuit microelectronic device with bond wires soldered between a contact structure and a lead frame in a molded package.
Detailed Description
In the drawings, like numerals refer to like elements throughout, and various features are not necessarily drawn to scale. In the following discussion and claims, the terms "including/including", "having", "with", "having" or variants thereof are intended to be included in a similar manner to the term "comprising", and thus should be interpreted as "including, but not limited to". Furthermore, the term "coupled" is intended to include either indirect or direct electrical or mechanical connections, or a combination thereof. For example, if a first device couples to or with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intermediate devices and connections.
Fig. 1 shows a microelectronic device 100 comprising an electronic component 101 (e.g., a Metal Oxide Semiconductor (MOS) transistor) disposed on or in a semiconductor substrate 102. Although the example microelectronic device 100 is an integrated circuit having multiple components 101, other microelectronic device embodiments may include a single electronic component. In one example, the semiconductor substrate 102 is a silicon wafer, a silicon-on-insulator (SOI) substrate, or other semiconductor structure. One or more isolation structures 103 are formed on selected portions of the upper surface of the substrate 102. In some examples, the isolation structure 103 may be a Shallow Trench Isolation (STI) feature or a Field Oxide (FOX) structure.
A multi-layer metallization structure 104, 106 is disposed over the substrate 102. The metallization structure includes a first dielectric structure layer 104 formed over the substrate 102, and a multi-level upper metallization structure 106. In one example, the first dielectric 104 structure layer is a metal disposed over the upper surfaces of the component 101 and the substrate 102A front dielectric (PMD) layer. In one example, the first dielectric structure layer 104 comprises silicon dioxide (SiO) deposited on the component 101, the substrate 102 and the isolation structure 1032). In one example, the upper metallization structure 106 is a multilayer structure. In one example, a multi-layer structure is formed as a multi-layer metallization structure using an integrated circuit fabrication process. Fig. 1 shows an example 6-layer upper metallization structure 106, including a first layer 108, referred to herein as an interlayer or interlayer dielectric (ILD) layer. Different numbers of layers may be used in different embodiments. In one example, the first ILD layer 108 and other ILD layers of the upper metallization structure 106 are made of silicon dioxide (SiO)2) Or other suitable dielectric material. In some embodiments, the individual layers of the multi-layer upper metallization structure 106 are formed in two stages, including an inter-metal dielectric (IMD, not shown) sublayer and an ILD sublayer overlying the IMD sublayer. The individual IMD and ILD sublayers may be formed from any suitable dielectric material or materials, such as SiO-based2Of the dielectric material of (a).
A tungsten or other conductive contact 110 extends through selective portions of the first dielectric structure layer 104. Subsequent ones of the first ILD layer 108 and the upper metallization structure 106 include conductive metallization interconnect structures 112, such as aluminum, formed on the top surface of the underlying layers. In this example, the first layer 108 and subsequent ILD layers also include conductive vias 113, such as tungsten, that provide electrical connections from the metallization features 112 of the individual layers to the overlying metallization layers. The example of fig. 1 includes a second layer 114 disposed over the first layer 108. The second ILD layer 108 includes conductive interconnect structures 112 and vias 113. The illustrated structure also includes a metallization level with respective dielectric layers 115, 116 and 117, and an uppermost or top metallization layer 118. The substrate 102, the electronic component 101, the first dielectric structure layer 104 and the upper metallization structure 106 constitute a wafer or die 120 having an upper side or surface 121. In this example, each individual layer 115-118 includes a conductive interconnect structure 112 and an associated via 113.
The top metallization layer 118 includes two example conductive features 119, such as uppermost aluminum vias. The conductive feature 119 is included uppermostThe side or surface at the upper side 121 of the wafer or die 120 at the top of the metallization layer 118. Any number of conductive features 119 may be provided. One or more of the conductive features 119 may be electrically coupled with the electronic component 101. In one example, the upper ILD dielectric layer 118 is covered by one or more protective layers (e.g., a Protective Overcoat (PO) and/or passivation layer, not shown), such as silicon nitride (SiN), silicon oxynitride (SiO)xNy) Or silicon dioxide (SiO)2). In one example, the one or more protective layers include one or more openings that expose a portion of the conductive features 119 to allow the features 119 to be electrically connected to corresponding contact structures.
The microelectronic device 100 of fig. 1 also includes two example contact structures 132. Each contact structure 132 is electrically coupled to a corresponding one of the conductive features 119. The single contact structure 132 includes a barrier layer 122 disposed at least partially on the corresponding conductive feature 119 along with a copper structure 126, the copper structure 126 extending at least partially outward (e.g., upward in fig. 1) from the upper side 121 of the wafer or die 120. The single contact structure 132 also includes a bronze material 124 disposed between the barrier layer 122 and the copper structure 126. In one example, the bronze material layer 124 has a thickness (e.g., along the vertical or Y-axis direction in fig. 1) of 300 μm or more and 800 μm or less. In one example, the barrier layer 122 includes titanium (Ti) or titanium Tungsten (TiW). In one example, the thickness of barrier layer 122 is less than the thickness of bronze material layer 124.
In one example, the copper structure 126 provides a copper pillar or stud for subsequent soldering to a flip chip substrate or chip carrier, or for soldering to a bond wire during packaging. In one example, bronze material 124 provides a conductive coupling between copper structure 126 and barrier layer 122. In one example, the lateral dimensions (e.g., along the x-axis in fig. 1) of barrier layer 122, bronze material 124, and copper structure 126 are substantially equal to one another. In particular, the lateral dimensions of bronze material 124 and copper structure 126 are substantially equal in one embodiment due to the reduction or elimination of undercutting of bronze material 124 under copper structure 126 during fabrication. This facilitates low impedance coupling of the copper structure 126 to the conductive features 119 of the wafer or die 120.
In one example, the contact structure 132 further includes solder 130, such as tin-silver (SnAg) on or over the copper structure 126, although not required for all possible implementations. In one example, the contact structure 132 further includes a diffusion barrier 128, such as a nitride material disposed between the copper structure 126 and the solder 130, although other embodiments are possible in which the diffusion barrier 128 and/or the solder 130 are omitted. In another example, the copper structure 126 is soldered directly to a chip carrier substrate or bond wire using solder supplied during the packaging process.
Fig. 2 illustrates a method 200 of fabricating a microelectronic device, such as the device 100 of fig. 1. The example method 200 includes a process or method of manufacturing a contact structure of an electronic device, such as the contact structure 132 of fig. 1. Fig. 3-13 illustrate processing at various intermediate stages of fabrication to fabricate the device 100 of fig. 1 in accordance with the method 200. The method 200 begins with fabricating one or more electronic components on and/or in a substrate at 202. Any suitable semiconductor processing steps may be used at 202 to fabricate one or more electronic components on and/or in the semiconductor substrate 102. For example, the processing at 202 may include fabricating one or more transistors 101 on and/or in a semiconductor substrate 102, as shown in fig. 3. In one example, the fabrication at 202 includes fabricating additional structural features, such as the isolation structure 103 shown in fig. 3. The method 200 of fig. 2 also includes fabricating metallization structures over the substrate (e.g., the first dielectric structure layer 104 and the upper metallization structure 106 over the substrate 102 in fig. 3) at 204. In certain examples, the construction of the metallization structure at 204 may further include fabricating one or more additional electronic components (e.g., resistors, inductors, capacitors, transformers, not shown) at least partially in the metallization structure. In one example, the processing at 202 and 204 provides wafer 120 as shown in fig. 3.
Further processing at 206-226 in fig. 2 provides an inclusive method for fabricating a contact structure, such as contact structure 132 in fig. 1. In this example, the method 200 includes forming a barrier layer at least partially over the conductive features of the wafer 120 at 204. Fig. 4 shows an example including performing a sputtering or electroplating deposition process 400 that deposits a barrier layer 122 on the upper side 121 of the wafer 120. In one example, the deposition process 400 forms a barrier layer 122 of titanium or titanium tungsten material on the wafer side 121 that extends at least partially over the conductive features 119 of the wafer 120.
The method 200 further includes forming a seed layer on the barrier layer at 208. Fig. 5 illustrates one example, including performing a deposition process 500 that forms a tin (Sn) seed layer 123 on the barrier layer 122. In one example, the deposition process 500 forms the tin seed layer 123 to a thickness of 300 μm or more and 800 μm or less. In one example, the process 500 is a sputtering process that deposits tin directly on the TiW or Ti barrier layer 122. In another example, the electroplating deposition process 500 may be used to form a tin seed layer 123 on the barrier layer 122. In one example, the seed layer 123 provides a conductive material to facilitate subsequent electroplating to form a copper structure (e.g., copper structure 126 in fig. 1). Furthermore, the use of tin for the seed layer 123 facilitates subsequent formation of bronze (e.g., bronze 124 in fig. 1) over the barrier layer 122, and further facilitates removal of portions of the bronze 124 without significant undercutting. In this regard, the use of sputtered copper for the seed layer may result in undesirable undercutting during subsequent etching, wherein the etching process preferentially removes the sputtered copper seed layer material at a higher etch rate than the blanket electroplated copper. The use of deposited tin and subsequently formed bronze for the seed layer material in accordance with process 200 advantageously reduces or mitigates undercut and helps to construct a low impedance contact structure to allow soldering with low impedance electrical coupling to the conductive features 119 of wafer 120 during subsequent packaging operations.
The method 200 continues in fig. 2, where copper pillars or pillar structures are formed over the deposited seed layer at 210, 212, and 214. One example embodiment includes forming a photoresist layer at 210 and patterning the photoresist layer to form openings for the pillars at 212. Fig. 6 shows an example deposition process 600 for depositing and patterning a layer of photoresist material 602 on a tin seed layer 123. In one example, the photoresist layer 602 is patterned at 212 using a photolithography process that selectively removes portions of the photoresist material 602 to expose portions of the tin seed layer 123 over the conductive features 119 of the wafer 120. In one example, the lateral (X-axis) width of the opening in the photoresist layer 602 is generally coextensive with the lateral width of the conductive feature 119 of the wafer 120, although not required for all possible implementations. The copper structure formation in this example includes depositing a copper material on the exposed portion of the tin seed layer 123 over the conductive feature at 214. Fig. 7 illustrates an example including performing an electroplating deposition process 700 that forms copper structures 126 in the openings of the photoresist 602. The process 700 forms a copper structure 126 on the exposed portion of the seed layer 123 over the conductive features 119 of the wafer 120. As previously described, the initial use of the tin barrier layer 123 directly beneath the deposited copper structure 126, and the subsequent reaction to form the bronze 124 beneath the electroplated copper structure 126 advantageously mitigates or avoids undercutting in subsequent etching steps during fabrication of the microelectronic device 100. Furthermore, the use of a thin tin barrier layer 123 (e.g., 300 μm to 800 μm) advantageously mitigates or avoids the formation of Kirkendall voids (Kirkendall void) at the interface of the copper pillar structures 126 and the tin seed layer 123.
In one example, the contact structure 132 further includes a diffusion barrier (e.g., 128 in fig. 1), and a solder (e.g., 130) over the deposited copper structure 126. In this example, method 200 also includes forming a diffusion barrier layer at 216 in fig. 2. Fig. 8 shows an example process 800 of forming a diffusion barrier 128 on portions of the copper structure 126 exposed by the photoresist 602. In one example, the process 800 forms a nickel material (Ni) diffusion barrier 128 on exposed portions of the copper structure 126. In another example, the diffusion barrier formation at 216 is omitted.
In the example of fig. 2, the method 200 further includes forming solder on the diffusion barrier layer (if included) at 218, or forming solder directly on the exposed portion of the copper structure 126 at 218. Fig. 9 shows an example process 900 of forming solder (e.g., tin-silver or SnAg)130 on a diffusion barrier 128 over a copper structure 126. In one example, the solder 130 is formed at 218 by an electroplating process 900. In another example, the solder deposition at 218 and the diffusion barrier formation at 216 are omitted.
The method 200 in fig. 2 continues at 220 with the removal of the remaining resist layer. Fig. 10 illustrates a photoresist removal process 1000 (e.g., selective etching) that removes photoresist material 602 from wafer 120. Although the example method 200 is shown and described above using a damascene (damascone) type process to form the copper structures 126 using the patterned photoresist 602, other processing steps may be used to form conductive copper structures on the seed layer over the conductive features 119 of the wafer 120. Further, although the illustrated example wafer 120 includes a plurality of conductive features 119 and corresponding contact structures 132, other implementations are possible in which only a single contact structure 132 is formed, and other examples are possible in which more than two contact structures 132 are formed.
Continuing at 222 in fig. 2, method 200 further includes heating seed layer 123 and copper structure 126 to form bronze material 124 between barrier layer 122 and copper structure 126. Fig. 11 shows an example in which an annealing process 1100 is performed at a temperature sufficient to react the deposited tin seed layer 123 with the overlying electroplated copper 126 to form a bronze material 124 between the underlying barrier layer 122 and the overlying electroplated copper structure 126 over the corresponding conductive features 119 of the wafer 120. In one example, the annealing process 1100 causes diffusion of tin and copper at the interface of the copper pillar structures 126, resulting in the formation of the bronze material 124, as shown in fig. 11.
The method 200 further includes removing the exposed portion of the remnant tin seed layer 123 at 224 in fig. 2 to expose a portion of the barrier layer 122. Fig. 12 shows an example of performing an etching process 1200 that etches the exposed tin seed layer 123. As shown in fig. 12, process 1200 selectively removes the exposed portion of the tin seed layer 123 to expose a portion of the barrier layer 122. In one example, the etch process 1200 uses an acidic stripping solution (e.g., ensrip TL-105 from Enthone, by immersing the wafer 120 in the solution, where no current is required). The etching process 1200 selectively removes exposed portions of the tin seed layer 123 from underlying portions of the barrier layer 122. In another example, the tin seed layer 123 is selectively removed at 224 without substantially removing the copper 126 by immersion in a hot solution of potassium hydroxide or sodium hydroxide. Alternatively, Enstrip TL-105 (from Enthone) can be used by immersing the working sample in the solution and no current is required. Other selective etching processes 1200 may be used, for example, using solutions designed to remove tin from copper and copper alloys. The selective removal of the remaining (e.g., unreacted) seed layer material 123 using process 1200, as well as the previously diffused bronze material 124 between the copper 126 and Ti/TiW barrier layer 122, mitigates or avoids the undercut problems found in alternative processes using a sputtered copper seed layer (not shown).
Process 200 continues at 226 in fig. 2, where the exposed barrier layer 122 is removed. Fig. 13 illustrates one example of using a selective etch process 1300 that removes exposed portions of barrier layer 122 between contact structures 132. The microelectronic device manufacturing process 200 ends at 228 with die singulation (e.g., separating the wafer 120 into two or more dies) and packaging of the individual microelectronic device dies. Fig. 14 illustrates one example packaged microelectronic device 100 undergoing a packaging process 1400 that uses solder 1404 to solder bond wires 1402 to the constructed contact structures 132. Fig. 15 shows another example of the microelectronic device 100 undergoing a flip-chip bonding process 1500, which bonds the constructed contact structure 132 to a conductive pad or feature 1504 of a flip-chip substrate 1502.
The completed microelectronic device 100 may include other features such as molded or ceramic packaging materials, lead frames, solder bumps, and the like. Fig. 16 shows an example Integrated Circuit (IC)1600 that includes the microelectronic device 100. This example includes a bond wire 1402 (e.g., fig. 14 above) soldered between the contact structure 132 and an electrical conductor 1602 (e.g., a lead, pin, or pad) of the lead frame. The example IC 1600 also includes a molded encapsulation material 1604 (e.g., plastic) that encapsulates the die 120, the contact structures 132, the bond wires 1402, and portions of the electrical conductors 1602. An example electrical conductor 1602 is an IC pin or pad that may be soldered to a main printed circuit board (PCB, not shown).
The above examples are merely illustrative of several possible embodiments of various aspects of the disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.
