阅读说明：本技术 半导体装置和制造半导体装置的方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 崔永焕 黄泰周 闵台洪 池永根 韩相旭 于 2015-08-25 设计创作，主要内容包括：提供了半导体装置和制造半导体装置的方法。所述半导体装置包括：至少第一半导体芯片和第二半导体芯片,沿第一方向彼此堆叠；至少一个硅通孔(TSV),至少穿过第一半导体芯片和第二半导体芯片中的第一半导体芯片；接触焊盘,位于第一半导体芯片的所述至少一个TSV上,接触焊盘将第一半导体芯片的TSV电连接到第二半导体芯片；多个虚设焊盘,位于第一半导体芯片上,所述多个虚设焊盘沿第二方向彼此分隔开并且沿第二方向与接触焊盘分隔开,虚设焊盘与接触焊盘在各自的顶表面与底表面之间沿第一方向测量的高度相同。(A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes: at least a first semiconductor chip and a second semiconductor chip stacked on each other along a first direction; at least one Through Silicon Via (TSV) passing through at least a first semiconductor chip of the first and second semiconductor chips; a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip; a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other along the second direction and from the contact pads along the second direction, the dummy pads and the contact pads having a same height as measured along the first direction between the respective top and bottom surfaces.)

1. A semiconductor device, the semiconductor device comprising:

a first semiconductor chip including a passivation layer;

a second semiconductor chip stacked on the first semiconductor chip;

a plurality of first through-silicon vias in and through the first semiconductor chip;

a plurality of contact pads on the plurality of first through-silicon vias and electrically connecting the plurality of first through-silicon vias with the second semiconductor chip, and on the first surface of the first semiconductor chip; and

a plurality of dummy pads on the first surface of the first semiconductor chip and including a first dummy pad, a second dummy pad, a third dummy pad, and a fourth dummy pad,

wherein the passivation layer directly contacts an entire lower surface of each of the plurality of dummy pads,

the first dummy pad and the second dummy pad are located on a first side with respect to the plurality of contact pads, and

the third and fourth dummy pads are located on a second side relative to the plurality of contact pads, the second side being an opposite side of the first side.

2. The semiconductor device of claim 1, wherein the first dummy pad and the second dummy pad are along a first edge of the first semiconductor chip, and

the third dummy pad and the fourth dummy pad are along a second edge of the first semiconductor chip, the second edge being an opposite edge of the first edge.

3. The semiconductor device of claim 2, wherein the plurality of dummy pads further comprises:

a fifth dummy pad and a sixth dummy pad parallel to a third edge of the first semiconductor chip; and

seventh and eighth dummy pads parallel with respect to a fourth edge of the first semiconductor chip, the fourth edge being an opposite edge of the third edge.

4. The semiconductor device of claim 2, wherein there are no dummy pads between the first dummy pads and the first edge of the first semiconductor chip,

there is no dummy pad between the second dummy pad and the first edge of the first semiconductor chip,

there is no dummy pad between the third dummy pad and the second edge of the first semiconductor chip, and

there is no dummy pad between the fourth dummy pad and the second edge of the first semiconductor chip.

5. The semiconductor device of claim 1, further comprising a second plurality of through-silicon vias located in and through the second semiconductor chip.

6. The semiconductor device of claim 1, wherein each of the plurality of dummy pads has no first through silicon vias formed thereunder.

7. The semiconductor device according to claim 1, further comprising a substrate on which the first semiconductor chip is provided,

wherein there is no dummy pad between the substrate and the first semiconductor chip.

8. The semiconductor device of claim 1, wherein the plurality of dummy pads and the plurality of contact pads are formed of the same material.

9. The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are stacked on each other along the first direction, and

none of the plurality of through silicon vias is formed on the same line with the corresponding dummy pad along the first direction.

10. The semiconductor device according to claim 1, wherein the plurality of dummy pads are configured to receive a bonding force for the plurality of contact pads when the second semiconductor chip is bonded on the first semiconductor chip.

11. The semiconductor device of claim 1, wherein the plurality of dummy pads are configured to withstand a bonding force with the plurality of contact pads when bonding the second semiconductor chip on the first semiconductor chip.

12. The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are stacked on each other along the first direction, and

each of the plurality of dummy pads has a same height as each of the plurality of contact pads as measured along a first direction between the respective top and bottom surfaces.

13. The semiconductor device of claim 1, wherein a portion of the plurality of dummy pads are disposed on a left side of the plurality of contact pads and another portion of the plurality of dummy pads are disposed on a right side of the plurality of contact pads such that a force is evenly distributed along a direction in which the first and second semiconductor chips are stacked.

14. The semiconductor device according to claim 13, wherein the plurality of dummy pads are arranged symmetrically with respect to a center of the first semiconductor chip when viewed in a top view.

15. A semiconductor device, the semiconductor device comprising:

a first semiconductor chip including a passivation layer;

a second semiconductor chip stacked on the first semiconductor chip;

a plurality of through-silicon vias in and through the first semiconductor chip;

a plurality of contact pads on the plurality of through-silicon vias and electrically connecting the plurality of through-silicon vias with the second semiconductor chip, and on the first surface of the first semiconductor chip; and

a plurality of dummy pads on the first surface of the first semiconductor chip and including a first group of dummy pads, a second group of dummy pads, a third group of dummy pads, and a fourth group of dummy pads,

wherein the passivation layer directly contacts an entire lower surface of each of the plurality of dummy pads,

a first set of dummy pads is along a first edge of the first semiconductor chip,

a second set of dummy pads along a second edge of the first semiconductor chip, the second edge being an opposite edge of the first edge,

the third group of dummy pads is parallel with respect to the third edge of the first semiconductor chip, and

the fourth set of dummy pads is parallel with respect to a fourth edge of the first semiconductor chip, the fourth edge being an opposite edge of the third edge.

16. The semiconductor device of claim 15, wherein a first set of dummy pads is located on a first side relative to the plurality of contact pads, and

a second set of dummy pads is located on a second side relative to the plurality of contact pads, the second side being an opposite side of the first side.

17. The semiconductor device of claim 15, wherein at least one dummy pad is located between the first set of dummy pads and the second set of dummy pads.

18. The semiconductor device of claim 15, wherein at least one dummy pad of the plurality of dummy pads is located between a third group of dummy pads and the plurality of contact pads.

19. The semiconductor device of claim 15, wherein a third set of dummy pads and a fourth set of dummy pads are opposing with respect to the plurality of contact pads.

20. The semiconductor device according to claim 15, wherein the plurality of second semiconductor chips have no through-silicon-via.

21. The semiconductor device according to claim 15, wherein the first semiconductor chip and the second semiconductor chip are stacked on each other along the first direction, and

none of the first through silicon vias and the corresponding dummy pad are formed on the same line along the first direction.

22. The semiconductor device according to claim 15, wherein the plurality of dummy pads are configured to receive a bonding force for the plurality of contact pads when the second semiconductor chip is bonded on the first semiconductor chip.

23. The semiconductor device of claim 15, wherein the plurality of dummy pads are configured to withstand a bonding force with the plurality of contact pads when bonding the second semiconductor chip on the first semiconductor chip.

24. The semiconductor device according to claim 15, wherein the first semiconductor chip and the second semiconductor chip are stacked on each other along the first direction, and

each of the plurality of dummy pads has a same height as each of the plurality of contact pads as measured along a first direction between the respective top and bottom surfaces.

25. The semiconductor device of claim 15, wherein a portion of the plurality of dummy pads are disposed on a left side of the plurality of contact pads and another portion of the plurality of dummy pads are disposed on a right side of the plurality of contact pads such that the force is evenly distributed along a direction in which the first and second semiconductor chips are stacked.

26. The semiconductor device according to claim 25, wherein the plurality of dummy pads are arranged symmetrically with respect to a center of the first semiconductor chip when viewed in a top view.

27. A semiconductor device, the semiconductor device comprising:

a substrate;

a first semiconductor chip on the substrate and including a passivation layer;

a second semiconductor chip stacked on the first semiconductor chip;

a plurality of first through-silicon vias in and through the first semiconductor chip;

a plurality of contact pads on the plurality of first through-silicon vias and electrically connecting the plurality of first through-silicon vias with the second semiconductor chip, and on the first surface of the first semiconductor chip; and

a plurality of dummy pads on the first surface of the first semiconductor chip and including a first group of dummy pads, a second group of dummy pads, a third group of dummy pads, and a fourth group of dummy pads,

wherein the passivation layer directly contacts an entire lower surface of each of the plurality of dummy pads,

a first set of dummy pads parallel with respect to a first edge of the first semiconductor chip and on a first side with respect to the plurality of contact pads,

a second set of dummy pads parallel with respect to a second edge of the first semiconductor chip and on a second side with respect to the plurality of contact pads, the second edge being an opposite edge of the first edge, the second side being an opposite side of the first side,

the third group of dummy pads is parallel with respect to the third edge of the first semiconductor chip, and

the fourth set of dummy pads is parallel with respect to a fourth edge of the first semiconductor chip, the fourth edge being an opposite edge of the third edge.

28. The semiconductor device of claim 27, wherein the first set of dummy pads is along a first edge of the first semiconductor chip, and

the second set of dummy pads is along a second edge of the first semiconductor chip.

29. The semiconductor device according to claim 27, further comprising:

a third semiconductor chip stacked on the second semiconductor chip; and

and a plurality of second through-silicon vias in and through the second semiconductor chip.

30. The semiconductor device of claim 27, wherein the plurality of dummy pads are electrically insulated from the first semiconductor chip by a passivation layer.

31. The semiconductor device according to claim 27, wherein the first semiconductor chip and the second semiconductor chip are stacked on each other along the first direction, and

none of the first through silicon vias and the corresponding dummy pad are formed on the same line along the first direction.

32. The semiconductor device of claim 27, wherein the plurality of dummy pads are configured to withstand bonding forces for the plurality of contact pads when bonding the second semiconductor chip on the first semiconductor chip.

33. The semiconductor device of claim 27, wherein the plurality of dummy pads are configured to withstand a bonding force with the plurality of contact pads when bonding the second semiconductor chip on the first semiconductor chip.

34. The semiconductor device according to claim 27, wherein the first semiconductor chip and the second semiconductor chip are stacked on each other along the first direction, and

each of the plurality of dummy pads has a same height as each of the plurality of contact pads as measured along a first direction between the respective top and bottom surfaces.

35. The semiconductor device of claim 27, wherein a portion of the plurality of dummy pads are disposed on a left side of the plurality of contact pads and another portion of the plurality of dummy pads are disposed on a right side of the plurality of contact pads such that the force is evenly distributed along the direction in which the first and second semiconductor chips are stacked.

36. The semiconductor device according to claim 35, wherein the plurality of dummy pads are arranged symmetrically with respect to a center of the first semiconductor chip when viewed in a top view.

37. A semiconductor device, the semiconductor device comprising:

at least a first semiconductor chip and a second semiconductor chip stacked on each other along a first direction;

at least one through-silicon-via passing through at least a first semiconductor chip of the first and second semiconductor chips;

a contact pad on the at least one through-silicon via of the first semiconductor chip, the contact pad electrically connecting the through-silicon via of the first semiconductor chip to the second semiconductor chip;

a plurality of dummy pads on the upper surface of the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pads along the second direction, and the dummy pads having the same height as the contact pads as measured along the first direction between the respective top and bottom surfaces; and

a passivation layer between the first semiconductor chip and the plurality of dummy pads, the passivation layer being in direct contact with an entire lower surface of each of the plurality of dummy pads.

38. The semiconductor device of claim 37, wherein at least one through silicon via is formed on the same line as a corresponding dummy pad along the first direction.

39. The semiconductor device of claim 37, wherein the plurality of dummy pads are configured to withstand bonding forces for the plurality of contact pads when bonding the second semiconductor chip on the first semiconductor chip.

40. The semiconductor device of claim 37, wherein the plurality of dummy pads are configured to withstand a bonding force with the plurality of contact pads when bonding the second semiconductor chip on the first semiconductor chip.

41. The semiconductor device of claim 37, wherein each of the plurality of dummy pads has a same height as each of the plurality of contact pads as measured along the first direction between the respective top and bottom surfaces.

42. The semiconductor device of claim 37, wherein a portion of the plurality of dummy pads are disposed on a left side of a contact pad and another portion of the plurality of dummy pads are disposed on a right side of a contact pad such that the force is evenly distributed along the first direction.

43. The semiconductor device according to claim 42, wherein the plurality of dummy pads are arranged symmetrically with respect to a center of the first semiconductor chip when viewed in a top view.

44. A method of fabricating a semiconductor device, the method comprising:

forming at least one through-silicon-via through the first semiconductor chip;

forming a passivation layer on the first semiconductor chip, the passivation layer having at least one opening exposing one end of the at least one through-silicon-via;

simultaneously forming a contact pad on the one end of the at least one through silicon via and a plurality of dummy pads on the passivation layer such that the passivation layer is in direct contact with an entire lower surface of each of the plurality of dummy pads; and

the second semiconductor chip is stacked on the first semiconductor chip such that the contact pads electrically connect the through-silicon vias of the first semiconductor chip to the second semiconductor chip.

Technical Field

Background

Recently, the electronics industry (e.g., semiconductor industry) has demanded high bandwidth and high capacity devices. Accordingly, there is an increasing demand for a technique of stacking multiple chips.

Disclosure of Invention

Drawings

Features will become apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

fig. 1 shows a schematic cross-sectional view of a semiconductor device according to an embodiment;

fig. 2 shows a schematic cross-sectional view of a semiconductor device according to another embodiment;

fig. 3 shows an enlarged portion C of fig. 2;

fig. 4 shows an enlarged portion D of fig. 2;

fig. 5 illustrates an exploded view of a stacked structure of the semiconductor device of fig. 2;

fig. 6 to 13 are sectional views showing steps in a method of manufacturing a semiconductor device according to an embodiment;

fig. 14A to 14D illustrate different top views of dummy pad arrangements in a semiconductor device according to an embodiment;

fig. 15 shows a block diagram of a memory card including a semiconductor device according to the embodiment;

fig. 16 shows a block diagram of an information processing system using a semiconductor device according to an embodiment;

fig. 17 shows a block diagram of an electronic device including a semiconductor device according to an embodiment.

Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device.