Semiconductor device with a plurality of transistors
阅读说明:本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 小山田成圣 于 2015-09-28 设计创作,主要内容包括:本发明涉及半导体器件。这样一种半导体器件的电源布线结构,其包括以倒装芯片方式安装在衬底上的半导体芯片,其降低了内部布线的特性阻抗且由此提高了噪声降低效果,同时实现了在高频电源操作期间的低阻抗。在从平面图观察时的半导体芯片的安装面上的多个周边电极焊盘的内侧区域中,在半导体芯片的保护膜上的第一绝缘膜上,半导体器件具有用于将电力提供至半导体芯片的内侧电源板结构。内侧电源板结构包括在第一绝缘膜上的第一电源板、在第一电源板上的第二绝缘膜、以及第二绝缘膜上的第二电源板。(The present invention relates to a semiconductor device. A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate reduces the characteristic impedance of internal wiring and thereby improves the noise reduction effect while achieving low impedance during high-frequency power supply operation. The semiconductor device has an inside power supply board structure for supplying power to the semiconductor chip on a first insulating film on a protective film of the semiconductor chip in an inside region of the plurality of peripheral electrode pads on the mounting surface of the semiconductor chip as viewed in a plan view. The inner power supply plate structure includes a first power supply plate on the first insulating film, a second insulating film on the first power supply plate, and a second power supply plate on the second insulating film.)
1. A semiconductor device, comprising:
a substrate provided with a first power supply land and a second power supply land;
a semiconductor chip flip-chip mounted on the substrate;
a first insulating film disposed on a mounting surface of the semiconductor chip facing the substrate;
an inner power board structure integrally disposed with the semiconductor chip between the semiconductor chip and the substrate via the first insulating film,
the semiconductor chip includes:
a plurality of peripheral electrode pads including a first peripheral power supply pad and a second peripheral power supply pad located in a peripheral portion of the mounting surface, and a first inner power supply pad and a second inner power supply pad located in an inner region of the peripheral electrode pads; and
a protective film formed on the mounting surface of the semiconductor chip at a position other than the peripheral electrode pad, the first inner power supply pad, and the second inner power supply pad;
the first insulating film is formed on the protective film of the semiconductor chip inside the plurality of peripheral electrode pads in a plan view and has openings at positions corresponding to the first inner power supply pad and the second inner power supply pad,
the inner power board structure is formed on the first insulating film, supplies power to the semiconductor chip,
the inboard power strip structure includes:
a first power supply plate formed on the first insulating film;
a second insulating film formed on the first power supply plate;
a second power supply plate formed on the second insulating film; and
a substrate-side insulating film formed on the second power supply plate,
the first power supply board has, in a peripheral portion thereof, a first peripheral power supply terminal connected to the first peripheral electrode pad of the semiconductor chip via a bump and connected to the first inner power supply pad of the semiconductor chip via a bump penetrating the opening of the first insulating film,
the first power supply plate and the second insulating film each have an opening at a position corresponding to the second inner power supply pad of the semiconductor chip;
the second power supply plate has, in a peripheral portion thereof, a second peripheral power supply terminal connected to the second peripheral electrode pad of the semiconductor chip via a bump, and connected to the second inner power supply pad of the semiconductor chip via a bump penetrating the opening formed in the first insulating film and the openings formed in the first power supply plate and the second insulating film,
the substrate-side insulating film, the second power supply plate, and the second insulating film have openings at positions corresponding to the first power supply lands of the substrate, respectively, the first power supply plate is connected to the first power supply lands of the substrate via bumps penetrating the openings, the substrate-side insulating film has openings at positions corresponding to the second power supply lands of the substrate, and the second power supply plate is connected to the second power supply lands of the substrate via bumps penetrating the openings.
2. The semiconductor device of claim 1, wherein:
the plurality of peripheral electrode pads are arranged in two rows at an inner periphery and an outer periphery;
the first peripheral power supply pad and the second peripheral power supply pad are peripheral electrode pads arranged on an inner periphery; and
the peripheral electrode pads arranged at the outer periphery include a third peripheral power supply pad and a fourth peripheral power supply pad,
the semiconductor device further includes: an outer power board structure in an outer peripheral portion of the semiconductor chip and arranged close to the semiconductor chip as viewed in a plan view,
the outside power strip structure includes:
a third power supply board including a third peripheral terminal connected to the third peripheral power supply pad;
a third insulating film formed on the third power supply plate; and
a fourth power supply plate formed on the third insulating film and including a fourth peripheral terminal connected to the fourth peripheral power supply pad.
3. The semiconductor device of claim 2, comprising a connection connecting the inner power plane structure and the outer power plane structure,
wherein the connecting portion includes:
a first connection part electrically connecting the third power supply board and the first power supply board;
a second connection part electrically connecting the fourth power supply board and the second power supply board; and
and a third connection portion connecting the second insulating film and the third insulating film.
4. The semiconductor device of claim 3,
the third power supply board includes a first power supply land connected to the substrate; and
the fourth power supply board includes a second power supply land connected to the substrate.
5. The semiconductor device of claim 4,
the semiconductor chip has a rectangular shape in plan view;
the outer power strip structure is arranged to surround an outer peripheral portion of the rectangular semiconductor chip; and
the first power supply land and the second power supply land are arranged at positions on an extension line of a diagonal line of the rectangular shape.
6. The semiconductor device according to any one of claims 2 to 5,
the first power supply plate and the third power supply plate, the second power supply plate and the fourth power supply plate, and the second insulating film and the third insulating film are respectively arranged on the same plane.
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a power supply wiring structure for supplying power to a semiconductor chip (semiconductor integrated circuit) in a semiconductor device in which the semiconductor chip is flip-chip mounted on a substrate.
Background
Conventionally, as cA power supply wiring structure for supplying power to cA semiconductor integrated circuit (hereinafter referred to as "LSI"), for example, cA technique disclosed in JP- cA-2006-173418 is known. According to this technique, a power supply wiring structure (hereinafter referred to as a "mesh power supply wiring structure") includes: a first wiring layer in which a plurality of power supply voltage supply lines (hereinafter referred to as "power supply voltage lines") and a plurality of reference voltage supply lines (hereinafter referred to as "ground lines") are alternately arranged; a second wiring layer in which a plurality of power supply voltage lines and a plurality of ground lines are alternately arranged in a direction perpendicular to a wiring direction of the first wiring layer; and an insulating layer disposed between the first wiring layer and the second wiring layer. In the mesh wiring structure, a parasitic capacitance is formed at an overlapping portion (intersection) of the power supply voltage line of the first wiring layer and the ground line of the second wiring layer, or an overlapping portion of the ground line of the first wiring layer and the power supply voltage line of the second wiring layer, via the insulating layer. The parasitic capacitance can be used as a capacitance to reduce power supply noise.
However, since an increase in LSI clock frequency has been achieved in recent years, the parasitic capacitance of a general mesh power supply wiring structure is not necessarily expected to provide a power supply noise reduction effect with respect to a desired frequency bandwidth. Further, in the case where the latest LSI design rule requires more minute features, when the LSI power supply wiring has a mesh structure, the transmission path of the signal line system in the LSI has high characteristic impedance. Therefore, in the case of a relatively long wiring, a mismatch may occur between the output impedance of the transistor in the LSI and the characteristic impedance of the transmission path, thereby causing noise. Also, a relatively long transmission path having such a high characteristic impedance may serve as an antenna that picks up noise. Meanwhile, as for the power supply impedance (impedance on the power supply side as viewed from LSI) at a high frequency of the LIS power supply, the wiring resistance (series resistance) of the power supply becomes too high to be ignored because of the mesh structure. This results in that the intended operation of the LSI at high frequencies cannot be obtained due to parasitic inductance and parasitic wiring resistance in the power supply wiring network.
Disclosure of Invention
Accordingly, the present specification provides a power supply wiring structure in a semiconductor device having a semiconductor chip flip-chip mounted on a substrate, whereby the characteristic impedance of the internal wiring of an LSI can be reduced and the noise reduction effect can be improved, while achieving a lower impedance during high-frequency operation of the LSI power supply.
The present specification discloses a semiconductor device including a substrate and a semiconductor chip flip-chip mounted on the substrate. The semiconductor chip includes a plurality of peripheral electrode pads formed on a peripheral portion of a mounting face facing the substrate and connected to the substrate, and a protective film formed on the mounting face except for portions where the plurality of peripheral electrode pads are formed. The semiconductor device further includes: the power supply board includes a first insulating film formed on a protective film of the semiconductor chip, and an inner power supply board structure formed on the first insulating film in an inner region of the plurality of peripheral electrode pads in a plan view of the mounting surface and configured to supply power to the semiconductor chip. The inboard power strip structure includes: a first power supply plate formed on the first insulating film, a second insulating film formed on the first power supply plate, and a second power supply plate formed on the second insulating film.
According to this structure, for example, by forming a power supply path for supplying power to a semiconductor chip (LSI) as a power supply board to be approximately the same area as an inner area of a mounting surface of the semiconductor chip, wiring resistance of the power supply path can be reduced, whereby parasitic series resistance or Equivalent Series Resistance (ESR) relating to a power supply of the semiconductor chip can be reduced. Further, the first power supply board, the second insulating film, and the second power supply board constitute a power supply noise removal capacitor (bypass capacitor) having a capacitance comparable to or larger than that of a parasitic capacitor of a mesh electrode structure formed in an LSI. Due to the low ESR, the electrodes of low ESL (parasitic series inductance) formed by the first power supply plate and the second power supply plate, and the relatively large capacitance formed by the two plates, the signal line noise and the power supply noise can be reduced, and stable operation at high frequencies of the LSI can be realized.
In the semiconductor device, the semiconductor chip may include a first inner power supply pad connected to the first power supply board and a second inner power supply pad connected to the second power supply board in an inner region of the plurality of peripheral electrode pads. The first power supply board may include a first inner power supply terminal connected to the first inner power supply pad and the substrate. The second power supply board may include a second inner power supply terminal connected to the second inner power supply pad and the substrate. The semiconductor chip may be supplied with power from the substrate via the first and second internal power supply terminals.
According to this configuration, power can be directly supplied from the substrate to the semiconductor chip via the power supply pad formed in the inner region of the peripheral electrode pad without passing through the power supply line. Therefore, the power supply line between the substrate and the semiconductor chip can be minimized. Therefore, the power supply line resistance and inductance can be further reduced, and the impedance with respect to the high frequency of the semiconductor chip power supply can be reduced. Further, the first power supply plate, the second insulating film, and the second power supply plate constitute a bypass capacitor in addition to the power supply structure. Therefore, the bypass capacitor can be directly connected to the semiconductor chip without passing through the wiring line, whereby a lower ESL can be achieved and the power supply noise removal effect during high-frequency operation of the LSI can be improved.
In the semiconductor device, the plurality of peripheral electrode pads may include a first peripheral power supply pad connected to the first power supply board and a second peripheral power supply pad connected to the second power supply board. The first power supply board may include a first peripheral power supply terminal connected to the first peripheral power supply pad. The second power supply board may include a second peripheral power supply terminal connected to the second peripheral power supply pad. The semiconductor chip may be further configured to be supplied with power from the substrate via the first peripheral power supply terminal and the second peripheral power supply terminal.
According to this configuration, power can be further supplied from the substrate to the semiconductor chip via the peripheral power supply pad of the semiconductor chip. Therefore, it is possible to cope with a plurality of power supply systems of the semiconductor chip.
In the semiconductor device, the plurality of peripheral electrode pads may be arranged in two rows at an inner periphery and an outer periphery, the first peripheral power supply pad and the second peripheral power supply pad may be peripheral electrode pads arranged at the inner periphery, and the peripheral electrode pads arranged at the outer periphery may include a third peripheral power supply pad and a fourth peripheral power supply pad. The semiconductor device may further include an outer power supply plate structure disposed in an outer peripheral portion of the semiconductor chip and close to the semiconductor chip as viewed in a plan view, the outer power supply plate structure including a third power supply plate connected to a third peripheral terminal of the third peripheral power supply pad, a third insulating film formed on the third power supply plate, and a fourth power supply plate formed on the third insulating film and including a fourth peripheral terminal connected to the fourth peripheral power supply pad.
According to this structure, power can also be supplied to the semiconductor chip from the outer peripheral portion of the semiconductor chip. That is, the power supply path from the substrate to the semiconductor chip can be further increased. Furthermore, the bypass capacitor connected to the semiconductor chip may not be configured as a separate, discrete component but rather be configured to access the outer periphery of the semiconductor chip in a direct manner without passing through a wiring line.
The semiconductor device may further include a first connection portion for electrically connecting the third power supply plate and the first power supply plate, a second connection portion for electrically connecting the fourth power supply plate and the second power supply plate, and a third connection portion for connecting the second insulating film and the third insulating film.
According to this configuration, the inner power board structure and the outer power board structure are electrically connected and integrated through the first to third connecting portions, whereby the selection of the power supply manner from the substrate to the semiconductor chip can be increased. For example, the configuration for supplying power directly from the substrate to the inside power supply board structure (the first and second inside power supply pads, the first and second inside power supply terminals, and the like) may be omitted.
In the semiconductor device, the third power supply plate may include a first power supply land connected to the substrate, and the fourth power supply plate may include a second power supply land connected to the substrate.
According to this configuration, power can be supplied from the substrate to the semiconductor chip via the external power supply board structure.
In the semiconductor device, the semiconductor chip may have a rectangular shape as viewed in plan, the outer power supply plate structure may be arranged to surround an outer peripheral portion of the rectangular semiconductor chip, and the first power supply land and the second power supply land may be arranged at positions on extension lines of diagonals of the rectangular shape.
According to this configuration, by providing the first power supply land and the second power supply land at positions on the extension line of the diagonal line of the semiconductor chip, a space for signal wiring from the semiconductor chip to the substrate can be easily secured, whereby signal wiring to the substrate can be easily designed.
In the semiconductor device, the first power supply plate and the third power supply plate, the second power supply plate and the fourth power supply plate, and the second insulating film and the third insulating film may be respectively arranged on the same plane.
According to this configuration, the respective power supply boards and the respective insulating films can be formed on the same plane simultaneously and collectively. Therefore, the manufacturing steps for the chip internal power board structure and the chip external power board structure can be reduced.
According to the present invention, in a semiconductor device having a semiconductor chip (LSI) flip-chip mounted on a substrate, an inner power supply board structure is provided in an inner region of a peripheral electrode pad of the semiconductor chip, whereby a wiring system noise reduction effect and a shielding effect can be improved, and a low impedance of a power supply during a high frequency operation of the LSI can be realized.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment;
fig. 2 is a partial plan view of the semiconductor device viewed from the relay board side;
FIG. 3 is a schematic plan view showing the relationship between the power board structure and the LSI chip;
fig. 4 is a graph showing the frequency characteristic of the S parameter;
fig. 5 is a sectional view illustrating a manufacturing step of a semiconductor device;
fig. 6 is a sectional view illustrating a manufacturing step of a semiconductor device;
fig. 7 is a sectional view illustrating a manufacturing step of a semiconductor device;
fig. 8 is a sectional view illustrating a manufacturing step of a semiconductor device;
fig. 9 is a sectional view illustrating a manufacturing step of the semiconductor device;
fig. 10 is a sectional view illustrating a manufacturing step of a semiconductor device;
fig. 11 is a sectional view illustrating a manufacturing step of a semiconductor device;
fig. 12 is a partial sectional view illustrating the manner of connection of the power supply pads at the center portion of the LSI chip;
fig. 13 is a partial sectional view illustrating the manner of connection of the ground plate at the center portion of the LSI chip;
fig. 14 is a schematic plan view illustrating the relationship of a power board structure and an LSI chip of a semiconductor device according to a second embodiment;
fig. 15 is a schematic plan view illustrating the relationship of another power board structure and LSI chip of the second embodiment; and
fig. 16 is a schematic plan view illustrating the relationship between another power board structure and an LSI chip of the second embodiment.
Detailed Description
First embodiment
A first embodiment will be explained with reference to fig. 1 to 13.
1. Structure of semiconductor device
As shown in fig. 1, the
The inboard
The power
Fig. 1 corresponds to a cross-sectional view of a
As shown in fig. 3, the
On the mounting
The power
The
Therefore, the inner
Fig. 4 is a graph showing an example of a simulation result of the frequency characteristic of the S parameter (impedance) relating to the general mesh power supply wiring structure and the power supply board structure according to the present embodiment. As shown in fig. 4, superiority of the power supply impedance characteristic provided by the power supply board structure with respect to the mesh power supply wiring structure can be observed in all frequency regions (10MHz to 50 GHz). It has been confirmed through simulation that the power supply board structure greatly contributes to lowering the impedance of the power supply of the LSI chip, particularly in the frequency region (high frequency region) of 1GHz or more.
Simulation conditions for the mesh power supply wiring structure include: a wiring material of Al; 1 μm upper and lower Al wiring thickness; a wiring width of 30 μm; a wiring pitch of 60 μm;
upper/lower wiring gaps of (1); a relative dielectric constant of 3.8 of the insulating film between the upper/lower wirings; and the simulation area has the same area as the power board structure. The simulation conditions for the power board structure include: a plate material of Al; the thickness of the upper and lower Al plates is 3 μm; longitudinal and transverse widths of the plate of 390 μm, respectively; a plate gap of 0.4 μm; and a relative dielectric constant of 20 for the insulating film between the plates.As shown in fig. 1, the relay board 1 includes: a plurality of
The
As shown in fig. 1 and 2, a plurality of
As shown in fig. 1 and 2, on the
The
As shown in fig. 1, a plurality of
The via 31 and the
The
The power
The
2. Semiconductor device manufacturing method
Referring to fig. 5 to 13, a method of manufacturing the
First, as shown in fig. 5, in the peripheral portion of the mounting
At this time, in the region including the power
Subsequently, as shown in fig. 6, on the power
Subsequently, the inner
As shown in fig. 7, as the inner power
As shown in fig. 8, on the
As shown in fig. 9, on the
Subsequently, on the
As shown in fig. 11, the
Fig. 12 shows the manner of electrical connection between the
Similarly, fig. 13 shows the manner of electrical connection between the micro gold bumps 8B of the relay board 1 and the
Subsequently, solder balls 4 for external connection are formed on the
The order of manufacturing the
3. Effect of the first embodiment
According to the present embodiment, the power supply path for supplying power to the
Specifically, on the protective film 22 (thickness: about 1 μm) of the
The power
At this time, power is supplied from the relay board 1 to the
Power supply from the relay board 1 to the
Second embodiment
A second embodiment will now be explained with reference to fig. 14 to 16. In the following description, portions similar to those of the first embodiment will be designated by similar symbols and the description thereof will be omitted for the purpose of simplifying the description.
According to the second embodiment, an example will be explained in which a power supply board structure for providing power supply wiring and a bypass capacitor is additionally provided outside the area of the
The outside
Similarly, the outer
Similarly, the outside
Similarly, the outside
As shown in fig. 14, each of the third power supply boards (51,61,71,81) includes a first power supply land (54A,64A,74A,84A) connected to the relay board 1, and each of the fourth power supply boards (53,63,73,83) includes a second power supply land (54B,64B,74B,84B) connected to the relay board 1. Power is supplied from the relay board 1 to each of the outside power board structures (50,60,70,80) via each of the first and second power lands.
In the second embodiment, in the respective power supply board structures, the first
4. Effect of the second embodiment
According to the second embodiment, power can also be supplied from the relay board 1 to the
5. Other examples of the second embodiment
The outside power strip structure is not limited to the example shown in fig. 14, and may be implemented as in the case shown in fig. 15, for example. Fig. 15 shows an outboard
The outer
The third
Further, as shown in fig. 15, at four positions along the diagonal line of the
The formation manner of the
In the case of this example, the inner
Also, as shown in fig. 16, the first
The first
Other embodiments
The present invention is not limited to the embodiments described with reference to the drawings, and the following embodiments, for example, may be included within the technical scope of the present invention.
(1) In an embodiment, the power supply voltage plate is a first power supply plate and the ground plate is a second power supply plate. However, this is merely an example, and the supply voltage plate may be the second supply plate and the ground plate may be the first supply plate. The same applies to the third power supply board and the fourth power supply board.
(2) In the embodiment, the relay board (interposer) 1 is described as a substrate on which a semiconductor chip is flip-chip mounted, for example. However, the substrate is not limited to the relay board, and may be a double-sided circuit substrate.
(3) In the embodiment, the plurality of
(4) In the embodiments, the respective power supply board structures of the present application are applied to LSI chips including a general mesh power supply wiring structure. However, it is not limited thereto, and the power supply board structure of the present application may be applied to an LSI chip that does not include a general mesh power supply wiring structure.
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