阅读说明：本技术 阻变式存储器的制造方法和阻变式存储器 (Resistive random access memory and manufacturing method thereof ) 是由 姚国峰 沈健 于 2018-04-03 设计创作，主要内容包括：本发明提供一种阻变式存储器的制造方法和阻变式存储器,该方法,包括：在绝缘层上硅SOI晶圆上设置填充多晶硅的深沟槽,得到带有深沟槽的SOI晶圆；其中,深沟槽贯穿SOI晶圆的硅器件层、埋氧层,并抵达支撑层；在带有深沟槽的SOI晶圆上制作互补金属氧化物半导体CMOS电路,得到包含CMOS电路的SOI晶圆；将包含CMOS电路的SOI晶圆的支撑层减薄至埋氧层的表面,并在填充多晶硅的深沟槽的顶端位置形成凹槽；在SOI晶圆的埋氧层上制作忆阻器。从而实现RRAM标准CMOS电路制作工艺与忆阻器制作工艺的分离,使得在RRAM的规模化生产过程中引入贵金属作为忆阻器的电极,从而提高RRAM中忆阻器的电学存储特性。(The invention provides a manufacturing method of a resistive random access memory and the resistive random access memory, wherein the method comprises the following steps: arranging a deep groove filled with polysilicon on the silicon-on-insulator (SOI) wafer on the insulating layer to obtain the SOI wafer with the deep groove; the deep groove penetrates through a silicon device layer and an oxygen embedding layer of the SOI wafer and reaches the supporting layer; manufacturing a complementary metal oxide semiconductor CMOS circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit; thinning a supporting layer of an SOI wafer containing a CMOS circuit to the surface of a buried oxide layer, and forming a groove at the top end of a deep groove filled with polysilicon; and manufacturing a memristor on a buried oxide layer of the SOI wafer. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and the noble metal is introduced to serve as the electrode of the memristor in the RRAM large-scale production process, so that the electrical storage characteristic of the memristor in the RRAM is improved.)

A method for manufacturing a resistive random access memory includes:

arranging a deep groove filled with polysilicon on the silicon-on-insulator (SOI) wafer on the insulating layer to obtain the SOI wafer with the deep groove; the deep groove penetrates through a silicon device layer and an oxygen burying layer of the SOI wafer and reaches the supporting layer;

manufacturing a complementary metal oxide semiconductor CMOS circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit;

thinning the support layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon;

and manufacturing a memristor on a buried oxide layer of the SOI wafer, wherein a lower electrode of the memristor is manufactured in the groove.

The method of claim 1, wherein the providing the deep trench filled with polysilicon on the silicon-on-insulator (SOI) wafer to obtain the SOI wafer with the deep trench comprises:

sequentially growing a pad oxide layer, a pad nitride layer and a hard mask layer on a silicon device layer of the silicon-on-insulator (SOI) wafer;

forming a deep trench on the SOI wafer by a reactive ion etching method, wherein the deep trench comprises: the memory cell region deep groove and the peripheral circuit region deep groove; the storage unit area deep groove and the peripheral circuit area deep groove penetrate through a silicon device layer and an oxygen burying layer of the SOI wafer and reach the supporting layer;

removing the hard mask layer of the SOI wafer with the deep groove by adopting a wet etching mode, and carrying out thermal oxidation on the SOI wafer with the deep groove so as to form a layer of liner silicon oxide with preset thickness on the silicon surface of the deep groove;

filling the deep groove with polysilicon for the first time, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep groove so as to form a groove region on the upper surface of the polysilicon in the deep groove and the surface of the silicon device layer;

performing high-energy ion implantation to the periphery of the groove region according to a preset inclination angle to form an embedded connecting band; wherein the doping type of the ions is the same as that of the polysilicon;

and after removing the liner silicon oxide on the side wall around the groove region by adopting a wet etching mode, performing polysilicon filling on the deep groove for the second time, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep groove so as to enable the depth between the upper surface of the polysilicon in the deep groove and the upper surface of the silicon device layer to be less than or equal to a preset threshold value.

The method of claim 1, wherein fabricating Complementary Metal Oxide Semiconductor (CMOS) circuits on the SOI wafer with deep trenches comprises:

manufacturing electronic devices required in the CMOS circuit and metal interconnection among the electronic devices on the SOI wafer with the deep grooves; the electronic device includes: a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, a capacitor and a resistor; the metal interconnection includes: the silicon nitride insulating layer, the dielectric layer before metal deposition, the contact hole, the intermetallic dielectric layer, the metal layer and the through hole; the metal interconnection is used for connecting the electronic devices so as to electrically connect the electronic devices with each other to form a CMOS circuit.

The method of claim 1, wherein thinning the support layer of the SOI wafer containing CMOS circuitry to the surface of the buried oxide layer and forming a recess at a top location of the deep trench filled with polysilicon comprises:

temporarily bonding one side of the SOI wafer containing the CMOS circuit with a first carrier wafer, wherein the first carrier wafer is used for supporting the SOI wafer with the deep grooves;

thinning the supporting layer of the SOI wafer containing the CMOS circuit so as to enable the thickness of the supporting layer to be within a preset range;

removing the rest supporting layer and part of polysilicon in the deep trench by adopting an etching process so as to enable the surface of the polysilicon in the deep trench and the surface of the buried oxide layer to form a groove with a preset depth range, wherein the etching process comprises the following steps: dry etching and wet etching; and the etching speed of the etching process to silicon is greater than that to silicon oxide.

The method of claim 1, wherein fabricating a memristor on a buried oxide layer of the SOI wafer comprises:

manufacturing a lower electrode of the memristor in the groove;

manufacturing a resistance layer of the memristor on the oxygen burying layer and a lower electrode of the memristor;

and manufacturing an upper electrode of the memristor above the resistance layer.

The method of claim 5, wherein fabricating a lower electrode of a memristor within the recess comprises:

depositing a metal layer with a preset thickness on the surface of the buried oxide layer, wherein the metal layer is made of the following materials: iridium, palladium, gold, platinum, ruthenium; the deposition mode comprises the following steps: chemical vapor deposition, evaporation and sputtering;

and removing the metal layer on the surface of the buried oxide layer by adopting an ion beam etching process, and only leaving the metal layer in the groove, wherein the metal layer in the groove forms a lower electrode of the memristor.

The method of claim 5, wherein fabricating a resistive layer of the memristor on the buried oxide layer and a lower electrode of the memristor comprises:

depositing a resistance layer on the buried oxide layer, wherein the resistance layer is made of the following materials: hafnium oxide, HfOx, titanium oxide, TiOx, tantalum oxide, TaOx, niobium oxide, NbOx, zirconium oxide, ZrOx, scandium oxide, ScOx, yttrium oxide YOx, nickel oxide, NiOx, tungsten oxide, and vanadium oxide, VOx;

and removing the resistance layer above the deep trench in the peripheral circuit region by photoetching and etching processes.

The method of claim 5, wherein fabricating an upper electrode of a memristor over the resistive layer comprises:

depositing an upper electrode layer with a preset thickness on the resistance layer, wherein the material of the upper electrode layer comprises: tantalum Ta, hafnium Hf, titanium Ti, tungsten W, chromium Cr, nickel Ni.

The method of claim 8, further comprising, after depositing an upper electrode layer of a predetermined thickness on the resistive layer:

depositing a conductive layer with a preset thickness on the upper electrode layer, wherein the conductive layer comprises the following materials: aluminum, titanium, copper;

and depositing a silicon oxide dielectric layer on the surface of the conducting layer in a PECVD (plasma enhanced chemical vapor deposition) mode, and flattening the upper surface of the silicon oxide dielectric layer.

The method of claim 9, wherein after depositing a silicon oxide dielectric layer on the surface of the conductive layer by PECVD and planarizing the top surface of the silicon oxide dielectric layer, further comprising:

bonding the upper surface of the silicon oxide dielectric layer with a second carrier wafer, and releasing the temporary bonding of the front surface of the SOI wafer containing the CMOS circuit and the first carrier wafer;

determining a target position of an aluminum bonding pad required to be arranged on one surface of the SOI wafer containing the CMOS circuit;

removing the dielectric layer on the target position by photoetching and etching processes until the metal layer under the dielectric layer is exposed;

manufacturing an aluminum bonding pad on the target position;

arranging a passivation layer on one surface of the SOI wafer containing the CMOS circuit and the aluminum bonding pad;

and removing the passivation layer on the aluminum bonding pad to obtain a welding spot, wherein the welding spot is used for connecting an external circuit.

The method of claim 5, after fabricating an upper electrode of a memristor over the resistive layer, further comprising:

determining a target position of an aluminum bonding pad required to be arranged on the other surface of the SOI wafer containing the CMOS circuit;

forming an opening structure on the target position by adopting photoetching and etching processes, wherein the bottom of the opening structure reaches a metal layer of the CMOS circuit;

depositing a silicon oxide isolation layer on the other surface, the bottom surface and the side wall of the opening structure of the SOI wafer containing the CMOS circuit, wherein the silicon oxide isolation layer is used for isolating a silicon device layer;

removing the silicon oxide isolation layer on the surface of the upper electrode of the memristor and at the bottom of the opening structure by adopting photoetching and etching processes;

sequentially arranging a redistribution layer and a passivation layer on the other surface, the bottom surface and the side wall of the opening structure of the SOI wafer containing the CMOS circuit; wherein, the material of redistribution layer includes: aluminum;

and removing the passivation layer on the bottom surface of the opening structure to obtain a welding spot, wherein the welding spot is used for connecting an external circuit.

The method of claim 1, wherein the providing the deep trench filled with polysilicon on the silicon-on-insulator (SOI) wafer to obtain the SOI wafer with the deep trench comprises:

growing a pad oxide layer, a pad nitride layer and a hard mask layer on the SOI wafer;

forming a deep groove on the SOI wafer in a reactive ion etching mode; the deep groove penetrates through a silicon device layer and an oxygen burying layer of the SOI wafer and reaches the supporting layer;

removing the hard mask layer of the SOI wafer with the deep groove by adopting a wet etching mode, and carrying out thermal oxidation on the SOI wafer with the deep groove so as to form a layer of liner silicon oxide with preset thickness on the silicon surface of the deep groove;

filling the deep groove with polysilicon, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep groove so as to form a groove region on the upper surface of the polysilicon in the deep groove and the surface of the silicon device layer; the polysilicon in the deep groove is connected with one end of a common contact hole, one end of the common contact hole is also connected with a source electrode of a transistor in the CMOS circuit, and the other end of the common contact hole is connected with a metal layer of metal interconnection in the CMOS circuit.

A resistance change memory manufactured by applying the method for manufacturing a resistance change memory according to any one of claims 1 to 12, comprising: a storage unit and an access control unit;

the storage unit comprises a lower electrode, a resistance layer and an upper electrode, and the access control unit comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET); wherein:

the access control unit is manufactured on one surface of a silicon-on-insulator (SOI) wafer, the storage unit is manufactured on the other surface of the SOI wafer, and the access control unit is connected with a lower electrode of the storage unit through a deep groove filled with polycrystalline silicon on the SOI wafer.

The RRAM of claim 13, wherein the lower electrode of the memory cell is formed in a trench formed by the buried oxide layer and the deep trench of the SOI wafer, and the material of the lower electrode comprises: iridium, palladium, gold, platinum, ruthenium; the material of the upper electrode layer comprises: tantalum Ta, hafnium Hf, titanium Ti, tungsten W, chromium Cr, nickel Ni; the material of the resistance layer comprises: hafnium oxide HfOx, titanium oxide TiOx, tantalum oxide TaOx, niobium oxide NbOx, zirconium oxide ZrOx, scandium oxide ScOx, yttrium oxide YOx, nickel oxide NiOx, tungsten oxide WOx, and vanadium oxide VOx.