阅读说明：本技术 一种芯片及电子设备 (A kind of chip and electronic equipment ) 是由 林峰 于 2019-09-16 设计创作，主要内容包括：本申请提供了一种芯片,其包括：基板、设置在所述基板上的晶圆裸片以及设置在所述基板上的一个或多个静电防护元件。所述静电防护元件位于所述晶圆裸片的外围用于为晶圆裸片提供静电防护。所述晶圆裸片包括距离基板最远的顶面,所述静电防护元件距离基板最远的部分低于所述晶圆裸片的顶面。(This application provides a kind of chips comprising: the one or more electrostatic protection elements of wafer bare die and setting on the substrate of substrate, setting on the substrate.The periphery that the electrostatic protection element is located at the wafer bare die is used to provide electrostatic protection for wafer bare die.The wafer bare die includes the top surface farthest apart from substrate, the electrostatic protection element top surface partially below the wafer bare die farthest apart from substrate.)

1. a kind of chip characterized by comprising substrate is arranged wafer bare die on the substrate and is arranged described One or more electrostatic protection elements on substrate, the electrostatic protection element are located at the periphery of the wafer bare die, for for The wafer bare die provides electrostatic protection, and the wafer bare die includes the top surface farthest apart from substrate, the electrostatic protection element The top surface partially below the wafer bare die farthest apart from substrate.

2. chip as described in claim 1, which is characterized in that institute is arranged in multiple electrostatic protection elements end to end State the periphery of wafer bare die.

3. chip as claimed in claim 2, which is characterized in that be provided with pad, the electrostatic protection element on the substrate Opposite end pass through the pad respectively and be connected to substrate, multiple electrostatic protection elements join end to end refer to it is adjacent Respectively hithermost one end is connected with each other two electrostatic protection elements by common pad.

4. chip as claimed in claim 1 or 2, which is characterized in that the wafer bare die include the bottom surface being connected with substrate, The top surface that is oppositely arranged with the bottom surface and the one or more sides for connecting the top and bottom, at least one described side Electrostatic protection element with two layers or two layers or more is oppositely arranged, different electrostatic protection element layers and the opposite side it Between projector distance it is different, the electrostatic protection element layer is an electrostatic protection element or including multiple electrostatic Protective element；Or

The wafer bare die includes the bottom surface being connected with substrate, the top surface being oppositely arranged with the bottom surface and connect the top surface With one or more sides of bottom surface, the periphery of the wafer bare die, the wafer bare die is arranged in the electrostatic protection element At least one side and an electrostatic protection element be oppositely arranged or with end to end multiple electrostatic protections Element is oppositely arranged；Or

The wafer bare die includes the bottom surface being connected with substrate, the top surface being oppositely arranged with the bottom surface and connect the top surface With one or more sides of bottom surface, the electrostatic protection element is configured for one week around the wafer bare die, with the crystalline substance Each side of circle bare die keeps opposite；Or

The wafer bare die includes the bottom surface being connected with substrate, the top surface being oppositely arranged with the bottom surface and connect the top surface With one or more sides of bottom surface, the wafer bare die is in the position where wherein one or more sides by beating conductor wire Mode be electrically connected with substrate, the electrostatic protection element be arranged in the wafer bare die do not beat conductor wire side it is outer It encloses, and the side for not beating conductor wire with the wafer bare die is kept relatively.

5. chip as claimed in claim 1 or 2, which is characterized in that the wafer bare die include the bottom surface being connected with substrate, The top surface that is oppositely arranged with the bottom surface and the one or more sides for connecting the top and bottom, the chip include two Or more than two electrostatic protection element sections, each electrostatic protection element section include one or more electrostatic protection elements, The electrostatic protection element section is separately positioned on two or more not opposite positions of ipsilateral with wafer bare die, described The wafer bare die not ipsilateral opposite with the electrostatic protection element section is not attached to each other；Or

The wafer bare die is connected each other with the not ipsilateral that the electrostatic protection element section is oppositely arranged, wherein with difference The electrostatic protection element section that is oppositely arranged respectively of side between be connected with each other；Or

The wafer bare die is connected each other with the not ipsilateral that the electrostatic protection element section is oppositely arranged, wherein with difference The electrostatic protection element section that is oppositely arranged respectively of side between be not attached to.

6. chip as claimed in claim 1 or 2, which is characterized in that the wafer bare die include the bottom surface being connected with substrate, The top surface that is oppositely arranged with the bottom surface and the one or more sides for connecting the top and bottom, the electrostatic protection element It is oppositely arranged with the side, the spanning length of each electrostatic protection element is less than, is equal to or is greater than on the other side The length of the side.

7. chip as described in claim 1, which is characterized in that the chip is for sensing finger print information, the electrostatic protection Element is connected directly or indirectly to ground.

8. chip as described in claim 1, which is characterized in that the substrate is printed circuit board, the electrostatic protection element Pass through the circuit connection on printed circuit board to ground；Or

The substrate is insulating substrate, and the electrostatic protection element is connected by the flexible circuit board being connected on the insulating substrate It is connected to ground.

9. chip as described in claim 1, which is characterized in that the electrostatic protection element is electrostatic conductor, the static guiding The opposite end of line is connected to substrate by way of routing respectively with static electricity discharge.

10. a kind of electronic equipment, which is characterized in that including shell and the chip being arranged in or beyond housing openings inside shell, The chip is chip described in any one of claim 1-9, and the electronic equipment is sensed according to the chip The information of external object executes corresponding function.

Technical field

The application belongs to optical technical field more particularly to a kind of chip and electronic equipment.

Background technique

As electronic equipment is more and more light and portable, has become people and like belongings.Therefore, very much Chip is started setting up on electronic equipment all to sense the information of user, preferably exchange and interact between user to realize. The chip is generally required through user in contact with or close to implementing to sense.However, when user is in contact with or close to chip, people Body electrostatic can damage chip, and chip senses efficiency is caused to reduce or fail.

Summary of the invention

In order to solve the above technical problems, the application provides a kind of new-type chip and electronic equipment.

The application embodiment provides a kind of chip comprising: substrate, setting wafer bare die on the substrate and One or more electrostatic protection elements on the substrate are set, and the electrostatic protection element is located at the outer of the wafer bare die It encloses, for providing electrostatic protection for the wafer bare die, the wafer bare die includes the top surface farthest apart from substrate, the electrostatic The protective element top surface partially below the wafer bare die farthest apart from substrate.

In some embodiments, the outer of the wafer bare die is arranged in multiple electrostatic protection elements end to end It encloses.

In some embodiments, pad, the opposite end difference of the electrostatic protection element are provided on the substrate It is connected to substrate by the pad, multiple electrostatic protection elements, which join end to end, refers to two adjacent electrostatic protection members Respectively hithermost one end is connected with each other part by common pad.

In some embodiments, the wafer bare die includes the bottom surface being connected with substrate, opposite with the bottom surface sets One or more sides of the top surface set and the connection top and bottom, at least one described side with two layers or two layers or more Electrostatic protection element be oppositely arranged, the projector distance between different electrostatic protection element layers and the opposite side is not Together, the electrostatic protection element layer is for an electrostatic protection element or including multiple electrostatic protection elements.

In some embodiments, the wafer bare die includes the bottom surface being connected with substrate, opposite with the bottom surface sets One or more sides of the top surface and the connection top and bottom set, the electrostatic protection element setting are naked in the wafer The periphery of piece, at least one side of the wafer bare die be oppositely arranged with an electrostatic protection element or with head and the tail phase Multiple electrostatic protection elements even are oppositely arranged.

In some embodiments, the wafer bare die includes the bottom surface being connected with substrate, opposite with the bottom surface sets One or more sides of the top surface and the connection top and bottom set, the electrostatic protection element surround the wafer bare die It is configured within one week, keeps opposite with each side of the wafer bare die.

In some embodiments, the wafer bare die includes the bottom surface being connected with substrate, opposite with the bottom surface sets One or more sides of the top surface set and the connection top and bottom, the wafer bare die one or more sides wherein The position at place is electrically connected by way of beating conductor wire with substrate, and the electrostatic protection element setting does not have in the wafer bare die There is the periphery for the side for beating conductor wire, and the side for not beating conductor wire with the wafer bare die is kept relatively.

In some embodiments, the wafer bare die includes the bottom surface being connected with substrate, opposite with the bottom surface sets One or more sides of the top surface and the connection top and bottom set, the chip include that two or more electrostatic are anti- Protection element section, each electrostatic protection element section include one or more electrostatic protection elements, the electrostatic protection element Section is separately positioned on the position opposite with two or more not ipsilaterals of wafer bare die, the wafer bare die with it is described The not ipsilateral that electrostatic protection element section is oppositely arranged is not attached to each other；Or

The wafer bare die is connected each other with the not ipsilateral that the electrostatic protection element section is oppositely arranged, wherein with It is connected with each other between the electrostatic protection element section that different sides is oppositely arranged respectively；Or

The wafer bare die is connected each other with the not ipsilateral that the electrostatic protection element section is oppositely arranged, wherein with It is not attached between the electrostatic protection element section that different sides is oppositely arranged respectively.

In some embodiments, the wafer bare die includes the bottom surface being connected with substrate, opposite with the bottom surface sets One or more sides of the top surface and the connection top and bottom set, the electrostatic protection element is opposite with the side to be set Set, the spanning length of each electrostatic protection element is less than, be equal to or greater than wafer bare die on the other side side length Degree.

In some embodiments, the electrostatic protection element is connected directly or indirectly to ground.

In some embodiments, the substrate is printed circuit board, and the electrostatic protection element passes through printed circuit board On circuit connection to ground；Or

The substrate is insulating substrate, and the electrostatic protection element passes through the flexible circuit that is connected on the insulating substrate Plate is connected to the ground.

It in some embodiments, further comprise packaging body, for encapsulating the wafer bare die and electrostatic protection element, And the gap between the filling wafer bare die and electrostatic protection element.

In some embodiments, the chip is optical profile type sensing chip, capacitive sensing chip, ultrasonic type sensing One of chip is a variety of.

In some embodiments, the electrostatic protection element is electrostatic conductor, the opposite end point of the electrostatic conductor Substrate is not connected to by way of routing with static electricity discharge.

The application embodiment provides a kind of electronic equipment comprising shell and setting are in or beyond the housing openings in shell The chip in portion.The chip is chip provided by above-mentioned any one embodiment.The electronic equipment is according to the chip institute The information of the external object sensed executes corresponding function.

It in some embodiments, further comprise power supply, the electrostatic protection element is directly or indirectly attached to institute State the positive or negative pole of power supply.

Compared with prior art, chip provided herein, which is used, is arranged a plurality of join end to end in the periphery of wafer bare die Electrostatic protection element mode, can be formed with the longer electrostatic protection element and cover the wafer bare die surrounding Biggish range, so that the electrostatic to come from all directions can be guided by the electrostatic protection element without getting to wafer On bare die, the antistatic capacity of the electrostatic protection element is improved.

The additional aspect and advantage of the application embodiment will be set forth in part in the description, partially will be from following Become obvious in description, or is recognized by the practice of the application embodiment.

Detailed description of the invention

Fig. 1 is the front schematic view for the electronic equipment that the application embodiment provides.

Fig. 2 is the structural schematic diagram of the chip of electronic equipment described in Fig. 1.

Fig. 3 is the overlooking structure diagram of one of embodiment of the electrostatic protection element of chip described in Fig. 2.

Fig. 4 is the overlooking structure diagram of the electrostatic protection element for the chip that another embodiment of the application provides.

Fig. 5 is the overlooking structure diagram of the electrostatic protection element for the chip that another embodiment of the application provides.

Fig. 6 is the overlooking structure diagram of the electrostatic protection element for the chip that another embodiment of the application provides.

Fig. 7 is the overlooking structure diagram of the electrostatic protection element for the chip that another embodiment of the application provides.

Fig. 8 is the overlooking structure diagram of the electrostatic protection element for the chip that another embodiment of the application provides.

Fig. 9 is the plan structure signal of the electrostatic protection element for the chip that another embodiment of the application provides Figure.

Figure 10 is the overlooking structure diagram of the electrostatic protection element for the chip that another embodiment of the application provides.

Specific embodiment

Presently filed embodiment is described below in detail, the example of the embodiment is shown in the accompanying drawings, wherein from beginning Same or similar element or element with the same or similar functions are indicated to same or similar label eventually.Below by ginseng The embodiment for examining attached drawing description is exemplary, and is only used for explaining the application, and should not be understood as the limitation to the application.In In the description of the present application, it is to be understood that term " first ", " second " are only used for describing, and should not be understood as instruction or dark Show relative importance or implicitly indicates the quantity of indicated technical characteristic or put in order.Define as a result, " first ", The technical characteristic of " second " can explicitly or implicitly include one or more technical characteristic.In retouching for the application In stating, the meaning of " plurality " is two or more, unless otherwise specifically defined.

In the description of the present application, it should be noted that unless otherwise specific regulation or limit, term " installation ", " phase Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integration connection；It can To be mechanical connection, it is also possible to be electrically connected or is in communication with each other；It can be directly connected, the indirect phase of intermediary can also be passed through Even, the connection inside two elements or the interaction relationship between two elements be can be.For the ordinary skill of this field For personnel, the concrete meaning of above-mentioned term in this application can be understood as the case may be.

Following disclosure provides many different embodiments or example is used to realize the different structure of the application.In order to Simplify disclosure herein, hereafter only to the component of specific examples and being set for describing.Certainly, they are merely examples, and And purpose does not lie in limitation the application.

In addition, the application can reuse reference number and/or reference letter, this reuse in different examples It is itself not indicated between the various embodiments discussed and/or setting to simplify and clearly state the application Particular kind of relationship.In addition, provided various specific techniques and material are only to realize the application skill to the application in the following description The example of art scheme, but those of ordinary skill in the art should be aware that the technical solution of the application can also be by hereafter not Other techniques and/or other materials of description are realized.

Further, described feature, structure can be incorporated in one or more embodiment party in any suitable manner In formula.In the following description, many details are provided so as to fully understand presently filed embodiment.However, this Field technical staff will be appreciated that even if without one or more in the specific detail, or using other structures, group Member etc. can also practice the technical solution of the application.In other cases, it is not shown in detail or describes known features or operation To avoid the emphasis of fuzzy the application.

As shown in Figure 1, the application embodiment provides a kind of electronic equipment 1.The electronic equipment 1 is such as, but not limited to Consumer electrical product or household electric product or vehicle electronics product.Wherein, consumer electrical product is, for example, mobile phone, notes The electronic product of the types of applications detection technology such as this computer, tablet computer, e-book, personal digital assistant, wearable device.Family The formula electronic product of residence is, for example, the electronic product of the types of applications detection technology such as intelligent door lock, TV, refrigerator.Vehicular electronics produces Product are, for example, touch-control interactive screen, door handle etc..

The electronic equipment 1 includes shell 10 and chip 12.The chip 12 is used for the contact by external object or connects Recently the relevant information of the external object is sensed, it is such as, but not limited to, fingerprint, palmmprint, ear line, heart rate, blood oxygen, blood pressure, quiet One of arteries and veins, distance are a variety of.The electronic equipment 1 can execute corresponding function according to the sensing result of the chip 12 Energy.Corresponding function includes but is not limited to be solved after identifying the identity of the external object according to the information sensed It locks, pay, starting preset application program, the preset function of activation, or the heart rate and blood oxygen of the acquisition external object contain The combination of any one or more in the moods and health condition of the biological informations to judge external object such as amount.The core Piece 12 can be one of optical profile type sensing chip, capacitive sensing chip, ultrasonic type sensing chip or a variety of.

In the example of fig. 1, the electronic equipment 1 is mobile phone.The front of mobile phone, which is provided with, combines the aobvious of touch module Showing device 14.The part being located at other than display device 14 below the front shroud 16 of electronic equipment 1 is arranged in the chip 12.So And in other change embodiments, inside or display dress in the display device 14 also can be set in the chip 12 Set 14 lower section.In addition, that front, the back side and side of electronic equipment 1 etc. can also be arranged in is multiple and different for the chip 12 Position.Through-hole (not shown) can be offered on the shell 10.The chip 12 is arranged in the through-hole of shell 10, with logical Cross the outer surface that the through-hole is exposed to electronic equipment 1.The chip 12 also can be set in the inside of electronic equipment 1, such as Inside positioned at the shell 10 is without exposing to the open air in the outer surface of electronic equipment 1.

As shown in Fig. 2, the chip 12 include substrate 120, the wafer bare die 122 that is arranged on the substrate 120 and One or more electrostatic protection elements 124 on the substrate 120 are set.The opposite end of the electrostatic protection element 124 It is respectively connected to substrate 120.The electrostatic protection element 124 is used for static electricity discharge.The electrostatic protection element 124 is arranged in institute State the periphery of wafer bare die 122.The electrostatic protection element 124 is directly or indirectly attached to ground, will be from the quiet of the external world Electricity is released, and is damaged to prevent electrostatic from getting on wafer bare die 122 to the wafer bare die 122.

The substrate 120 can be transparent substrate or nontransparent substrate.Wherein, the transparent substrate is such as, but not limited to glass Glass substrate, plastic base, crystal, sapphire insulation substrate.The nontransparent substrate is such as, but not limited to silicon substrate, printing electricity Road plate, metal substrate etc..It is understood that the material of the substrate 120 can be rigid, or flexible material Matter, such as fexible film etc..

External circuit 121 is provided on the substrate 120.The external circuit 121 is for externally transmitting signal.The crystalline substance Circle bare die 122 is arranged on substrate 120, and the external circuit 121 of substrate 120 is connected to by conductor wire 123.The wafer bare die 122 include the bottom surface 1220 being connected with substrate 120, the top surface 1222 being oppositely arranged with the bottom surface 1220 and described in connecting The side 1224 of top surface 1222 and bottom surface 1220.The top surface 1222 is the surface farthest apart from substrate 120 of wafer bare die 122. The top surface 1222 is for example a flat surface.Vertical interval between the top surface 1222 and substrate 120 can be defined as the crystalline substance Height h1 of the circle bare die 122 relative to substrate 120.According to the shape of the wafer bare die 122, the side 1224 can be one It is a or multiple.For example, if the wafer bare die 122 be it is cylindric, the side 1224 be a Cylinder Surface, it is not bright thereon Aobvious line of demarcation.If the wafer bare die 122 is quadrangular shape, the wafer bare die 122 includes four sides 1224, respectively court To different directions.

The electrostatic protection element 124 for example can be electrostatic conductor.The electrostatic conductor is by conductive metal material system At the metal material for example can be selected from any one in aluminium, copper, Au Ag Pt Pd, nickel and combinations thereof.The electrostatic Protective element 124 can also be made of other suitable conductive materials.The electrostatic conductor can be arch or arc, to utilize Lightning rod principle attracts the extraneous electrostatic transmitted.The opposite end of the electrostatic conductor is connected to base by way of routing respectively Plate 120 is to fall the electrostatic leakage attracted.

The electrostatic protection element 124 part farthest apart from substrate 120, such as: the top of the electrostatic conductor is lower than The top surface 1222 of the wafer bare die 122.If the electrostatic protection element 124 part farthest from substrate 120 and substrate 120 it Between vertical interval be defined as height h2 of the electrostatic protection element 124 relative to substrate 120, then the electrostatic protection element 124 relative to substrate 120 height h2 be lower than height h1 of the wafer bare die 122 relative to substrate 120.

The chip 12 further includes packaging body 126.The packaging body 126 is for encapsulating the wafer bare die 122 and electrostatic Gap between protective element 124, and the filling wafer bare die 122 and electrostatic protection element 124.The packaging body 126 Material be, for example, epoxy resin or other suitable insulating materials.The encapsulation of the chip 12 can use grid array package The packaged types such as (Land Grid Array, LGA), ball-like pins Background Grid array packages (Ball Grid Array, BGA).So And optionally, the chip 12 can also use other packaged types.The packaging body 126 is higher by 122 He of wafer bare die Electrostatic protection element 124 seals the wafer bare die 122 and electrostatic protection element 124 inside it.The packaging body 126 side surfaces 1260 farthest apart from substrate 120, which are used to receiving, believes because of external object in contact with or close to being formed by input Number, defining the side surface is sensing face 1260.The wafer bare die 122 according to the input signal in contact with or close to outside Object carries out information sensing.Because the resistance of the electrostatic protection element 124 is much smaller than the resistance of the wafer bare die 122, when outer Portion's object contact or when close to the sensing face 1260, the following electrostatic can be preferentially by the lesser electrostatic protection element of resistance 124 attract and are released by the electrostatic protection element 124, enter the wafer bare die 122 so as to avoid electrostatic And wafer bare die 122 is damaged.

If the electrostatic protection element 124 is arranged higher than 122 top surface 1222 of wafer bare die, because of institute in encapsulation process It states and interacts between 124 meeting of electrostatic protection element and the packaging body 126 of flowing, so that the different electrostatic protection elements Different degrees of change occurs for 124 height, and the top for completing to have individual static protective element 124 after encapsulation is higher than other The case where 124 top of electrostatic protection element.The highest electrostatic protection element 124 in top is particularly easy to repeat to attract extraneous pass The electrostatic strike come causes the packaging body 126 for being located at highest 124 top of electrostatic protection element in top because of duplicate electrostatic It hits and damages.Electrostatic protection element 124 in the application highly lower than 122 top surface 1222 of wafer bare die can attract originally The electrostatic on the wafer bare die 122 is beaten, the probability that electrostatic is got on wafer bare die 122 can be effectively reduced.Moreover, because described The height of electrostatic protection element 124 itself is lower, span under the same conditions, the whole height of the electrostatic protection element 124 Degree variation can be made more gentle, not will form particularly pertinent part, so that 124 different piece of the electrostatic protection element Attract the probability of electrostatic more average, advantageously reduce electrostatic repeat to hit the same place and caused by cumulative damage.

It is understood that the electronic equipment 1 further includes power supply 18 (referring to Fig. 1) in other change embodiments, Such as: the battery of electronic equipment 1.The electrostatic protection element 124 can also be connected to the electronic equipment 1 to direct or part Power supply 18.The power supply 18 is equivalent to a capacitor, can sponge the electrostatic come is conducted through.The electrostatic protection element 124 can connect to the positive or negative pole of the power supply 18.

Specifically, pad 125 is provided on the substrate 120.The material of the pad 125 for example can selected from aluminium, copper, In Au Ag Pt Pd, nickel any one and combinations thereof.Certainly, the material of the pad 125 can also suitably lead for other Electric material.The electrostatic protection element 124 is connected on the substrate 120 by pad 125.Such as: each electrostatic is anti- Protection element 124 includes opposite both ends, and the opposite end of the electrostatic protection element 124 passes through two on substrate 120 respectively Pad 125 is connected on the substrate 120.Because multiple electrostatic protection elements 124 need to be connected to substrate 120, the base Multiple pads 125 are provided on plate 120 for being connected respectively with multiple electrostatic protection elements 124.The adjacent weldering Interval between disk 125 can be identical, can not also be identical.If the substrate 120 is printed circuit board, pass through printed circuit The pad 125 is connected to the ground or power supply 18 by circuit in plate；If it is not provided with circuit structure on the substrate 120, such as The substrate 120 is insulating substrate, then can be connected pad 125 by the flexible circuit board being arranged on insulating substrate 120 To ground or power supply 18.It is understood that described hereinly including the ground of chip 12, or it is using the chip 12 System or electronic equipment 1 systematically or equipment.Pass through the electrostatic protection element 124 and pad 125 and ground or electricity as a result, Conducting wire between source 18 can release electrostatic guide to the ground or power supply 18 that the external world comes in.

The electrostatic protection element 124 is located at the periphery of the wafer bare die 122, and extremely with the wafer bare die 122 A few side 1224 is oppositely arranged.One or more electrostatic protection elements 124 on substrate 120 orthographic projection it is total Length can be longer than the length of side 1224 corresponding thereto.It is understood that one or more electrostatic protection elements 124 the total length of orthographic projection can also be equal or shorter than the length of side 1224 corresponding thereto on substrate 120.

Optionally, as shown in figure 3, one of side 1224 of the wafer bare die 122 can also with it is multiple described quiet Electric protective element 124 is opposite, and the substrate 120 is arranged in multiple electrostatic protection elements 124 end to end.It is multiple described Electrostatic protection element 124 is arranged end to end refers to two adjacent electrostatic protection elements 124 respectively near mutual One end is connected with each other by common pad 125.The spanning length of each electrostatic protection element 124 can be less than, be equal to Or the length greater than 122 side 1224 of wafer bare die on the other side.The spanning length of the electrostatic protection element 124 can be managed Solution is the length of orthographic projection of the electrostatic protection element 124 on substrate 120.Join end to end setting multiple electrostatic it is anti- Protection element 124 can be considered as the electrostatic protection element 124 of a whole segment length on the whole, can be in the periphery of the wafer bare die 122 Broader region is covered, to increase the chance of guidance electrostatic.It is understood that in other change embodiments, it is more A electrostatic protection element 124 can also be not connected between each other.

Optionally, as shown in figure 4, one of side 1224 of the wafer bare die 122 can be with the electrostatic Protective element 124 is opposite, and the spanning length of one electrostatic protection element 124 can be less than, greater than or equal in contrast 122 side 1224 of wafer bare die length.The spanning length of the electrostatic protection element 124 is longer, then electrostatic protection member The variation of 124 whole height of part can be made gentler, so that 124 different piece of the electrostatic protection element attracts electrostatic Probability is more average.

Optionally, as shown in figure 5, one of side 1224 of the wafer bare die 122 can also be with two layers or two layers Above electrostatic protection element 124 is oppositely arranged.124 layers of different electrostatic protection element and opposite wafer bare die 124 Side 1224 between projector distance it is different.Each 124 layers of described electrostatic protection element can be an electrostatic protection member Part 124 also may include multiple electrostatic protection elements 124.124 layers different of electrostatic protection elements are just being thrown on substrate 120 respectively The total length of shadow may be different or the same, and different 124 layers of electrostatic protection element on the side of wafer bare die 124 1224 Projected position may be different or the same.

Optionally, as shown in fig. 6, the electrostatic protection element 124 can also be separately positioned on two with wafer bare die 122 The opposite position of a or more than two not ipsilaterals 1224.For example, the chip 12 is anti-including two or more electrostatic Protection element section 1240.Each electrostatic protection element section 1240 includes one or more electrostatic protection elements 124.The crystalline substance Circle bare die 122 two or more different sides 1224 respectively with 1240 phase of electrostatic protection element section described at least one To setting.The wafer bare die 122 is connected with each other with the not ipsilateral 1224 that the electrostatic protection element section 1240 is oppositely arranged, It can be not attached between the electrostatic protection element section 1240 being oppositely arranged respectively from different sides 1224.Certainly, such as Fig. 7 It is shown, it can also be connected between the electrostatic protection element section 1240 being oppositely arranged respectively from different sides 1224.It can With understanding, as shown in figure 8, the not ipsilateral that the wafer bare die 122 is opposite with the electrostatic protection element section 1240 1224 can also be parallel to each other or be not attached between each other.The opposite electrostatic is anti-respectively with the disjunct side 1224 It can be connected between protection element section 1240, can also be not attached to.

Optionally, as shown in figure 9, the wafer bare die 122 is logical in the position where wherein one or more sides 1224 The mode of dozen conductor wire 123 is crossed to be electrically connected with the external circuits realization on substrate 120.The setting of electrostatic protection element 124 exists The wafer bare die 122 does not beat the periphery of other one or more sides 1224 of conductor wire 123, and with the side 1224 Holding is oppositely arranged.Because the conductor wire 123 needs to occupy the certain space of 122 periphery of wafer bare die, so if in conduction The electrostatic protection element 124 is arranged again and then will increase the volume of the chip 12 for the periphery of line 123.In the example of figure 9, institute Stating wafer bare die 122 includes substantially vertical four connected sides 1224, respectively first side 1224a, second side 1224b, third side 1224c and the 4th side 1224d.The wafer bare die 122 passes through at first side 1224a wherein The mode of conducting wire is beaten to be electrically connected with the external circuits realization on substrate 120.The wafer bare die 122 does not beat conductor wire 123 The periphery of second side 1224b, third side 1224c and the 4th side 1224d are respectively arranged with one section of electrostatic on the other side Protective element section 1240, the electrostatic protection element section 1240 can be an electrostatic protection element 124, or including multiple head The connected electrostatic protection element 124 of tail.Adjacent electrostatic protection element section 1240 is connected with each other each other, to be formed round institute State one whole section of end to end electrostatic protection element of second side 1224b, third side 1224c and the 4th side 1224d 124。

Optionally, can also be not attached between adjacent electrostatic protection element section 1240, formed respectively with second side 1224, the opposite three sections of separated electrostatic protection element sections 1240 in third side 1224 and the 4th side 1224.

Optionally, be oppositely arranged from the same side 1224 of the wafer bare die 122 can have two layers it is different quiet Electric protective element section 1240 is respectively provided between two layers of different electrostatic protection element section 1240 and opposite side 1224 Different projector distances.

It is understood that the electrostatic protection element 124 can be on the other side along being parallel or generally parallel to The direction of the side 1224 extends, and each section in the electrostatic protection element section 1240 for being arranged in contrast at this time The side 1224 projector distance having the same.Electrostatic protection element 124 in the electrostatic protection element section 1240 can also With along non-parallel to the side 1224 on the other side direction extension, at this time the electrostatic protection element section 1240 for The projector distance of the side 1224 can be considered as each section in the electrostatic protection element section 1240 to the side in contrast The average value of projector distance on face 1224.

Optionally, as shown in Figure 10, in other change embodiments, if the size of the chip 12 allows, the crystalline substance Electrostatic protection element section 1240 on the other side also can be set in 1224 periphery of side for beating conductor wire 123 in circle bare die 122.By This, the electrostatic protection element 124 is configured for 122 1 weeks around the wafer bare die, can be with the wafer bare die 122 Each side 1224 keeps opposite.

The electrostatic protection element 124 is set in the periphery of the wafer bare die 122 around the wafer bare die 122 It sets, the broader range of 122 surrounding of wafer bare die can be covered, so that the electrostatic to come from all directions can be by The electrostatic protection element 124 attracts without getting on wafer bare die 122.

Chip 12 provided herein is lower than wafer by the one or more height of periphery setting in wafer bare die 122 The electrostatic protection element 124 of 122 top surface 1222 of bare die can form height in the larger range of 122 surrounding of wafer bare die Degree changes more gentle electrostatic protection element 124, effectively reduces the probability that electrostatic is got on the wafer bare die 122, Er Qieyou Conducive to reduce electrostatic repeat hit it is same place and caused by cumulative damage.

It should be noted that it will be understood by those skilled in the art that without creative efforts, the application Some or all of embodiment, and the deformation for some or all of embodiment, replacement, change, fractionation, combination, extension Cover Deng being considered as creating thought by present invention, belongs to the protection scope of the application.

In the description of this specification, reference term " embodiment ", " certain embodiments ", " schematically implementation What the description of mode ", " example ", " specific example " or " some examples " etc. meant to describe in conjunction with the embodiment or example Particular features, structures, materials, or characteristics are contained at least one embodiment or example of the application.In this specification In, schematic expression of the above terms are not necessarily referring to identical embodiment or example.Moreover, the specific spy of description Sign, structure, material or feature can be combined in any suitable manner in any one or more embodiments or example.

The foregoing is merely the better embodiments of the application, all the application's not to limit the application Made any modifications, equivalent replacements, and improvements etc., should be included within the scope of protection of this application within spirit and principle.