阅读说明：本技术 一种显示面板和显示装置 (Display panel and display device ) 是由 刘海民 于 2021-08-06 设计创作，主要内容包括：本发明实施例提供一种显示面板和显示装置。显示面板包括显示区和非显示区；非显示区包括第一信号线和多条第二信号线；显示面板包括衬底；第一信号线和多条第二信号线位于衬底的同一侧,第一信号线和第二信号线位于不同层；非显示区还包括第一区,在第一区内：第一信号线的延伸方向和第二信号线的延伸方向相互交叉；第一信号线在衬底所在平面的正投影与多条第二信号线在衬底所在平面的正投影至少部分交叠；第一区设置有静电缓冲单元；静电缓冲单元在衬底所在平面的正投影与第一信号线在衬底所在平面的正投影至少部分交叠。本发明静电缓冲单元能够对第一信号线上的静电进行存储并释放,避免第二信号线被静电击伤,能够提升产品性能可靠性。(The embodiment of the invention provides a display panel and a display device. The display panel comprises a display area and a non-display area; the non-display area comprises a first signal line and a plurality of second signal lines; the display panel includes a substrate; the first signal line and the plurality of second signal lines are positioned on the same side of the substrate, and the first signal line and the second signal lines are positioned on different layers; the non-display area further includes a first area in which: the extending direction of the first signal line and the extending direction of the second signal line are crossed with each other; the orthographic projection of the first signal line on the plane of the substrate is at least partially overlapped with the orthographic projection of the plurality of second signal lines on the plane of the substrate; the first area is provided with an electrostatic buffer unit; the orthographic projection of the electrostatic buffer unit on the plane of the substrate is at least partially overlapped with the orthographic projection of the first signal line on the plane of the substrate. The electrostatic buffer unit can store and release the static electricity on the first signal wire, avoid the second signal wire from being damaged by the static electricity, and improve the reliability of product performance.)

1. A display panel, comprising a display region and a non-display region;

the non-display area comprises a first signal line and a plurality of second signal lines;

the display panel includes a substrate; the first signal line and the plurality of second signal lines are positioned on the same side of the substrate, and the first signal line and the second signal lines are positioned on different layers;

the non-display area further includes a first area in which: the first signal line extends along a first direction, the second signal line extends along a second direction, and the first direction and the second direction are mutually crossed; the orthographic projection of the first signal line on the plane of the substrate at least partially overlaps with the orthographic projection of the plurality of second signal lines on the plane of the substrate; wherein the content of the first and second substances,

the first area is provided with an electrostatic buffer unit; the orthographic projection of the electrostatic buffer unit on the plane of the substrate at least partially overlaps with the orthographic projection of the first signal line on the plane of the substrate.

2. The display panel according to claim 1,

in a third direction, a width of the electrostatic buffer unit is smaller than a width of the second signal line, and the third direction is perpendicular to the second direction.

3. The display panel according to claim 1,

and the electrostatic buffer unit is positioned on at least one side of at least one second signal line along the arrangement direction of the second signal lines.

4. The display panel according to claim 3,

the orthographic projection of the electrostatic buffer unit on the plane of the substrate is positioned between the orthographic projections of the two adjacent second signal lines on the plane of the substrate.

5. The display panel according to claim 4,

the orthographic projection of the electrostatic buffer unit on the plane of the substrate and the orthographic projection of the second signal line on the plane of the substrate are alternately distributed.

6. The display panel according to claim 1,

the electrostatic buffer unit is located on one side of the first signal line close to the substrate.

7. The display panel according to claim 6,

the plurality of second signal lines comprise first sub-signal lines, and the orthographic projection of the first sub-signal lines on the plane of the substrate is adjacent to the orthographic projection of the electrostatic buffer units on the plane of the substrate; the electrostatic buffer unit includes a first unit section;

in the direction perpendicular to the substrate, the first unit section is at a distance d1 from the first signal line, and the first sub-signal line is at a distance d2 from the first signal line, wherein d1 ≦ d 2.

8. The display panel according to claim 7,

the metal layer structure further comprises a first metal layer, a second metal layer and a third metal layer which are positioned on one side of the substrate and are arranged along the direction far away from the substrate; wherein the content of the first and second substances,

the first signal line is located on the third metal layer; the first sub-signal line is located in the first metal layer;

the first cell portion is located in any one of the first metal layer and the second metal layer.

9. The display panel according to claim 7,

the metal layer structure further comprises a first metal layer, a second metal layer and a third metal layer which are positioned on one side of the substrate and are arranged along the direction far away from the substrate; wherein the content of the first and second substances,

the first signal line is located on the third metal layer, and the first sub-signal line is located on the second metal layer;

the first unit portion is located on the second metal layer.

10. The display panel according to claim 7,

the electrostatic buffer unit further comprises a second unit part positioned on one side of the first unit part close to the substrate;

the first cell portion and the second cell portion at least partially overlap in a direction perpendicular to the substrate.

11. The display panel according to claim 10,

the semiconductor layer, the first metal layer, the second metal layer and the third metal layer are arranged on one side of the substrate and along the direction far away from the substrate; wherein the content of the first and second substances,

the first signal line is located on the third metal layer, and the first sub-signal line is located on the second metal layer;

the first cell portion is located in the second metal layer, and the second cell portion is located in the first metal layer or the semiconductor layer.

12. The display panel according to claim 10,

the semiconductor layer, the first metal layer, the second metal layer and the third metal layer are arranged on one side of the substrate and along the direction far away from the substrate; wherein the content of the first and second substances,

the first signal line is located on the third metal layer, and the first sub-signal line is located on the first metal layer;

the first unit part is positioned on the second metal layer, and the second unit part is positioned on the first metal layer; alternatively, the first cell portion is located in the first metal layer, and the second cell portion is located in the semiconductor layer.

13. The display panel according to claim 10,

the first unit section is electrically connected to the first signal line.

14. The display panel according to claim 6,

the plurality of second signal lines comprise first sub-signal lines, and the orthographic projection of the first sub-signal lines on the plane of the substrate is adjacent to the orthographic projection of the electrostatic buffer units on the plane of the substrate;

the electrostatic buffer unit comprises a third unit part and a fourth unit part, wherein the third unit part is positioned on one side of the first sub-signal line close to the substrate, and the fourth unit part is positioned on one side of the third unit part close to the substrate;

the third unit part and the fourth unit part at least partially overlap in a direction perpendicular to the substrate;

wherein the third unit portion is connected to the first signal line.

15. The display panel according to claim 14,

the semiconductor layer, the first metal layer, the second metal layer and the third metal layer are arranged on one side of the substrate and along the direction far away from the substrate; wherein the content of the first and second substances,

the first signal line is located on the third metal layer, and the first sub-signal line is located on the second metal layer;

the third unit portion is located in the first metal layer, and the fourth unit portion is located in the semiconductor layer.

16. The display panel according to claim 1,

the second signal line includes the second sub-signal line and the third sub-signal line alternately arranged;

the display panel further comprises a first metal layer, a second metal layer and a third metal layer which are arranged on one side of the substrate and along the direction far away from the substrate; wherein the content of the first and second substances,

the second sub-signal line is located on the first metal layer, and the third sub-signal line is located on the second metal layer.

17. The display panel according to claim 1,

the electrostatic buffering unit overlaps an edge of the first signal line extending in the first direction in a direction perpendicular to the substrate.

18. The display panel according to claim 17,

the first signal line has a first edge and a second edge extending in the first direction and arranged in a second direction;

the electrostatic buffer unit overlaps both the first edge and the second edge in a direction perpendicular to the substrate.

19. The display panel according to claim 1,

the first signal line comprises a main body part and a protruding part, the main body part extends along the first direction, and the protruding part protrudes from the main body part along the second direction to a direction far away from the main body part;

the electrostatic buffer unit overlaps the projection in a direction perpendicular to the substrate.

20. A display device characterized by comprising the display panel according to any one of claims 1 to 19.

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

Static electricity generated in the process of the display panel can be transmitted on the signal lines, and for two signal lines with mutually crossed extension directions, the static electricity is easy to discharge at the overlapped position of the two signal lines to break through an insulating layer between the two signal lines, and finally, water vapor enters to corrode the signal lines in an aging test, so that the performance reliability of products is influenced.

Disclosure of Invention

Embodiments of the present invention provide a display panel and a display device, so as to reduce a risk that a position where two signal lines overlap due to static electricity generated in a manufacturing process is damaged, and improve performance reliability of a product.

In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes a display area and a non-display area;

the non-display area comprises a first signal line and a plurality of second signal lines;

the display panel includes a substrate; the first signal line and the plurality of second signal lines are positioned on the same side of the substrate, and the first signal line and the second signal lines are positioned on different layers;

the non-display area further includes a first area in which: the first signal line extends along a first direction, the second signal line extends along a second direction, and the first direction and the second direction are mutually crossed; the orthographic projection of the first signal line on the plane of the substrate is at least partially overlapped with the orthographic projection of the plurality of second signal lines on the plane of the substrate; wherein the content of the first and second substances,

the first area is provided with an electrostatic buffer unit; the orthographic projection of the electrostatic buffer unit on the plane of the substrate is at least partially overlapped with the orthographic projection of the first signal line on the plane of the substrate.

In a second aspect, an embodiment of the present invention provides a display device including the display panel provided in any embodiment of the present invention.

The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: in the embodiment of the invention, the electrostatic buffer unit is overlapped with the first signal line, when electrostatic charges generated in the display panel process are transmitted on the first signal line, a capacitor can be formed between the electrostatic buffer unit and the first signal line to store the static electricity, and the electrostatic buffer unit is damaged after the static electricity is accumulated to a certain degree so as to release the static electricity. The invention can prevent electrostatic charges transmitted on the first signal wire from damaging the insulating layer at the overlapping position of the first signal wire and the second signal wire, thereby protecting the second signal wire and improving the reliability of product performance.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.

FIG. 1 is a partial schematic view of a display panel in the prior art;

fig. 2 is a schematic top view of a display panel according to an embodiment of the present invention;

fig. 3 is a schematic partial enlarged view of a first region of a display panel according to an embodiment of the invention;

FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 3;

FIG. 5 is a schematic diagram of a first region of another display panel according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a first area of another display panel according to an embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view taken along line B-B' of FIG. 2;

FIG. 8 is another schematic cross-sectional view taken along line A-A' of FIG. 3;

fig. 9 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the present invention;

fig. 10 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the present invention;

fig. 11 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the invention;

fig. 12 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the present invention;

fig. 13 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the invention;

fig. 14 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the present invention;

fig. 15 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the invention;

fig. 16 is a schematic view of a partial film structure of a first region of a display panel according to another embodiment of the present invention;

FIG. 17 is another schematic cross-sectional view taken along line A-A' of FIG. 3;

FIG. 18 is another schematic cross-sectional view taken at line A-A' of FIG. 3;

FIG. 19 is a schematic top view of a portion of a first region of a display panel according to an embodiment of the invention;

FIG. 20 is a schematic cross-sectional view taken along line D-D' of FIG. 19;

FIG. 21 is a schematic top view of a portion of a first region of a display panel according to another embodiment of the present invention;

FIG. 22 is a schematic cross-sectional view taken along line C-C' of FIG. 21;

fig. 23 is a schematic view of a display device according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Fig. 1 is a partial schematic view of a display panel in the prior art, as shown in fig. 1, a non-display area BA of the display panel includes a plurality of data leads 01, one end of each data lead 01 is connected to a binding terminal 02, and the other end is connected to a data line (not labeled) in a display area AA. The non-display area BA is further provided with a power supply lead 03, and the power supply lead 03 is led out from the binding terminal 02, extends to the display area AA, and is connected to a power supply signal line in the display area AA. In which at least a portion of the power supply wire 03 crosses the region where the plurality of data wires 01 are arranged, that is, at least a portion of the power supply wire 03 overlaps the plurality of data wires 01. In the display panel in the prior art, the display panel is subjected to aging test in a factory, and then the display panel is found to have the problem of abnormal display. The inventor finds that part of the data leads 01 can not normally transmit signals to cause abnormal display after detection.

The inventors have made a detailed analysis of the cause of this problem and then concluded that: when the electrostatic charges move in the power supply lead 03, the accumulated amount of the electrostatic charges may cause the insulating layer at the overlapping position (e.g., the region Q shown in fig. 1) of the power supply lead 03 and the data lead 01 to be broken, and the data lead 01 to be slightly damaged. During subsequent aging tests, water vapor enters the position where the insulating layer is punctured, so that the data lead 01 is corroded, and the product performance reliability is affected. Based on the above problems and related analysis, the present invention provides a display panel, in which an electrostatic buffer unit is added in the display panel, the electrostatic buffer unit is at least partially overlapped with a power lead, and the electrostatic buffer unit is used to store and release the static electricity generated in the process, so as to prevent the static electricity from damaging the data lead, thereby improving the reliability of the product performance.

Fig. 2 is a schematic partial top view of a display panel according to an embodiment of the invention.

As shown in fig. 2, the display panel includes a display area AA and a non-display area BA; the non-display area BA includes a first signal line 10 and a plurality of second signal lines 20. The first signal line 10 and the plurality of second signal lines 20 are located on the same side of a substrate (not shown in fig. 1), and the first signal line 10 and the second signal lines 20 are located on different layers.

At least a part of the second signal lines 20 include a first line segment 20-1 and a second line segment 20-2, wherein the first line segment 20-1 has one end connected to the binding terminal 40 and the other end connected to the second line segment 20-2; one end of the second line segment 20-2 is connected to the first line segment 20-1, and the other end is connected to a corresponding trace in the display area AA. The plurality of first line segments 20-1 of the plurality of second signal lines 20 extend in substantially the same direction, and the second line segments 20-2 extend in a direction different from the direction in which the first line segments 20-1 extend. In some embodiments, the plurality of second signal lines 20 are arranged in a fan shape. The non-display area BA further includes a first area Q1, in which Q1: the first signal line 10 extends in a first direction x, and the second signal line 20 extends in a second direction y, the first direction x and the second direction y crossing each other. The line width of the first signal line 10 is greater than the line width of the second signal line 20 in the first region Q1. Here, the line width is understood as the width of the signal line in the direction perpendicular to the extending direction of the signal line.

In the first region Q, an orthogonal projection of the first signal line 10 on the plane of the substrate at least partially overlaps with an orthogonal projection of the plurality of second signal lines 20 on the plane of the substrate. In other words, within the first region Q1, the first signal line 10 and the second signal line 20 at least partially overlap in a direction perpendicular to the plane of the substrate. Fig. 1 is a schematic top view of a display panel, and it can be understood that the top view direction is the same as the projection direction of the signal line to the substrate. Therefore, in top view, the first signal line 10 coincides with its orthographic projection on the plane of the substrate, and the second signal line 20 coincides with its orthographic projection on the plane of the substrate, and the orthographic projection of the signal lines is not shown in fig. 1. In fig. 2, the first direction x is shown substantially perpendicular to the second direction y. In some embodiments, the first direction x and the second direction y have an angle different from 90 °.

In the embodiment of the present invention, the first section Q1 is provided with the electrostatic buffer unit 30. It will be appreciated that in the top view of fig. 2, the electrostatic buffer unit 30 coincides with its orthographic projection on the plane of the substrate. The orthographic projection of the electrostatic buffer unit 30 on the plane of the substrate at least partially overlaps with the orthographic projection of the first signal line 10 on the plane of the substrate. In other words, within the first region Q1, the electrostatic buffer unit 30 at least partially overlaps the first signal line 10 in the direction perpendicular to the substrate.

In the embodiment of the present invention, the electrostatic buffering unit 30 is overlapped with the first signal line 10, when electrostatic charges generated in the display panel process are transmitted on the first signal line 10, a capacitor can be formed between the electrostatic buffering unit 30 and the first signal line 10 to store the electrostatic charges, and the electrostatic buffering unit 30 is damaged after the electrostatic charges are accumulated to a certain extent to discharge the electrostatic charges. According to the invention, electrostatic charges transmitted on the first signal line 10 can be prevented from breaking through the insulating layer at the overlapping position of the first signal line 10 and the second signal line 20 to damage the second signal line 20, so that the second signal line 20 can be protected, and the performance reliability of the product can be improved.

The display panel provided by the embodiment of the invention comprises a plurality of light-emitting devices and a plurality of pixel circuits, wherein the pixel circuits are used for driving the light-emitting devices to emit light, and the light-emitting devices are organic light-emitting devices or inorganic light-emitting devices. In one embodiment, the first signal line 10 is a power supply lead, and the first signal line 10 is electrically connected to a power supply signal line in the display area AA, which supplies a power supply voltage signal to the pixel circuit. The second signal line 20 is a data lead line in the non-display area BA, and the second signal line 20 is electrically connected to the data line in the display area AA. As also illustrated in fig. 2, the binding terminals 40 of the non-display area BA are electrically connected to the first and second signal lines 10 and 20, respectively, with the binding terminals 40.

Fig. 3 is a partially enlarged schematic view of a first region of a display panel according to an embodiment of the invention, and fig. 4 is a schematic cross-sectional view of a position of a cut line a-a' in fig. 3. As will be understood in conjunction with fig. 3 and 4, the first signal line 10 and the second signal line 20 are both located above the substrate 1. The third direction z is perpendicular to the second direction y, i.e. the third direction z is the width direction of the second signal line 20. The second signal line 20 is in the third directionWidth in z is D₁The width of the electrostatic buffer unit 30 in the third direction z is D₂Wherein D is₂Is less than D₁. In the embodiment of the invention, in the direction e perpendicular to the plane of the substrate 1, the electrostatic buffer unit 30 at least partially overlaps the first signal line 10, and the second signal line 20 at least partially overlaps the first signal line 10, so that the electrostatic buffer unit 30 and the first signal line 10 form a capacitor C1, and the second signal line 20 and the first signal line 10 form a capacitor C2.

In fig. 4, taking the example that the electrostatic buffer unit 30 and the second signal line 20 are located on the same layer, the capacitance formula C is ═ S/(4 pi kd), epsilon is the dielectric constant of the capacitor between two plates, S is the facing area of the capacitor between two plates, k is the electrostatic force constant, and d is the vertical distance between two plates of the capacitor. According to the capacitance formula, when D is₂Is less than D₁The capacitance C1 is smaller than the capacitance C2. From the fact that C is Q/U, Q is the charged capacity of the capacitor, and U is the voltage between two plates of the capacitor, it can be seen that the larger the capacitor is, the smaller the voltage applied to the two ends of the capacitor is when the same charge is stored. That is, the voltage that can be borne between the two plates of the capacitor C2 is greater than the voltage that can be borne by the capacitor C1. When static electricity is transmitted through the first signal line 10, the capacitor C1 formed by the static electricity buffering unit 30 and the first signal line 10 is damaged preferentially when the static electricity is accumulated to a certain amount, so that the second signal line 20 can be protected.

Optionally, the width D of the electrostatic buffer unit 30 in the third direction z₂Less than or equal to 2.5 mu m. Optionally, the second signal line 20 has a width D in the third direction z₁Between 3 μm and 5 μm. In the case of satisfying the process condition, the width of the electrostatic buffer unit 30 can be made relatively small to ensure that the electrostatic buffer unit 30 can be damaged preferentially by the charges generated in the process when the charges are transmitted on the first signal line 10, so as to protect the second signal line 20.

When the extending direction of the first signal line 10 and the extending direction of the second signal line 20 are perpendicular to each other, that is, when the first direction x and the second direction y are perpendicular to each other, the third direction z is the same direction as the first direction x. When the first direction x and the second direction y have an included angle of other than 90 °, the third direction z is perpendicular to the second direction y, and the third direction z has an included angle of other than 0 ° with the first direction x.

In the embodiment of the present invention, the electrostatic buffering unit 30 is located at least one side of at least one second signal line 20 along the arrangement direction of the second signal lines 20. That is, in some embodiments, for one second signal line 20, the electrostatic buffering unit 30 is provided only on one side of the one second signal line 20; in some embodiments, for one second signal line 20, the electrostatic buffer units 30 are disposed on both sides of the one second signal line 20; in some embodiments, a plurality of electrostatic buffer units 30 are provided, and the electrostatic buffer units 30 are respectively located between two adjacent second signal lines 20.

The term "adjacent" in the embodiment of the present invention means adjacent in the arrangement direction of the plurality of second signal lines 20. In the arrangement direction of the second signal lines 20, one electrostatic buffer unit 30 is located at one side of one second signal line, which can also be said: one electrostatic buffer unit 30 is adjacent to one second signal line 20 in the arrangement direction of the second signal lines 20; in other words, the electrostatic buffer unit 30 is spaced apart from the orthographic projection of the substrate 1 by a certain distance from the orthographic projection of the second signal line 20 on the substrate 1. As shown in fig. 4, when the electrostatic buffer unit 30 and the second signal line 20 are located on the same layer, the electrostatic buffer unit 30 and the second signal line 20 are adjacent to each other with a certain distance therebetween. The distance can be determined according to the process conditions for manufacturing the second signal line, and the second signal line 20 and the electrostatic buffer unit 30 are ensured to be insulated from each other under the condition that the manufacturing yield of the second signal line is met. As shown in fig. 3, taking the electrostatic buffering unit 30-3 as an example, the electrostatic buffering unit 30-3 is adjacent to the two second signal lines 20. That is, one second signal line 20 is provided on each of the right and left sides of the electrostatic buffering unit 30-3. In the embodiment of the invention, the electrostatic protection of the second signal line is realized by setting the structure of the electrostatic buffer unit and the relative positions of the electrostatic buffer unit and the film layer of the second signal line adjacent to the electrostatic buffer unit.

In some embodiments, the electrostatic buffering unit 30 can simultaneously protect two second signal lines 20 respectively located at both sides thereof in the arrangement direction of the second signal lines 20. As shown in the embodiment of fig. 4, the electrostatic buffer unit 30 is located at the same layer as the second signal line 20, and the relative positional relationship between the electrostatic buffer unit 30 and the two adjacent second signal lines 20 is the same, in this embodiment, the electrostatic buffer unit 30 can simultaneously protect the two second signal lines 20 located at both sides thereof.

In some embodiments, in the arrangement direction of the second signal lines 20, the electrostatic buffer unit 30 is located between two adjacent second signal lines 20, and the electrostatic buffer unit 30 can protect one of the two second signal lines 20. In the following related embodiments, the above two cases will also be explained.

Fig. 5 is a schematic diagram of a first area of another display panel according to an embodiment of the present invention, and as shown in fig. 5, two electrostatic buffer units, namely an electrostatic buffer unit 30-1 and an electrostatic buffer unit 30-2, are disposed in the first area Q1, where the electrostatic buffer unit 30-1 is located on one side of a first second signal line 20 in an arrangement direction of the plurality of second signal lines 20, and the electrostatic buffer unit 30-2 is located on one side of a last second signal line 20 in the arrangement direction of the plurality of second signal lines 20. Static electricity generated during the manufacturing process of the display panel may be transmitted from left to right on the first signal line 10 or from right to left on the second signal line 10. Regarding the plurality of second signal lines 20 arranged as a signal line group, this embodiment is equivalent to disposing static electricity buffering units on two sides of the signal line group, so that when static electricity is transmitted on the first signal line 10, and when static electricity is not transmitted to the position of the portion of the first signal line 10 overlapped with the second signal line 20, the static electricity is transmitted to the position where the static electricity buffering unit 30 and the first signal line 10 are overlapped, the static electricity can be stored and released by the action of the static electricity buffering unit 30, and static electricity charges are prevented from breaking through the insulating layer at the overlapped position of the first signal line 10 and the second signal line 20, so that the second signal line 20 can be protected.

In some embodiments, fig. 6 is a schematic view of a first area in another display panel according to an embodiment of the present invention, and as shown in fig. 6, a plurality of electrostatic buffer units 30 are disposed in the first area Q1, and an orthogonal projection of each electrostatic buffer unit 30 on a plane of the substrate 1 is located between orthogonal projections of two adjacent second signal lines 20 on the plane of the substrate 1. The structure of the electrostatic buffer unit 30 and the relative positions of the electrostatic buffer unit 30 and the two adjacent second signal lines are combined, and the electrostatic buffer unit 30 can protect at least the second signal lines 20 on the two sides.

In some embodiments, as shown in fig. 2 and 3, the orthogonal projection of the electrostatic buffer unit 30 on the plane of the substrate 1 and the orthogonal projection of the second signal line 20 on the plane of the substrate 1 are alternately distributed. So set up and to make at least one side of each second signal line 20 all be provided with static buffer cell 30, a plurality of static buffer cells 30 can cushion the static of releasing on first signal line 10 a plurality of positions department, guarantee that each second signal line 20 is not wounded by the static.

In some embodiments, the electrostatic buffer unit 30 is located at a side of the first signal line 10 close to the substrate 1. The second signal line 20 is located on a side of the first signal line 10 close to the substrate 1, i.e., the electrostatic buffer unit 30 is located on the same side of the first signal line 10 as the second signal line 20. The electrostatic buffer unit 30 can be manufactured by reusing the existing conductive layer (such as a metal layer or a semiconductor layer) in the display panel without adding a new process.

In one embodiment, FIG. 7 is a schematic cross-sectional view taken along line B-B' of FIG. 2, and FIG. 7 shows a film structure of the display panel. As shown in fig. 7, the display panel includes a semiconductor layer 2, a first metal layer 3, a second metal layer 4, and a third metal layer 5 on a side of a substrate 1 and disposed in a direction away from the substrate 1. Wherein, the active layer of the transistor is positioned on the semiconductor layer 2; one polar plate of a storage capacitor in the pixel circuit is positioned on the first metal layer 3, and the other polar plate is positioned on the second metal layer 4; the data line is located in the third metal layer 5. The display panel further comprises a light emitting device 50, the light emitting device 50 comprising a first electrode 51, a light emitting layer 52 and a second electrode 53 arranged in a stack, the first electrode 51 being located at a side of the light emitting layer 52 close to the substrate 1. Also illustrated in fig. 7 is a first insulating layer 61 located between the semiconductor layer 2 and the first metal layer 3, a second insulating layer 62 located between the first metal layer 3 and the second metal layer 4, a third insulating layer 63 located between the second metal layer 4 and the third metal layer 5, and a fourth insulating layer 64 located between the third metal layer 5 and the light emitting device 50. Optionally, the first insulating layer 61, the second insulating layer 62, and the third insulating layer 63 are all inorganic insulating layers; the fourth insulating layer 64 includes an organic insulating layer.

Fig. 7 schematically shows a storage capacitor C in the pixel circuit, one plate of the storage capacitor C is located in the first metal layer 3, and the other plate is located in the second metal layer 4.

In one embodiment, the semiconductor layer 2 is made of silicon. In another embodiment, the material of which the semiconductor layer 2 is made comprises a metal oxide.

Optionally, the first metal layer 3 and the second metal layer 4 are made of the same material and include molybdenum. The third metal layer 5 is made of metal titanium and metal aluminum. Optionally, the third metal layer 5 is a titanium/aluminum/titanium three-layer structure.

In another embodiment, the display panel further comprises a fourth metal layer (not shown), which is located between the third metal layer 5 and the first electrode 51 electrode. Optionally, the fourth metal layer and the third metal layer 5 are made of the same material.

In one embodiment, the first signal lines 10 are located on the third metal layer 5, and the plurality of second signal lines 20 are located on the same film layer different from the third metal layer. Optionally, the plurality of second signal lines 20 are all located on the first metal layer 3 or the second metal layer 4.

In another embodiment, FIG. 8 is another cross-sectional view taken at line A-A' of FIG. 3. As shown in fig. 8, the second signal line 20 includes second sub-signal lines 22 and third sub-signal lines 23 alternately arranged; the second sub-signal line 22 is located on the first metal layer 3, the third sub-signal line 23 is located on the second metal layer 4, and the first signal line 10 is located on the third metal layer 5. In this embodiment, the second signal lines 20 for transmitting the same type of signals are disposed in two metal layers for wiring, so that the total width occupied by the second signal lines 20 in the third direction z in the first region can be reduced, and the space of the non-display region can be saved.

In the embodiment of the present invention, the electrostatic buffer unit 30 is located on at least one side of at least one second signal line 20 in the arrangement direction of the plurality of second signal lines 20. In other words, the orthogonal projection of the electrostatic buffer unit 30 on the plane of the substrate 1 is adjacent to the orthogonal projection of the at least one second signal line 20 on the plane of the substrate 1. The following embodiment takes the electrostatic buffering unit 30 located at one side of one second signal line 20 (in the following related embodiments, the name of the first sub-signal line is used for explanation) as an example, and the structure of the electrostatic buffering unit 30 and the film layer position relationship between the electrostatic buffering unit 30 and the second signal line 20 are explained by combining the film layer structure of the display panel illustrated in the embodiment of fig. 7.

In addition, in the embodiments of fig. 8 to 18, one structure is filled with one pattern, in which the first signal line 10 is filled with one pattern, the first sub-signal line 21 is filled with one pattern, and each of the first cell portion 31, the second cell portion 32, the third cell portion 33, and the fourth cell portion 34 is filled with one pattern. The filling of each structure in the embodiments of fig. 8 to 18 does not correspond to the filling of the metal layer in which it is located. For example, in the embodiment of fig. 8, the second signal line 20 includes a second sub-signal line 22, the second sub-signal line 22 is located in the first metal layer 3, and reference numeral 22/20/3 of the second sub-signal line 22 is the same as reference numeral 3, where the reference numeral 3 indicates that the second sub-signal line 22 is located in the first metal layer 3.

In some embodiments, fig. 9 is a schematic view of a partial film structure of a first region of another display panel according to an embodiment of the present invention, and fig. 9 illustrates a third direction z, that is, a cross-sectional line of the film structure of fig. 9 extends in parallel with the third direction z. As shown in fig. 9, the electrostatic buffer unit 30 includes a first cell part 31, and the first cell part 31 is spaced apart from the first signal line 10 by a distance d1 and the first sub-signal line 21 is spaced apart from the first signal line 10 by a distance d2 in a direction e perpendicular to the substrate 1, where d1< d 2. The display panel includes conductive layers (such as metal layers or semiconductor layers) and insulating layers between the conductive layers. The distance from the first unit portion 31 to the first signal line 10 is smaller than the distance from the first sub-signal line 21 to the first signal line 10, and the thickness of the insulating layer between the first unit portion 31 and the first signal line 10 is smaller than the thickness of the insulating layer between the first sub-signal line 21 and the first signal line 10. When there is electrostatic transmission on the first signal line 10, the insulating layer having a small thickness is more likely to be electrostatically broken. The capacitance formed between the first unit section 31 and the first signal line 10 first stores the static electricity accumulated on the first signal line 10, and when the static electricity is accumulated to a certain amount, the first unit section 31 is first damaged, so that the first sub-signal line 21 can be protected. That is, by providing the electrostatic buffering unit 30, the second signal line 20 is prevented from being electrostatically damaged.

Optionally, in the embodiment of fig. 9, the first signal line 10 is located in the third metal layer 5, the first sub-signal line 21 is located in the first metal layer 3, and the first unit portion 31 is located in the second metal layer 4. The insulating layer between the first unit section 31 and the first signal line 10 is a third insulating layer 63, and the insulating layer between the first sub-signal line 21 and the first signal line 10 includes a second insulating layer 62 and the third insulating layer 63. In this embodiment, the first unit portion 31 is formed by multiplexing the existing film layers of the display panel, and the process is not increased. Further, d1< d2 indicates that the thickness of the insulating layer between the first cell unit 31 and the first signal line 10 is smaller than the thickness of the insulating layer between the first sub-signal line 21 and the first signal line 10, and that the first cell unit 31 is more likely to be damaged by static electricity than the first sub-signal line 21 when static electricity is transmitted through the first signal line 10. When the orthographic projection of the first unit portion 31 on the substrate 1 is arranged adjacent to the orthographic projection of the first sub-signal line 21 on the substrate 1, the first unit portion 31 can effectively protect the first sub-signal line 21 from static electricity.

In another embodiment, fig. 10 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and an extending direction of a cross-sectional line of the film structure of fig. 10 is parallel to a third direction z. As shown in fig. 10, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 and the first unit section 31 are located in the first metal layer 3. A second insulating layer 62 and a third insulating layer 63 are included between the first metal layer 3 and the third metal layer 5. In the direction e perpendicular to the substrate 1, the distance from the first signal line 10 to the first cell unit 31 is d1, and the distance from the first sub-signal line 21 to the first signal line 10 is d2, where d1 is d 2. In this embodiment, by setting the width of the first unit section 31 in the third direction z to be smaller than the width of the first sub-signal line 21 in the third direction z, the capacitance formed between the first unit section 31 and the first signal line 10 can be made smaller than the capacitance formed between the first sub-signal line 21 and the first signal line 10, and the capacitance formed between the first unit section 31 and the first signal line 10 first stores static electricity accumulated on the first signal line 10, and after the static electricity is accumulated to a certain amount, the first unit section 31 is first damaged, so that the first sub-signal line 21 can be protected.

In another embodiment, fig. 11 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and a cross-sectional line of the film structure of fig. 11 extends in a direction parallel to a third direction z. As shown in fig. 11, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 and the first unit section 31 are both located in the second metal layer 4. In some embodiments, the third metal layer 5 is made of a titanium/aluminum/titanium triple layer metal, the first metal layer 3 and the second metal layer 4 are made of molybdenum, and the sheet resistance of the signal line made of the third metal layer 5 is smaller than that of the signal line made of the second metal layer 4. In the embodiment where the first signal line 10 is a power supply line, the voltage drop on the first signal line 10 can be reduced, thereby reducing the power consumption of the display panel. In addition, the second metal layer 4 is the metal layer closest to the first signal line 10 on the substrate 1, and the first unit part 31 is arranged on the second metal layer 4, so that the first unit part 31 can be manufactured by multiplexing the original process of the display panel; the second unit section 31 can protect the second signal line located in the second metal layer 4 from static electricity as well as the second signal line located in the first metal layer 3 from static electricity.

By setting the width of the first unit section 31 in the third direction z to be smaller than the width of the first sub-signal line 21 in the third direction z in this embodiment, the capacitance formed between the first unit section 31 and the first signal line 10 can be made smaller than the capacitance formed between the first sub-signal line 21 and the first signal line 10. The capacitance formed between the first unit section 31 and the first signal line 10 first stores static electricity accumulated on the first signal line 10, and after the static electricity is accumulated to a certain amount, the first unit section 31 is first damaged, so that the first sub-signal line 21 can be protected.

In another embodiment, fig. 12 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and a cross-sectional line of the film structure of fig. 12 extends in a direction parallel to a third direction z. As shown in fig. 12, the electrostatic buffer unit 30 further includes a second unit portion 32, the second unit portion 32 being located on a side of the first unit portion 31 close to the substrate 1; the first unit section 31 and the second unit section 32 at least partially overlap in a direction e perpendicular to the substrate 1. In this embodiment, the electrostatic buffer unit 30 includes a double-layer unit portion, and a capacitance can be formed between the first unit portion 31 and the first signal line 10. When the electrostatic charges transferred on the first signal line 10 break through the insulating layer between the first unit portion 31 and the first signal line 10, the first unit portion 31 and the first signal line 10 are conducted, and the electrostatic charges are transferred to the first unit portion 31 through the first signal line 10, and at this time, a capacitor can be formed between the second unit portion 32 and the first unit portion 31. In some embodiments, if the distance between the second unit portion 32 and the first unit portion 31 is not greater than the distance between the first sub-signal line 21 and the first signal line 10, the capacitance formed between the second unit portion 32 and the first unit portion 31 can continuously store and release static electricity on the first unit portion 31, continuously prevent the static electricity from damaging the first sub-signal line 21, achieve a double protection effect on the first sub-signal line, and reduce the risk of the first sub-signal line 21 being damaged by the static electricity.

Alternatively, as shown in fig. 12, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 is located in the second metal layer 4; the first cell portion 31 is located on the second metal layer 4, and the second cell portion 32 is located on the first metal layer 3. In this embodiment, the first unit portion 31 and the second unit portion 32 are both manufactured by reusing the existing film layer in the display panel, and no new process is added. When the first unit portion 31 and the first sub-signal line 21 are located on the same layer, the distance from the first unit portion 31 to the first signal line 10 is substantially equal to the distance from the first sub-signal line 21 to the first signal line 10, and the thickness of the insulating layer between the first unit portion 31 and the first signal line 10 is substantially equal to the thickness of the insulating layer between the first sub-signal line 21 and the first signal line 10. By setting the width of the first unit portion 31 in the third direction z to be smaller than the width of the first sub-signal line 21 in the third direction z, the first unit portion 31 is firstly damaged by static electricity transmitted on the first signal line 10 after the static electricity is accumulated to a certain degree so as to protect the first sub-signal line 21, and after the first unit portion 31 is damaged by the static electricity, a capacitor can be formed between the first unit portion 31 and the second unit portion 32 to continuously store and release the static electricity, so that a double protection effect on the first sub-signal line 21 can be realized.

Further, in the embodiment of fig. 12, the electrostatic buffer unit 30 further includes a fifth unit portion, and the fifth unit portion is located on a side of the second unit portion 32 close to the substrate 1. The fifth unit section at least partially overlaps the second unit section 32 in the direction e perpendicular to the substrate 1. Optionally, the fifth unit cell is located in the semiconductor layer 2. That is, the electrostatic buffer unit 30 has a three-layer unit portion structure, and after the unit portion on the side away from the substrate 1 is electrostatically damaged, a capacitance can be continuously formed between the electrostatically damaged unit portion and the unit portion below the electrostatically damaged unit portion, and by setting the width of each unit portion in the third direction z and the distance between the adjacent unit portions in the direction e perpendicular to the substrate 1, the capacitance formed by the electrostatically damaged unit portion and the unit portion below the electrostatically damaged unit portion can be continuously buffered and released for static electricity, so that a multiple protection effect on the first sub-signal line can be realized, and the risk of electrostatic damage to the first sub-signal line can be reduced.

In another embodiment, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 is located in the second metal layer 4; the first unit portion 31 is located on the second metal layer 4, and the second unit portion 32 is located on the semiconductor layer 2, which is not illustrated in the drawings.

In another embodiment, fig. 13 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and a cross-sectional line of the film structure of fig. 13 extends in a direction parallel to a third direction z. As shown in fig. 13, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 is located in the first metal layer 3; the first cell portion 31 is located on the second metal layer 4, and the second cell portion 32 is located on the first metal layer 3. In this embodiment, the second unit portion 32 is located on the same layer as the first sub-signal line 21, and the distance from the first unit portion 31 to the first signal line 10 is smaller than the distance from the first sub-signal line 21 to the first signal line 10. When there is static accumulation on the first signal line 10, the capacitance formed between the first signal line 10 and the first unit portion 31 can buffer and release static electricity, and when the static accumulation amount is large, the static electricity first damages the first unit portion 31 to perform static protection on the first sub-signal line 21; when static electricity is accumulated on the first signal line 10 again after the first unit portion 31 is damaged by the static electricity, the static electricity is transmitted to the first unit portion 31 through the first signal line 10, and at this time, the distance between the first unit portion 31 and the second unit portion 32 is smaller than the distance between the first sub-signal line 21 and the first signal line 10, so that a capacitor can be formed between the first unit portion 31 and the second unit portion 32 to continuously store and discharge the static electricity, and the first sub-signal line 21 can be protected again by the static electricity. This embodiment can realize the double protection effect on the first sub-signal line 21, and reduce the risk of the first sub-signal line 21 being damaged by electrostatic shock.

In another embodiment, fig. 14 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and a cross-sectional line of the film structure of fig. 14 extends in a direction parallel to a third direction z. As shown in fig. 14, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 and the first unit section 31 are both located in the first metal layer 3; the second unit portion 32 is located on the semiconductor layer 2. In this embodiment, the first unit portion 31 and the first sub-signal line 21 are located on the same layer, and the first unit portion 31 is first damaged by static electricity accumulated in the first signal line 10, so that the first unit portion 31 can protect the first sub-signal line 21 from static electricity. A first insulating layer 61 is interposed between the first cell portion 31 and the second cell portion 32, and a second insulating layer 62 and a third insulating layer 63 are interposed between the first sub-signal line 21 and the first signal line 10, so that the thickness of the insulating layer between the first cell portion 31 and the second cell portion 32 is smaller than the thickness of the insulating layer between the first sub-signal line 21 and the first signal line 10. After the first unit portion 31 is damaged by the static electricity, the static electricity continuously accumulated on the first signal line 10 is transferred to the first unit portion 31, so that a capacitor can be formed between the first unit portion 31 and the second unit portion 32 to continuously store and release the static electricity, the static electricity can be prevented from damaging the first sub-signal line again, the double protection effect on the first sub-signal line is realized, and the risk that the first sub-signal line 21 is damaged by the static electricity is reduced.

In another embodiment, fig. 15 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and a cross-sectional line of the film structure of fig. 15 extends in a direction parallel to a third direction z. As shown in fig. 15, the first unit portion 31 is electrically connected to the first signal line 10. Alternatively, the first unit portion 31 and the first signal line 10 are electrically connected through a via hole in the insulating layer. In this embodiment, static electricity on the first signal line 10 is transmitted to the first unit portion 31, and the capacitance formed between the first unit portion 31 and the second unit portion 32 can store and discharge the static electricity, so that the risk of damaging the first sub-signal line 21 by the static electricity can be reduced. In addition, the first unit portion 31 is electrically connected to the first signal line 10, so that the impedance of the first signal line 10 can be reduced, the electrostatic dissipation on the first signal line 10 is facilitated, and the risk of damaging the first sub-signal line 21 by electrostatic shock can be reduced.

In another embodiment, fig. 16 is a schematic view of a partial film structure of a first region in another display panel according to an embodiment of the present invention, and a cross-sectional line of the film structure of fig. 16 extends in a direction parallel to a third direction z. As shown in fig. 16, the electrostatic buffer unit 30 includes a third unit portion 33 and a fourth unit portion 34, the third unit portion 33 being located on a side of the first sub-signal line 21 close to the substrate 1, the fourth unit portion 34 being located on a side of the third unit portion 33 close to the substrate 1; in the direction e perpendicular to the substrate 1, the third unit section 33 and the fourth unit section 34 at least partially overlap; the third unit portion 33 is electrically connected to the first signal line 10. Optionally, the third unit portion 33 and the first signal line 10 are electrically connected through a via hole on the insulating layer. In this embodiment, static electricity on the first signal line 10 is transmitted to the third unit portion 33, and by setting the thickness of the insulating layer between the third unit portion 33 and the fourth unit portion 34 to be not more than the thickness of the insulating layer between the first sub-signal line 21 and the first signal line 10, the static electricity can be stored and discharged by the capacitance formed between the third unit portion 33 and the fourth unit portion 34, that is, the static electricity can be discharged by preferentially striking the fourth unit portion 34, and the risk of the static electricity striking the first sub-signal line 21 can be reduced. In addition, the third unit portion 33 is electrically connected to the first signal line 10, so that the impedance of the first signal line 10 can be reduced, the electrostatic dissipation on the first signal line 10 is facilitated, and the risk of damaging the first sub-signal line 21 by electrostatic shock can be reduced.

As shown in fig. 16, the first signal line 10 is located in the third metal layer 5, and the first sub-signal line 21 is located in the second metal layer 4; the third unit portion 33 is located on the first metal layer 3, and the fourth unit portion 34 is located on the semiconductor layer 2. In this embodiment, the third unit portion 33 is located on the side of the first sub-signal line 21 close to the substrate 1, and the distance from the third unit portion 33 to the first signal line 10 is greater than the distance from the first sub-signal line 21 to the first signal line 10 in the direction e perpendicular to the substrate 1. In this embodiment, the third unit section 33 and the fourth unit section 34 are not on the same layer as the first sub-signal line 21, and when a plurality of second signal lines are provided in the second metal layer 4, the electrostatic buffer unit (including the third unit section 33 and the fourth unit section 34) is provided so as not to occupy a space of the second metal layer 4.

The above-mentioned embodiments of fig. 9 to 16 take one first sub-signal line 21 of the plurality of second signal lines 20 as an example to describe the structure of the electrostatic buffer unit 30. In the embodiment of the present invention, the structure of the electrostatic buffer unit 30 may be configured according to the position of the film layer where the second signal line is located, with reference to the description of the above embodiment. In some embodiments, a plurality of electrostatic buffer units 30 are disposed in the first region Q1, and the structure of each electrostatic buffer unit 30 and the position of the film layer where each unit is located are the same. In some embodiments, a plurality of electrostatic buffer units 30 are disposed in the first region Q1, and the structure of each electrostatic buffer unit 30 and the position of the film layer where each unit is disposed are not identical.

In one embodiment, FIG. 17 is another cross-sectional view taken at line A-A' of FIG. 3. As shown in fig. 17, the second signal line 20 includes second sub-signal lines 22 and third sub-signal lines 23 alternately arranged; the second sub-signal line 22 is located on the first metal layer 3, the third sub-signal line 23 is located on the second metal layer 4, and the first signal line 10 is located on the third metal layer 5. The electrostatic buffer unit 30 includes a first electrostatic buffer unit 30-1 and a second electrostatic buffer unit 30-2, wherein the first electrostatic buffer unit 30-1 includes a first unit portion 31 and a second unit portion 32, and the second electrostatic buffer unit 30-2 includes the first unit portion 31. In this embodiment, the first and second electrostatic buffer units 30-1 and 30-2 have different structures.

In the arrangement direction of the plurality of second signal lines, the first electrostatic buffer unit 30-1 is located between the second sub-signal line 22 and the third sub-signal line 23, that is, the first electrostatic buffer unit 30-1 is adjacent to two second signal lines. The relative position relationship between the first electrostatic buffer unit 30-1 and the second sub-signal line 22 is the same as the relative position relationship between the electrostatic buffer unit 30 and the first sub-signal line 21 illustrated in the embodiment of fig. 13; the first static electricity buffering unit 30-1 can buffer and discharge static electricity and can prevent the second sub-signal line 22 from being damaged by static electricity. In addition, the relative positional relationship between the first electrostatic buffer unit 30-1 and the third sub-signal line 23 is the same as the relative positional relationship between the electrostatic buffer unit 30 and the first sub-signal line 21 illustrated in the above-described embodiment of fig. 12; the first electrostatic buffering unit 30-1 can buffer and discharge the static electricity and can prevent the third sub-signal line 23 from being damaged by the static electricity. In this embodiment, the first electrostatic buffer unit 30-1 can perform electrostatic protection on two adjacent second signal lines.

In the arrangement direction of the plurality of second signal lines, the second electrostatic buffer unit 30-2 is located between the second sub-signal line 22 and the third sub-signal line 23, that is, the second electrostatic buffer unit 30-2 is adjacent to two second signal lines. The relative positional relationship between the second electrostatic buffer unit 30-2 and the second sub-signal line 22 is the same as the relative positional relationship between the first unit portion 31 and the first sub-signal line 21 illustrated in the embodiment of fig. 9; the second static electricity buffering unit 30-2 can buffer and discharge static electricity and can prevent the second sub-signal line 22 from being damaged by static electricity. In addition, the relative positional relationship between the second electrostatic buffer unit 30-2 and the third sub-signal line 23 is the same as the relative positional relationship between the first unit section 31 and the first sub-signal line 21 illustrated in the above-described embodiment of fig. 11; the second electrostatic buffering unit 30-2 can buffer and discharge the static electricity and can prevent the third sub-signal line 23 from being damaged by the static electricity. In this embodiment, the second electrostatic buffer unit 30-2 can perform electrostatic protection on two second signal lines adjacent thereto.

In another embodiment, FIG. 18 is another cross-sectional view taken at line A-A' of FIG. 3. As shown in fig. 18, the electrostatic buffer units 30 are provided between the second sub-signal line 22 and the third sub-signal line 23, and the structures of the electrostatic buffer units 30 are the same. In the arrangement direction of the plurality of second signal lines, the electrostatic buffer unit 30 is located between the second sub-signal line 22 and the third sub-signal line 23, that is, the electrostatic buffer unit 30 is adjacent to two second signal lines. The relative position relationship between the electrostatic buffer unit 30 and the second sub-signal line 22 adjacent to the electrostatic buffer unit 30 is similar to the relative position relationship between the electrostatic buffer unit 30 and the first sub-signal line 21 illustrated in the embodiment of fig. 15, the electrostatic buffer unit 30 includes two unit portions, one unit portion farther from the substrate 1 is located on the same layer as the second sub-signal line 22, and the thickness of the insulating layer between the two unit portions in the electrostatic buffer unit 30 is set to be smaller than the thickness of the insulating layer between the second sub-signal line 22 and the first signal line 10, so that the electrostatic buffer unit 30 can perform electrostatic protection on the second sub-signal line 22. In addition, the relative positional relationship between the electrostatic buffer unit 30 and the third sub-signal line 23 is the same as the relative positional relationship between the electrostatic buffer unit 30 and the first sub-signal line 21 illustrated in the embodiment of fig. 16 described above; the static electricity buffering unit 30 can buffer and discharge static electricity and can prevent the third sub-signal line 23 from being damaged by static electricity. In this embodiment, the electrostatic buffer unit 30 can perform electrostatic protection on the two adjacent second signal lines.

In another embodiment, as shown in fig. 8, the second sub-signal lines 22 and the third sub-signal lines 23 are alternately arranged, and the electrostatic buffering unit 30 includes a first electrostatic buffering unit 30-1 and a second electrostatic buffering unit 30-2. In the arrangement direction of the plurality of second signal lines, the first electrostatic buffer unit 30-1 is located between the second sub-signal line 22 and the third sub-signal line 23, and the second electrostatic buffer unit 30-2 is also located between the second sub-signal line 22 and the third sub-signal line 23. The second electrostatic buffer unit 30-2 and the second sub-signal line 22 are located on the first metal layer 3, the first electrostatic buffer unit 30-1 and the third sub-signal line 23 are located on the second metal layer 4, and the first signal line 10 is located on the third metal layer 5. A third insulating layer 63 is provided between the second metal layer 4 and the third metal layer 5, and a third insulating layer 63 and a second insulating layer 62 are provided between the first metal layer 3 and the third metal layer 5. Wherein the content of the first and second substances,

the thickness of the insulating layer between the first electrostatic buffer unit 30-1 and the first signal line 10 is substantially equal to the thickness of the insulating layer between the third sub-signal line 23 and the first signal line 10, the thickness of the insulating layer between the first electrostatic buffer unit 30-1 and the first signal line 10 is smaller than the thickness of the insulating layer between the second sub-signal line 22 and the first signal line 10, and the first electrostatic buffer unit 30-1 can simultaneously perform electrostatic protection on the second sub-signal line 22 and the third sub-signal line 23 adjacent to the first electrostatic buffer unit 30-1 by designing the width of the first electrostatic buffer unit 30-1 in the third direction z.

The thickness of the insulating layer between the second electrostatic buffer unit 30-2 and the first signal line 10 is greater than the thickness of the insulating layer between the third sub-signal line 23 and the first signal line 10, the thickness of the insulating layer between the second electrostatic buffer unit 30-2 and the first signal line 10 is substantially equal to the thickness of the insulating layer between the second sub-signal line 22 and the first signal line 10, and the second electrostatic buffer unit 30-2 can perform electrostatic protection on the second sub-signal line 22 adjacent to the second electrostatic buffer unit.

In some embodiments, the electrostatic buffering unit is located on a side of the first signal line 10 away from the substrate 1. And the distance from the electrostatic buffer unit to the first signal line 10 in the direction perpendicular to the plane of the substrate 1 is not greater than the distance from the second signal line 20 to the first signal line. In this embodiment, when the capacitance formed between the electrostatic buffer and the first signal line 10 is set to be smaller than the capacitance formed between the second signal line 20 and the first signal line 10 and the distance between the electrostatic buffer and the first signal line 10 is set to be small, the insulating layer between the electrostatic buffer and the first signal line 10 is more likely to be electrostatically broken down, and the second signal line 20 can be protected.

In some embodiments, fig. 19 is a partial top view of a first region of another display panel provided in an embodiment of the invention, and fig. 20 is a schematic cross-sectional view taken along line D-D' of fig. 19. The first signal line 10 is illustrated in fig. 19 to have a first edge Y1 and a second edge Y2 extending in the first direction x and aligned in the second direction Y. When the first signal line 10 is formed by photolithography, a slope is formed at the etched edge of the first signal line 10, as shown in the regions Q2 and Q3 in fig. 20. The inventor analyzes the electrostatic damage phenomenon at the overlapping position of the first signal line 10 and the second signal line 20 and considers that: the metal thickness is thin at the slope position of the etched edge of the first signal line 10, and the electric field is easily concentrated at the slope angle position of the slope, so that the second signal line 20 is easily damaged by electric discharge at the overlapping position of the edge slope of the first signal line 10 and the second signal line 20. Based on this, in the embodiment of the present invention, the electrostatic buffering unit is disposed to overlap with the edge of the first signal line 10 extending in the first direction x, so as to buffer and discharge the static electricity at the edge position of the first signal line 10 through the electrostatic buffering unit.

As can be seen from the top view of fig. 19: the electrostatic buffer unit 30 overlaps an edge of the first signal line 10 extending in the first direction x in a direction perpendicular to the substrate 1. The third electrostatic buffer unit 30-3 overlaps the first edge Y1, and the fourth electrostatic buffer unit 30-4 overlaps the second edge Y2. In the embodiment of the present invention, the electrostatic buffering unit 30 is arranged to at least overlap with the edge of the first signal line 10 extending in the first direction x, so that static electricity at the edge position of the first signal line 10 extending in the first direction x can be stored and released through the electrostatic buffering unit 30, and the risk of the second signal line 20 being damaged by the static electricity can be reduced.

In another embodiment, as shown with reference to fig. 3, the first signal line 10 has a first edge Y1 and a second edge Y2 extending in the first direction x and arranged in the second direction Y; the electrostatic buffer unit 30 overlaps both the first edge Y1 and the second edge Y2 in the direction perpendicular to the substrate 1. In this embodiment, one electrostatic buffer unit 30 is disposed to overlap both the first edge Y1 and the second edge Y2, and static electricity on the first signal line 10 is stored and discharged through the buffer unit 30 to reduce the risk of the second signal line 20 being damaged by electrostatic shock.

In another embodiment, fig. 21 is a schematic partial top view of a first region of another display panel provided in an embodiment of the invention, and fig. 22 is a schematic cross-sectional view taken along the line C-C' of fig. 21.

As shown in fig. 21, the first signal line 10 includes a main body portion 11 and a protruding portion 12, the main body portion 11 extends in the first direction x, and the protruding portion 12 protrudes from the main body portion 11 in the second direction y in a direction away from the main body portion 11. As can be seen from fig. 22, the electrostatic buffer unit 30 overlaps the convex portion 12 in a direction e perpendicular to the plane of the substrate 1. In this embodiment, the shape of the first signal line 10 is designed such that the main body portion 11 extends in the extending direction of the first signal line 10 and the protruding portion 12 corresponds to an abrupt structure on the first signal line 10, and static electricity is likely to accumulate at the position of the protruding portion 12. The electrostatic buffering unit 30 is arranged to overlap the convex part 12 in the embodiment of the invention, and the electrostatic buffering unit 30 can store and release the static electricity accumulated at the position of the convex part 12, so that the risk that the second signal wire 20 is damaged by the static electricity is reduced.

Fig. 23 is a schematic view of a display device according to an embodiment of the present invention, and as shown in fig. 23, the display device includes a display panel 100 according to any embodiment of the present invention. The structure of the display panel 100 is already described in the above embodiments, and is not described herein again. The display device in the embodiment of the invention can be any equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a television, an intelligent watch and the like.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.