阅读说明：本技术 一种芯片防反向封装结构及封装方法 (Chip anti-reverse packaging structure and packaging method ) 是由 刘书利 王涛 章国涛 朱家昌 孟德喜 于 2021-08-24 设计创作，主要内容包括：本发明涉及一种微电子封装结构,尤其是一种芯片防反向封装结构及封装方法。一种芯片防反向封装结构,包括封装外壳和封装盖板,封装外壳内设有封装槽,封装盖板固定在封装槽的顶部,封装外壳上设有若干键合点,键合点与引脚连接；还包括：装片胶,装片胶分别与芯片的背面和封装槽粘结,将芯片固定在封装槽内；键合线,键合线设有若干个,用于键合点与芯片键合区的键合指的连接；及防反向硬质层,防反向硬质层覆盖在芯片正面的功能区。本发明提供的一种芯片防反向封装结构利用溅射方式在芯片功能区表面镀附防反向硬质层,有效地增强了芯片的防物理和化学反向性能,增加了芯片的安全性。(The invention relates to a microelectronic packaging structure, in particular to a chip anti-reverse packaging structure and a packaging method. A chip anti-reverse packaging structure comprises a packaging shell and a packaging cover plate, wherein a packaging groove is formed in the packaging shell, the packaging cover plate is fixed to the top of the packaging groove, a plurality of bonding points are arranged on the packaging shell, and the bonding points are connected with pins; further comprising: the chip mounting glue is respectively bonded with the back surface of the chip and the packaging groove, and the chip is fixed in the packaging groove; the bonding wires are provided with a plurality of bonding fingers and are used for connecting the bonding points with the bonding area of the chip; and the anti-reverse hard layer covers the functional area on the front surface of the chip. The chip anti-reverse packaging structure provided by the invention plates the anti-reverse hard layer on the surface of the chip functional area in a sputtering mode, so that the physical and chemical reverse resistance of the chip is effectively enhanced, and the safety of the chip is improved.)

1. A chip anti-reverse packaging structure comprises a packaging shell (1) and a packaging cover plate (5), wherein a packaging groove (10) is formed in the packaging shell (1), and the packaging cover plate (5) is fixed to the top of the packaging groove (10), and is characterized in that a plurality of bonding points (11) are arranged on the packaging shell (1), and the bonding points (11) are connected with pins; further comprising:

the chip mounting glue (6) is respectively bonded with the back surface of the chip (2) and the packaging groove (10), and the chip (2) is fixed in the packaging groove (10);

the bonding wires (4) are provided with a plurality of bonding points (11) which are used for connecting bonding points (11) with bonding fingers of a bonding area (21) of the chip (2); and

an anti-reverse hard layer (3), the anti-reverse hard layer (3) covering a functional region (22) on the front side of the chip (2).

2. The chip anti-reverse packaging structure according to claim 1, wherein the anti-reverse hard layer (3) is a high hardness ceramic layer.

3. The chip anti-reverse packaging structure according to claim 2, wherein the high hardness ceramic comprises: WC, TiN, TiNC, alumina, cubic BN.

4. The chip anti-reverse packaging structure according to claim 1, wherein the thickness of the anti-reverse hard layer (3) is 100-1000 nm.

5. Chip anti-reverse packaging structure according to any one of claims 1 to 4, wherein the bonding wire (4) is a gold wire, an aluminum wire or a copper wire.

6. The chip anti-reverse packaging structure according to any one of claims 1 to 4, wherein the packaging cover plate (5) is ceramic, metal or plastic resin.

7. A chip reverse packaging prevention method is characterized by comprising the following steps:

s20, forming an anti-reverse hard layer (3) on the functional region (22) of the chip (2) in an ion sputtering mode;

s30, fixing the chip (2) in a packaging groove (10) of the packaging shell (1) through the mounting glue (6);

s40, connecting the bonding fingers of the chip (2) with the bonding points (11) in the packaging shell (1) through bonding wires (4);

and S50, fixing the packaging cover plate (5) on the top of the packaging groove (10).

8. The method for preventing chip from being packaged reversely according to claim 7, further comprising a step S10 of placing the chip (2) on the mask jig (7) corresponding to the sputtering holes (71) on the mask jig (7), wherein the mask jig (7) covers the bonding regions (21) of the chip (2), and the functional regions (22) of the chip (2) are located in the sputtering holes (71).

9. The chip reverse-preventing packaging method according to claim 7, wherein the sputtering time is 10-30 min, and the sputtering thickness is 100-1000 nm.

10. The method for preventing the chip from being packaged reversely according to claim 7, wherein the mounting adhesive (6) is cured by heating, the heating temperature is 200-270 ℃, and the heating time is controlled to be 20-30 min.

Technical Field

The invention relates to a microelectronic packaging structure, in particular to a chip anti-reverse packaging structure and a packaging method.

Background

The packaging means that the chip is sealed in a shell in a certain mode, and then the chip is interconnected with structures such as a PCB (printed circuit board) through pins of a packaging shell, so that the function of the chip is realized. With the rapid development of the microelectronic field, the security requirement on the chip is increasingly enhanced, and the traditional packaging modes such as ceramic packaging, metal packaging, plastic packaging and the like cannot meet the requirements on the security, the leakage prevention and the like of the chip, so that the security packaging research on the chip is increasingly urgent.

At present, the security package mostly adopts means such as a built-in detection circuit, when a chip is attacked, the detection circuit is firstly damaged and sends a signal to the chip, so that a self-destruction device of the chip is started to ensure that chip information is not leaked. However, this secure packaging method occupies a large amount of chip design space, increases design cost, and most of the chips need to be powered to function. And is not favorable for protecting the information in the chip.

Disclosure of Invention

In order to solve the problems, the invention provides an anti-reverse packaging structure of a chip, which can effectively enhance the physical and chemical dissection prevention performance of the chip, and the specific technical scheme is as follows:

a chip anti-reverse packaging structure comprises a packaging shell and a packaging cover plate, wherein a packaging groove is formed in the packaging shell, the packaging cover plate is fixed to the top of the packaging groove, a plurality of bonding points are arranged on the packaging shell, and the bonding points are connected with pins; further comprising: the chip mounting glue is respectively bonded with the back surface of the chip and the packaging groove, and the chip is fixed in the packaging groove; the bonding wires are used for connecting bonding points with bonding fingers of the chip bonding area; and the anti-reverse hard layer covers the functional area on the front surface of the chip.

Preferably, the reverse hard prevention layer is a high-hardness ceramic layer.

Further, the high hardness ceramic includes: WC, TiN, TiNC, alumina, cubic BN.

Preferably, the thickness of the anti-reverse hard layer is 100-1000 nm.

The bonding wire is a gold wire, an aluminum wire or a copper wire.

Preferably, the package cover plate is made of ceramic, metal or plastic resin.

A chip reverse packaging prevention method comprises the following steps:

s20, forming an anti-reverse hard layer in the functional area of the chip by means of ion sputtering;

s30, fixing the chip in a packaging groove of a packaging shell through a mounting adhesive;

s40, connecting the bonding fingers of the chip with the bonding points in the packaging shell through bonding wires;

and S50, fixing the packaging cover plate on the top of the packaging groove.

Preferably, the method further includes step S10, placing the chip on the mask jig corresponding to the sputtering hole on the mask jig, wherein the mask jig covers the bonding region of the chip, and the functional region of the chip is located in the sputtering hole.

Preferably, the sputtering time is 10-30 min, and the sputtering thickness is 100-1000 nm.

Further, the mounting glue is cured by heating, the heating temperature is 200-270 ℃, and the heating time is controlled within 20-30 min.

Compared with the prior art, the invention has the following beneficial effects:

the chip anti-reverse packaging structure provided by the invention plates the anti-reverse hard layer on the surface of the chip functional area in a sputtering mode, so that the physical and chemical reverse resistance of the chip is effectively enhanced, and the safety of the chip is improved.

Drawings

FIG. 1 is a schematic diagram of a chip anti-reverse packaging structure;

fig. 2 is a schematic structural diagram of a mask jig.

Detailed Description

The invention will now be further described with reference to the accompanying drawings.

The chip anti-reverse packaging structure provided by the invention plates the anti-reverse hard layer on the surface of the chip functional area in a sputtering mode, and then packages the chip in a conventional mode, so that the operation is simple, the physical and chemical reverse resistance of the chip is effectively enhanced, and the safety of the chip is improved.

A chip anti-reverse packaging structure comprises a packaging shell 1, a packaging cover plate 5, a chip mounting adhesive 6, a bonding wire 4 and an anti-reverse hard layer 3; a packaging groove 10 is arranged in the packaging shell 1, a plurality of bonding points 11 are arranged on the packaging shell 1, the bonding points 11 are connected with pins, and the pins are fixed on the packaging shell 1 and are provided with a plurality of pins; the packaging cover plate 5 is fixed at the top of the packaging groove 10; the chip mounting glue 6 is respectively bonded with the back surface of the chip 2 and the bottom of the packaging groove 10, and the chip 2 is fixed at the bottom of the packaging groove 10; the bonding wires 4 are provided with a plurality of bonding points 11 for connecting bonding fingers of the bonding area 21 of the chip 2; the anti-reverse hard layer 3 covers the functional region 22 on the front surface of the chip 2, and the thickness of the anti-reverse hard layer 3 is 100-1000 nm.

The anti-reverse hard layer 3 is a high-hardness ceramic layer. The high-hardness ceramic includes: WC, TiN, TiNC, alumina, cubic BN.

WC, tungsten carbide ceramic; the hard ceramic material is a hard ceramic material consisting of carbon and tungsten, is a black hexagonal crystal, has metallic luster, and is characterized by having hardness similar to that of diamond and good wear-resisting property; the tungsten carbide has good acid and alkali corrosion resistance. These characteristics make the tungsten carbide anti-reverse coating have good function of preventing mechanical damage and corrosion damage.

TiN, titanium nitride ceramics; the hard ceramic material consists of nitrogen and titanium and has the characteristics of high melting point, high hardness and good chemical stability; these characteristics give the titanium nitride anti-reflective coating a good protection against mechanical and corrosive damage.

TiNC, titanium carbonitride ceramic; the ceramic material is a hard ceramic material consisting of three elements of carbon, nitrogen and titanium, and has the characteristics of high strength, high hardness, high temperature resistance, wear resistance, corrosion resistance, oxidation resistance and the like; these characteristics give the titanium carbonitride anti-reverse coating a good protection against mechanical and corrosive damage.

Cubic BN, cubic boron nitride ceramic: the hardness of the cubic boron nitride is close to that of diamond, and the cubic boron nitride has ultrahigh hardness, good thermal stability and chemical stability; these characteristics give the cubic boron nitride anti-reflective coating a good protection against mechanical and corrosive damage.

The materials all belong to hard ceramic materials and have good heat-conducting property. The good heat-conducting property enables the anti-reverse coating to well conduct heat to be dissipated when the chip works, and the normal work of the chip is guaranteed.

The thickness of the anti-reverse coating is controlled within the range of 100-1000nm, on one hand, the thickness is easy to realize for the process of preparing the hard coating by sputtering, and the 100-1000nm hard coating can realize good mechanical and corrosion damage prevention effects; more importantly, the submicron (100-1000 nm) thickness anti-reflection coating can ensure good heat dissipation of the chip surface, and can not cause the problem of chip heat dissipation caused by the addition of the anti-reflection coating or the problem of thermal mismatch between the chip and the anti-reflection coating.

The bonding wire 4 is a gold wire, an aluminum wire or a copper wire.

The package cover 5 is made of ceramic, metal or plastic resin.

The mounting adhesive 6 is conductive, insulating, heat conductive or corrosion resistant. The conductive mounting adhesive can ensure the stability of chip mounting process on one hand, and can ensure the relatively consistent thermal expansion coefficient of a laminated system of 'curing mounting adhesive-chip-anti-reflection coating' on the other hand, thereby avoiding the problem of thermal mismatch of a chip structure.

A chip reverse packaging prevention method comprises the following steps:

s10, placing the chip 2 on the mask jig 7, wherein the mask jig 7 covers the bonding region 21 of the chip 2 and the functional region 22 of the chip 2 is positioned in the sputtering hole 71, and corresponds to the sputtering hole 71 on the mask jig 7;

s20, forming an anti-reverse hard layer 3 on the functional region 22 of the chip 2 in an ion sputtering mode;

s30, fixing the chip 2 in the packaging groove 10 of the packaging shell 1 through the mounting glue 6;

s40, connecting the bonding fingers of the chip 2 with the bonding points 11 in the packaging shell 1 through bonding wires 4;

s50, the package cover 5 is fixed to the front surface of the package case 1 by an adhesive method, a tin-gold solder welding method, or a parallel sealing method, and the package groove 10 is closed.

Wherein the sputtering time is 10-30 min, and the sputtering thickness is 100-1000 nm.

The mounting glue 6 is cured by heating, the heating temperature is 200-270 ℃, and the heating time is controlled within 20-30 min.

The mask jig 7 is provided with a plurality of sputtering holes 71, and the plurality of sputtering holes 71 can sputter the plurality of chips 2 simultaneously against the hard layer 3. The size of the sputtering holes 71 is consistent with that of the functional regions 22 of the chip 2, and the mask jig 7 covers the bonding regions 21 of the chip 2 to prevent the bonding regions 21 from being covered by the anti-reverse hardening layer without affecting the subsequent bonding.

Example one

A chip anti-reverse packaging structure comprises a packaging shell 1, a packaging cover plate 5, a chip mounting adhesive 6, a bonding wire 4 and an anti-reverse hard layer 3; a packaging groove 10 is arranged in the packaging shell 1, a plurality of bonding points 11 are arranged on the packaging shell 1, and the bonding points 11 are connected with pins; the packaging cover plate 5 is fixed at the top of the packaging groove 10; the chip mounting glue 6 is respectively bonded with the back surface of the chip 2 and the packaging groove 10, and the chip 2 is fixed at the bottom of the packaging groove 10; the bonding wires 4 are provided with a plurality of bonding points 11 for connecting bonding fingers of the bonding area 21 of the chip 2; the anti-reverse hard layer 3 covers the functional region 22 on the front surface of the chip 2, and the thickness of the anti-reverse hard layer 3 is 300 nm.

The anti-reverse hard layer 3 is a TiN layer, the bonding wire 4 is a gold wire, and the packaging cover plate 5 is a ceramic cover plate.

A chip reverse packaging prevention method comprises the following steps:

s10, placing the chip 2 on the mask jig 7, wherein the mask jig 7 covers the bonding region 21 of the chip 2 and the functional region 22 of the chip 2 is positioned in the sputtering hole 71, and corresponds to the sputtering hole 71 on the mask jig 7;

s20, forming an anti-reverse hard layer 3 in the functional region 22 of the chip 2 in an ion sputtering mode, wherein the sputtering time is 15min, the sputtering thickness is 300nm, and the sputtering material is TiN;

s30, fixing the chip 2 in the packaging groove 10 of the packaging shell 1 through the mounting adhesive 6, and curing the mounting adhesive 6 by heating, wherein the heating temperature is 200 ℃, and the heating time is controlled to be 20 min;

s40, connecting the bonding fingers of the chip 2 with the bonding points 11 in the packaging shell 1 through bonding wires 4;

s50, the package cover 5 is fixed to the front surface of the package case 1 by adhesion, and the package groove 10 is closed.

Example two

A chip anti-reverse packaging structure comprises a packaging shell 1, a packaging cover plate 5, a chip mounting adhesive 6, a bonding wire 4 and an anti-reverse hard layer 3; a packaging groove 10 is arranged in the packaging shell 1, a plurality of bonding points 11 are arranged on the packaging shell 1, and the bonding points 11 are connected with pins; the packaging cover plate 5 is fixed at the top of the packaging groove 10; the chip mounting glue 6 is respectively bonded with the back surface of the chip 2 and the packaging groove 10, and the chip 2 is fixed at the bottom of the packaging groove 10; the bonding wires 4 are provided with a plurality of bonding points 11 for connecting bonding fingers of the bonding area 21 of the chip 2; the anti-reverse hard layer 3 covers the functional region 22 on the front surface of the chip 2, and the thickness of the anti-reverse hard layer 3 is 600 nm.

The anti-reverse hard layer 3 is a TiN layer, the bonding wire 4 is an aluminum wire, and the packaging cover plate 5 is a metal cover plate.

A chip reverse packaging prevention method comprises the following steps:

s10, placing the chip 2 on the mask jig 7, wherein the mask jig 7 covers the bonding region 21 of the chip 2 and the functional region 22 of the chip 2 is positioned in the sputtering hole 71, and corresponds to the sputtering hole 71 on the mask jig 7;

s20, forming an anti-reverse hard layer 3 in the functional region 22 of the chip 2 in an ion sputtering mode, wherein the sputtering time is 30min, the sputtering thickness is 600nm, and the sputtering material is TiN;

s30, fixing the chip 2 in the packaging groove 10 of the packaging shell 1 through the mounting adhesive 6, and curing the mounting adhesive 6 by heating, wherein the heating temperature is 210 ℃, and the heating time is controlled to be 25 min;

s40, connecting the bonding fingers of the chip 2 with the bonding points 11 in the packaging shell 1 through bonding wires 4;

s50, the package cover 5 is fixed to the front surface of the package case 1 by soldering with tin-gold solder, and the package groove 10 is closed.

EXAMPLE III

A chip anti-reverse packaging structure comprises a packaging shell 1, a packaging cover plate 5, a chip mounting adhesive 6, a bonding wire 4 and an anti-reverse hard layer 3; a packaging groove 10 is arranged in the packaging shell 1, a plurality of bonding points 11 are arranged on the packaging shell 1, and the bonding points 11 are connected with pins; the packaging cover plate 5 is fixed at the top of the packaging groove 10; the chip mounting glue 6 is respectively bonded with the back surface of the chip 2 and the packaging groove 10, and the chip 2 is fixed at the bottom of the packaging groove 10; the bonding wires 4 are provided with a plurality of bonding points 11 for connecting bonding fingers of the bonding area 21 of the chip 2; the anti-reverse hard layer 3 covers the functional region 22 on the front surface of the chip 2, and the thickness of the anti-reverse hard layer 3 is 500 nm.

The anti-reverse hard layer 3 is a TiNC layer, the bonding wire 4 is a copper wire, and the packaging cover plate 5 is a plastic resin cover plate.

A chip reverse packaging prevention method comprises the following steps:

s10, placing the chip 2 on the mask jig 7, wherein the mask jig 7 covers the bonding region 21 of the chip 2 and the functional region 22 of the chip 2 is positioned in the sputtering hole 71, and corresponds to the sputtering hole 71 on the mask jig 7;

s20, forming an anti-reverse hard layer 3 in the functional area 22 of the chip 2 in an ion sputtering mode, wherein the sputtering time is 20min, the sputtering thickness is 500nm, and the sputtering material is TiNC;

s30, fixing the chip 2 in the packaging groove 10 of the packaging shell 1 through the mounting adhesive 6, and curing the mounting adhesive 6 by heating, wherein the heating temperature is 250 ℃, and the heating time is controlled to be 30 min;

s40, connecting the bonding fingers of the chip 2 with the bonding points 11 in the packaging shell 1 through bonding wires 4;

and S50, fixing the packaging cover plate 5 on the front surface of the packaging shell 1 in a parallel sealing and welding mode, and sealing the packaging groove 10.

Example four

A chip anti-reverse packaging structure comprises a packaging shell 1, a packaging cover plate 5, a chip mounting adhesive 6, a bonding wire 4 and an anti-reverse hard layer 3; a packaging groove 10 is arranged in the packaging shell 1, a plurality of bonding points 11 are arranged on the packaging shell 1, and the bonding points 11 are connected with pins; the packaging cover plate 5 is fixed at the top of the packaging groove 10; the chip mounting glue 6 is respectively bonded with the back surface of the chip 2 and the packaging groove 10, and the chip 2 is fixed at the bottom of the packaging groove 10; the bonding wires 4 are provided with a plurality of bonding points 11 for connecting bonding fingers of the bonding area 21 of the chip 2; the anti-reverse hard layer 3 covers the functional region 22 on the front surface of the chip 2, and the thickness of the anti-reverse hard layer 3 is 1000 nm.

The anti-reverse hard layer 3 is an alumina layer, the bonding wire 4 is a gold wire, and the packaging cover plate 5 is a ceramic cover plate.

A chip reverse packaging prevention method comprises the following steps:

s10, placing the chip 2 on the mask jig 7, wherein the mask jig 7 covers the bonding region 21 of the chip 2 and the functional region 22 of the chip 2 is positioned in the sputtering hole 71, and corresponds to the sputtering hole 71 on the mask jig 7;

s20, forming an anti-reverse hard layer 3 in the functional region 22 of the chip 2 in an ion sputtering mode, wherein the sputtering time is 20min, the sputtering thickness is 1000nm, and the sputtering material is aluminum oxide;

s30, fixing the chip 2 in the packaging groove 10 of the packaging shell 1 through the mounting adhesive 6, and curing the mounting adhesive 6 by heating, wherein the heating temperature is 270 ℃, and the heating time is controlled to be 30 min;

s40, connecting the bonding fingers of the chip 2 with the bonding points 11 in the packaging shell 1 through bonding wires 4;

s50, the package cover 5 is fixed to the front surface of the package case 1 by adhesion, and the package groove 10 is closed.

The working principle of the invention is as follows: the anti-reverse hard layer 3 has the characteristics of high hardness, high wear resistance, acid-base corrosion resistance, high thermal conductivity, thermal expansion coefficient matched with Si and the like, and the chip 2 can resist conventional reverse means such as polishing, etching, acid corrosion and the like through the preparation of the anti-reverse hard layer 3, so that the structural information of the chip 2 is protected, and the structural content of the chip 2 is not stolen.

The chip anti-reverse packaging structure and the packaging method provided by the invention have the advantages that the anti-reverse hard layer is plated on the surface of the chip functional area in a sputtering mode, and then the chip is packaged in a conventional mode, so that the operation is simple, the physical and chemical reverse resistance of the chip is effectively enhanced, and the safety of the chip is improved.

The above description is only for the purpose of illustrating the four preferred embodiments of the present invention, and is not intended to limit the present invention, and those skilled in the art can utilize the above methods to make various changes and modifications to the technical solutions of the present invention, or to modify the technical solutions of the present invention into equivalent embodiments without departing from the scope of the present invention. Therefore, any modifications and equivalent changes made according to the technical spirit of the present invention are within the technical scope of the present invention, unless the technical spirit of the present invention departs from the content of the technical solution of the present invention.