阅读说明：本技术 半导体封装装置 (Semiconductor packaging device ) 是由 呂文隆 于 2021-08-23 设计创作，主要内容包括：本公开涉及半导体封装装置。该半导体封装装置包括：基板；第一芯片,设置于基板上,主动面设置有第一延伸线路,第一延伸线路延伸至第一芯片主动面的边缘；第二芯片,设置于基板上,主动面设置有第二延伸线路,第二延伸线路延伸至第二芯片主动面的边缘,第二芯片与第一芯片之间设置有间隙；桥接模块,设置于间隙,并电连接第一延伸线路和第二延伸线路；以提高第一芯片与第二芯片之间电连接对接的精准度。(The present disclosure relates to semiconductor packaging devices. The semiconductor package device includes: a substrate; the first chip is arranged on the substrate, the active surface of the first chip is provided with a first extension line, and the first extension line extends to the edge of the active surface of the first chip; the second chip is arranged on the substrate, the active surface of the second chip is provided with a second extension line, the second extension line extends to the edge of the active surface of the second chip, and a gap is formed between the second chip and the first chip; the bridging module is arranged in the gap and electrically connected with the first extension line and the second extension line; so as to improve the accuracy of the electric connection and butt joint between the first chip and the second chip.)

1. A semiconductor package device, comprising:

a substrate;

the first chip is arranged on the substrate, the active surface of the first chip is provided with a first extension line, and the first extension line extends to the edge of the active surface of the first chip;

the second chip is arranged on the substrate, a second extending line is arranged on the active surface of the second chip, the second extending line extends to the edge of the active surface of the second chip, and a gap is formed between the second chip and the first chip;

and the bridge module is arranged in the gap and electrically connected with the first extension line and the second extension line.

2. The device of claim 1, wherein the bridge module comprises a bridge circuit and a first guiding wall corresponding to the first chip and a second guiding wall corresponding to the second chip, and the bridge circuit is at least partially disposed on the first guiding wall and the second guiding wall and electrically connected to the first extending circuit and the second extending circuit, respectively.

3. The device of claim 2, wherein the bridging line disposed on the first and second guide walls is at least partially exposed above the first and second extended lines.

4. The apparatus of claim 2, wherein the bridge module comprises a first surface disposed opposite the substrate and a second surface opposite the first surface, the first surface having an area smaller than an area of the second surface.

5. The device of claim 4, wherein a distance between the first and second guide walls tapers from the second surface to the first surface.

6. The device of claim 2, wherein the bridge wire comprises a solder material.

7. The apparatus of claim 1, wherein the bridge module has a gap with the substrate.

8. The apparatus of claim 1, wherein a length of the bridge module extending from the plane of the first extension line toward the substrate is less than a height of the first chip or the second chip.

9. The device of claim 1, wherein a height of a portion of the bridge module between the plane of the second extension line and the substrate is less than a height of the second chip.

10. The apparatus of claim 1, wherein the bridge module comprises a support structure.

Technical Field

The present disclosure relates to the field of semiconductor packaging technology, and more particularly, to a semiconductor packaging apparatus.

Background

Currently, Die Bonding (DB) Bonding Accuracy (precision) is 3 microns, and it is necessary to use a Charge Coupled Device (CCD) positioning Device, and if DB is thinner, for example, 2 microns or less, in the future, the Accuracy challenge is faced. For example, in the fan-out chip structure on the substrate at present, if the displacement of the bridge chip is greater than 3 microns during DB bridge chip, the problem that the chips cannot be aligned during the subsequent fabrication of the rewiring layer fine line will be caused.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a semiconductor package device, including:

a substrate;

the first chip is arranged on the substrate, the active surface of the first chip is provided with a first extension line, and the first extension line extends to the edge of the active surface of the first chip;

the second chip is arranged on the substrate, a second extending line is arranged on the active surface of the second chip, the second extending line extends to the edge of the active surface of the second chip, and a gap is formed between the second chip and the first chip;

and the bridge module is arranged in the gap and electrically connected with the first extension line and the second extension line.

In some optional embodiments, the bridge module includes a bridge line, and a first guiding wall disposed corresponding to the first chip and a second guiding wall disposed corresponding to the second chip, and the bridge line is at least partially disposed on the first guiding wall and the second guiding wall and electrically connects the first extension line and the second extension line, respectively.

In some alternative embodiments, the bridge wire provided to the first and second guide walls is at least partially exposed above the first and second extended wires.

In some optional embodiments, the bridge module includes a first surface disposed opposite the substrate and a second surface opposite the first surface, the first surface having an area smaller than an area of the second surface.

In some alternative embodiments, the distance between the first guide wall and the second guide wall is gradually reduced from the second surface to the first surface.

In some alternative embodiments, the bridge wire comprises a solder material.

In some optional embodiments, an included angle between the first guiding wall and the active surface of the first chip is greater than 30 degrees and less than 80 degrees, and an included angle between the second guiding wall and the active surface of the second chip is greater than 30 degrees and less than 80 degrees.

In some alternative embodiments, the bridge module has a gap between the bridge module and the substrate.

In some optional embodiments, a length of the bridge module extending from the plane of the first extension line to the substrate is less than a height of the first chip or the second chip.

In some optional embodiments, a height of a portion of the bridge module between the plane of the second extension line and the substrate is smaller than a height of the second chip.

In some alternative embodiments, the bridge module comprises a support structure.

In some optional embodiments, the apparatus further comprises:

the circuit layer is arranged on the substrate, and the first chip, the second chip and the bridge module are arranged in the circuit layer.

In some optional embodiments, the apparatus further comprises:

and the electric connecting piece is arranged on the circuit layer.

In a second aspect, embodiments of the present disclosure provide a method for manufacturing a semiconductor package device, including:

providing a first chip and a second chip;

arranging a first extension line on the active surface of the first chip, wherein the first extension line extends to the edge of the active surface of the first chip;

arranging a second extension line on the active surface of the second chip, wherein the second extension line extends to the edge of the active surface of the second chip;

providing a substrate;

arranging the first chip on the substrate, and arranging the second chip on the substrate, wherein a gap is arranged between the second chip and the first chip;

and arranging a bridge module in the gap and electrically connecting the first extension line and the second extension line.

In some optional embodiments, the bridge module is obtained according to the following steps:

providing a carrier plate, wherein a support structure and a dielectric layer coating the support structure are arranged on the carrier plate;

removing a portion of the dielectric layer to form a first guiding surface and a second guiding surface;

forming a bridge line at least partially disposed on the first and second guide surfaces to form the bridge module.

According to the semiconductor packaging device and the manufacturing method thereof, the bridging module is arranged in the gap between the first chip and the second chip, the active surfaces of the first chip and the second chip are respectively provided with the first extension line and the second extension line which extend to the edge of the corresponding active surface, and the first extension line and the second extension line are electrically connected through the bridging module, so that the first chip and the second chip are electrically connected, and the accuracy of the electric connection and butt joint between the first chip and the second chip is improved.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1A is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure;

1B-1J are schematic longitudinal cross-sectional structures of various embodiments of semiconductor packaging devices according to the present disclosure;

fig. 2A-2L are cross-sectional views of a semiconductor package device fabricated at various stages according to one embodiment of the present disclosure.

Description of the symbols:

11-a substrate; 12-a first chip; 121-a first extension line; 13-a second chip; 131-a second extension line; 14-a bridge module; 141-bridge line; 14 a-a first guide wall; 14 b-a second guide wall; 14 c-a first surface; 14 d-a second surface; 142-a support structure; 143-welding material; 15-clearance; 16-a line layer; 17-electrical connections; 18-routing; 19-passive electronic components; 21-a first carrier plate; 22-a second carrier plate; 23-a wafer; 24-an extended line layer; 25-dielectric layer.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.

Referring to fig. 1A, fig. 1A is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device of the present disclosure. As shown in fig. 1A, the semiconductor package device 100A may include: substrate 11, first chip 12, second chip 13 and bridge module 14. Wherein:

the substrate 11 may be a substrate composed of a conductive material and a Dielectric material (Dielectric). Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic substances such as silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The first chip 12 is disposed on the substrate 11, the active surface of the first chip is provided with a first extension line 121, and the first extension line 121 extends to an edge of the active surface of the first chip 12.

And a second chip 13 disposed on the substrate 11, wherein the active surface is provided with a second extension line 131, the second extension line 131 extends to the edge of the active surface of the second chip 13, and a gap 15 is disposed between the second chip 13 and the first chip 12.

The types of the first chip 12 and the second chip 13 are not particularly limited in this disclosure, the first chip 12 and the second chip 13 may be the same type or different types of chips, and the first chip 12 and the second chip 13 may include, for example, a die (die), an ASIC (Application Specific Integrated Circuit) chip, a Power Management Integrated Circuit (PMIC) chip, or an HBM (High Bandwidth Memory) chip.

The first and second extension lines 121 and 131 may be line layers composed of wire traces and a Dielectric material (Dielectric). Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fiber (PA), PI, Epoxy resin (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 Epoxy glass cloth laminate, PP, ABF, etc., and inorganic substances may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The bridge module 14 is disposed in the gap 15 and electrically connects the first extension line 121 and the second extension line 131.

The bridge module 14 may be a module composed of wire traces and a dielectric material.

In some alternative embodiments, as shown in fig. 1A, the bridge module 14 includes a bridge circuit 141 and a first guiding wall 14a disposed corresponding to the first chip 12 and a second guiding wall 14b disposed corresponding to the second chip 13, and the bridge circuit 141 is at least partially disposed on the first guiding wall 14a and the second guiding wall 14b and electrically connected to the first extension circuit 121 and the second extension circuit 131, respectively.

The first and second guiding walls 14a and 14b are oblique sides of the bridge module 14 opposite to the first and second chips 12 and 13, and the bridge module 14 can be guided into the gap 15 by the first and second guiding walls 14a and 14b during the manufacturing process of the semiconductor package device 100A to achieve the positioning of the bridge module 14.

In some alternative embodiments, as shown in fig. 1A, the bridge wiring 141 provided to the first and second guide walls 14a and 14b is at least partially exposed above the first and second extended wirings 121 and 131.

In some alternative embodiments, as shown in fig. 1A, the bridge module 14 includes a first surface 14c disposed opposite the substrate 11 and a second surface 14d opposite the first surface 14c, and the area of the first surface 14c is smaller than that of the second surface 14 d.

In some alternative embodiments, as shown in fig. 1A, the distance between the first and second guide walls 14a and 14b gradually decreases from the second surface 14d to the first surface 14 c.

It will be appreciated that in some alternative embodiments, the bridge module 14 is prismoid in shape.

In some alternative embodiments, as shown in fig. 1A, the bridge wire 141 includes a solder material 143.

In some alternative embodiments, as shown in fig. 1A, there is a gap between the bridge module 14 and the substrate 11.

In some alternative embodiments, the length of the bridge module 14 extending from the plane of the first extension line 121 to the substrate 11 is less than the height of the first chip 12 or the second chip 13.

In some alternative embodiments, the height of the portion of the bridge module 14 between the plane of the second extension line 131 and the substrate 11 is less than the height of the second chip 13.

In some alternative embodiments, as shown in fig. 1A, the bridge module 14 may include a support structure 142.

Here, the support structure 142 may include a material capable of providing rigid support, such as a Die (Die), etc.

In some alternative embodiments, as shown in fig. 1A, the semiconductor package device 100A may further include: the circuit layer 16 is disposed on the substrate 11, and the first chip 12, the second chip 13 and the bridge module 14 are disposed in the circuit layer 16.

The wiring layer 16 may be a wiring layer or a redistribution layer composed of conductive traces and Dielectric material (Dielectric). It should be noted that, currently known or future developed redistribution layer forming techniques may be adopted in the manufacturing process, and the disclosure is not limited thereto, and for example, the redistribution layer may be formed by using processes including but not limited to photolithography, electroplating (plating), Electroless plating (electroplating), and the like. Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fiber (PA), PI, Epoxy resin (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 Epoxy glass cloth laminate, PP, ABF, etc., and inorganic substances may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The line layer 16 may also include interconnect structures (interconnects), such as Conductive traces (Conductive traces), Conductive vias (Conductive vias), and the like. Here, the conductive via may be a through hole, a buried hole, or a blind hole, and the through hole, the buried hole, or the blind hole may be filled with a conductive material such as a metal or a metal alloy, where the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

In some alternative embodiments, as shown in fig. 1A, the semiconductor package device 100A may further include: and the electric connector 17 is arranged on the circuit layer 16.

The electrical connection members 17 may be, for example, Solder balls (Solder balls), Solder bumps (Solder bumps), Conductive pillars (Conductive balls), Solder pads (Solder pads), or the like.

Referring now to fig. 1B, fig. 1B is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100B of a semiconductor package device according to the present disclosure. The semiconductor package device 100B shown in fig. 1B is similar to the semiconductor package device 100A shown in fig. 1A, except that in the semiconductor package device 100B, the conductive vias included in the circuit layer 16 have their holes filled with a conductive material.

Referring now to fig. 1C, fig. 1C is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100C of a semiconductor package device according to the present disclosure. As shown in fig. 1C, the first chip 12 and the second chip 13 disposed on the substrate 11 in the present disclosure may include: the inactive surfaces of the first chip 12 and the second chip 13 are attached to the chip provided on the substrate 11.

Referring now to fig. 1D, fig. 1D is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100D of a semiconductor package device according to the present disclosure. As shown in fig. 1D, the first chip 12 and the second chip 13 disposed on the substrate 11 in the present disclosure may include: the active surface of the first chip 12 and the active surface of the second chip 13 are disposed toward the substrate 11, or the inactive surface of the first chip 12 and the inactive surface of the second chip 13 are disposed toward the substrate 11.

Referring now to fig. 1E, fig. 1E is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100E of a semiconductor package device according to the present disclosure. The semiconductor package apparatus 100E shown in fig. 1E is similar to the semiconductor package apparatus 100A shown in fig. 1A except that in the semiconductor package apparatus 100E, the wiring layer 16 may be a rewiring layer including at least one layer of a circuit.

Referring now to fig. 1F, fig. 1F is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100F of a semiconductor package device according to the present disclosure. The semiconductor package device 100F shown in fig. 1F is similar to the semiconductor package device 100A shown in fig. 1A, except that in the semiconductor package device 100F, there is further included: wire bonding 18 and passive electronic components 19. The routing 18 is disposed in the circuit layer 16, and the second chip 13 can be electrically connected to the substrate 11 through the routing 18; the passive electronic element 19 is disposed on the substrate 11 and located between the substrate 11 and the bridge module 14 and the substrate 11.

The passive electronic components 19, i.e. passive devices, may be, for example: capacitance, resistance, inductance, etc.

Referring now to fig. 1G, fig. 1G is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100G of a semiconductor package device according to the present disclosure. The semiconductor package device 100G shown in fig. 1G is similar to the semiconductor package device 100A shown in fig. 1A, except that the same structures as the first chip 12, the second chip 13, the bridge module 14 and the circuit layer 16 on the substrate 11 are disposed below the substrate 11, and the structures on the upper and lower sides of the substrate 11 are corresponding, and are not repeated herein.

Referring next to fig. 1H, fig. 1H is a schematic longitudinal cross-sectional structure of one embodiment 100H of a semiconductor package device according to the present disclosure. The semiconductor package device 100H shown in fig. 1H is similar to the semiconductor package device 100A shown in fig. 1A, except that the height of the first chip 12 is different from the height of the second chip 13, and the bridge module 14 is obliquely disposed in the gap 15 to electrically connect the first extension line 121 and the second extension line 131.

Referring now to fig. 1I, fig. 1I is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100I of a semiconductor package device according to the present disclosure. The semiconductor package device 100I shown in fig. 1I is similar to that shown in fig. 1A, except that the bridge module 14 is obliquely disposed in the gap 15.

Here, the bridge module 14 is disposed obliquely with respect to the first surface 14c of the bridge module 14 disposed parallel to the substrate 11.

In the embodiment of the present disclosure, an included angle between the first guiding wall 14a and the active surface of the first chip 12 is greater than 30 degrees and less than 80 degrees, and an included angle between the second guiding wall 14b and the active surface of the second chip 13 is greater than 30 degrees and less than 80 degrees.

Referring next to fig. 1J, fig. 1J is a schematic longitudinal cross-sectional structure of one embodiment 100J of a semiconductor package device according to the present disclosure. The semiconductor package device 100J shown in fig. 1J is similar to fig. 1A, except that the substrate 11 and the second chip 13 may include conductive vias.

Referring now to fig. 2A to 2L, fig. 2A to 2L are schematic longitudinal sectional structural views of semiconductor package devices 200A, 200B, 200C, 200D, 200E, 200F, 200G, 200H, 200I, 200J, 200K, and 200L manufactured at various stages according to one embodiment of the present disclosure.

Referring to fig. 2A, a wafer 23 is provided, and an extended circuit layer 24 is disposed on an active surface of the wafer 23.

Referring to fig. 2B, cut to form the first chip 12, the active surface of the first chip 12 is provided with a first extension line 121.

It is understood that the second chip 13 and the second extension line 131 disposed on the active surface of the second chip 13 are completely corresponding to the first chip 12 and the first extension line 121, and can be obtained through the same steps as those in fig. 2A and 2B, and are not described herein again.

Referring to fig. 2C, the first chip 12 is obtained.

Referring to fig. 2D, a first carrier 21 is provided, and a support structure 142 is disposed on the first carrier 21.

Here, a plurality of support structures 142 may be disposed on the first carrier 21 at intervals.

Referring to fig. 2E, a dielectric layer 25 is disposed on the first carrier 21, and the dielectric layer 25 covers the support structure 142.

Referring to fig. 2F, a portion of the dielectric layer 25 is removed such that the remaining dielectric material covering the support structure 142 forms the first and second guide walls 14a and 14 b.

Here, a portion of the dielectric layer 25 may be removed by etching, which may include laser etching or Plasma (Plasma) etching.

Referring to fig. 2G, first, a bridge line 141 is disposed on the dielectric material.

Then, a solder material is provided on the bridge wiring 141 to form the bridge module 14.

Referring to fig. 2H, a second carrier 22 is provided, and the bridge module 14 is disposed on the second carrier 22.

Referring to fig. 2I, a substrate 11 is provided, and a first chip 12 inactive side and a second chip 13 inactive side are disposed on the substrate 11.

Referring to fig. 2J, the gap 15 between the first chip 12 and the second chip 13 is bonded to the bridge module 14, so that the bridge module 14 is electrically connected to the first extension line 121 and the second extension line 131.

For example, Flip Chip Bonding (FCB), Thermal Compression Bonding (TCB), or the like may be used for the electrical connection process.

Referring to fig. 2K, the second carrier 22 is removed after being flipped.

Referring to fig. 2L, a circuit layer 16 is disposed on the substrate 11, and the circuit layer 16 covers the first chip 12, the second chip 13 and the bridge module 14.

An electrical connection 17 is provided on the wiring layer 16.

Here, the electrical Connection member 17 may be provided on the wiring layer 16 by a flip Chip bonding (C4) method.

The method for manufacturing the semiconductor packaging device provided by the present disclosure can achieve similar technical effects to the aforementioned semiconductor packaging device, and is not described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.