阅读说明：本技术 三相全桥封装芯片 (Three-phase full-bridge packaged chip ) 是由 张小兵 廖光朝 于 2021-08-30 设计创作，主要内容包括：本发明实施例公开了一种三相全桥封装芯片。其包括基底、三个第一功率晶粒和三个第二功率晶粒；三个第一功率晶粒构成三相全桥的上桥臂,三个第二功率晶粒构成三相全桥的下桥臂；基底包括第一基岛区、第二基岛区和拉筋区；拉筋区围绕第一基岛区、以及围绕第二基岛区；三个第一功率晶粒均设置于第一基岛区,每一第二功率晶粒设置于每一第二基岛区；三个第一功率晶粒分别对应与一个第二功率晶粒连接。本方案设计的三相全桥封装芯片可以减小全桥的功率模块的设计体积,利用基底设计固定承载第一功率晶粒和第二功率晶粒的线路框架替代部分全桥的功率模块的连接线路,简化了全桥的功率模块的线路连接,实现高度集成的三相全桥封装芯片的封装设计。(The embodiment of the invention discloses a three-phase full-bridge packaged chip. The device comprises a substrate, three first power crystal grains and three second power crystal grains; the three first power crystal grains form an upper bridge arm of a three-phase full bridge, and the three second power crystal grains form a lower bridge arm of the three-phase full bridge; the substrate comprises a first base island region, a second base island region and a tie bar region; the tie bar region surrounds the first foundation island region and surrounds the second foundation island region; three first power crystal grains are arranged in the first base island region, and each second power crystal grain is arranged in each second base island region; the three first power crystal grains are respectively correspondingly connected with one second power crystal grain. The three-phase full-bridge package chip of this scheme design can reduce the design volume of the power module of full-bridge, utilizes the fixed circuit frame that bears first power crystalline grain and second power crystalline grain of basement design to replace the interconnecting link of the power module of part full-bridge, has simplified the line connection of the power module of full-bridge, realizes the package design of highly integrated three-phase full-bridge package chip.)

1. A three-phase full-bridge packaged chip is characterized by comprising a substrate, three first power crystal grains and three second power crystal grains; the three first power crystal grains form an upper bridge arm of the three-phase full bridge, and the three second power crystal grains form a lower bridge arm of the three-phase full bridge;

the substrate comprises a first base island region, a second base island region and a tie bar region; the tie bar region surrounds the first foundation island region and surrounds the second foundation island region; three of the first power dies are arranged in the first base island region, and each of the second power dies is arranged in each of the second base island regions; the three first power crystal grains are respectively correspondingly connected with one second power crystal grain.

2. The three-phase full-bridge packaged chip according to claim 1, wherein one of the first power dies and one of the second power dies form a leg of the three-phase full bridge; the first power die and the second power die each include a first pole, a second pole, and a gate;

the first pole of the first power crystal grain is connected with a power supply, the grid electrodes of the first power crystal grain and the second power crystal grain are both connected with a control signal, the second pole of the first power crystal grain is connected with the first pole of the second power crystal grain, and the second pole of the second power crystal grain is grounded.

3. The three-phase full-bridge packaged chip according to claim 1, wherein the first base island region comprises a first edge, a second edge, a third edge and a fourth edge which are connected end to end, and the second base island region comprises a fifth edge, a sixth edge, a seventh edge and an eighth edge which are connected end to end; the first edge and the seventh edge are parallel and adjacent to each other;

the lacing wire area comprises a first patterned structure, a second patterned structure and a third patterned structure;

the first patterned structure is arranged outside a third edge of the first foundation island region; the second patterned structure is disposed between the first edge and the seventh edge; the third patterned structure is disposed outside the second edge, or the third patterned structure is disposed outside the fourth edge.

4. The three-phase full-bridge packaged chip according to claim 3, wherein a side of the first patterned structure away from the third edge is provided with a first recessed region;

the three-phase full-bridge packaged chip further comprises a first bonding pad, and the first bonding pad is arranged in the first depressed area.

5. The three-phase full-bridge packaged chip according to claim 4, wherein three of the second island regions are adjacently arranged;

the lacing wire area further comprises a fourth patterned structure, a fifth patterned structure and a sixth patterned structure;

a part of the fourth patterned structure is disposed between a sixth edge and an eighth edge of the second base island region adjacent thereto, and another part of the fourth patterned structure is disposed between a seventh edge of the second base island region at the outer side and the second patterned structure; the fifth patterned structure is disposed outside a fifth edge of the second foundation island region; the sixth patterned structure is disposed outside a sixth edge of the second foundation island region at the outside, or the sixth patterned structure is disposed outside an eighth edge of the second foundation island region at the outside.

6. The three-phase full-bridge packaged chip according to claim 5, wherein a side of the fifth patterned structure away from the fifth edge is provided with a second recessed region;

the three-phase full-bridge packaged chip further comprises a second bonding pad and a third bonding pad, and the second bonding pad and the third bonding pad are arranged in the second depressed area.

7. The three-phase full-bridge packaged chip according to claim 6, wherein one of the first power dies and one of the second power dies form a leg of the three-phase full bridge; the first power die and the second power die each include a first pole, a second pole, and a gate;

a first pole of the first power crystal grain is connected with a first base island region, a grid of the first power crystal grain is connected with a first bonding pad, a second pole of the first power crystal grain is connected with a second base island region, a first pole of the second power crystal grain is connected with the second base island region, a second pole of the second power crystal grain is connected with a second bonding pad, and a grid of the second power crystal grain is connected with a third bonding pad; the first pad and the third pad are connected to a control signal interface, and the second pad is grounded.

8. The three-phase full-bridge packaged chip according to claim 6, further comprising an encapsulation layer;

the encapsulation layer encapsulates all portions of the substrate except the first foundation island region, the second foundation island region, the first pad, the second pad, and the third pad.

9. The three-phase full bridge packaged chip according to claim 1, further comprising transition regions between said tie bar regions, between said tie bar region and said first base island region, and between said tie bar region and said second base island region; the thickness of the substrate corresponding to the transition region is smaller than that of the substrate corresponding to the first basal island region, and the thickness of the substrate corresponding to the transition region is smaller than that of the substrate corresponding to the second basal island region.

10. The three-phase full-bridge packaged chip according to claim 1, wherein the substrate is hollowed out in a region corresponding to the tie bar region.

Technical Field

The embodiment of the invention relates to the technical field of chip packaging, in particular to a three-phase full-bridge packaged chip.

Background

At present, a full-bridge Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) power module is formed by combining 6 MOSFET single tubes or 3 half-bridge packaged MOSFET single tubes (2 MOSFET crystal grains are packaged in each MOSFET single tube) on a water pump or a motor control board, so that three-phase working voltage is generated and applied to the pump or the motor. The power module that carries out the combination through the MOSFET single tube that adopts 6 MOSFET single tubes or 3 half-bridge encapsulation not only needs fix on water pump or motor control board each MOSFET single tube, still needs carry out the line connection to each MOSFET single tube, can lead to the metal oxide semiconductor field effect transistor power module volume of full-bridge too big at this in-process, and the integrated level is low and the circuit is complicated.

Disclosure of Invention

The embodiment of the invention provides a three-phase full-bridge packaged chip, which aims to reduce the design volume of a full-bridge power module, simplify the line connection of the full-bridge power module and realize a highly integrated three-phase full-bridge packaged chip.

In a first aspect, an embodiment of the present invention provides a three-phase full-bridge packaged chip, which includes a substrate, three first power dies, and three second power dies; the three first power crystal grains form an upper bridge arm of a three-phase full bridge, and the three second power crystal grains form a lower bridge arm of the three-phase full bridge;

the substrate comprises a first base island region, a second base island region and a tie bar region; the tie bar region surrounds the first foundation island region and surrounds the second foundation island region; three first power crystal grains are arranged in the first base island region, and each second power crystal grain is arranged in each second base island region; the three first power crystal grains are respectively correspondingly connected with one second power crystal grain.

Optionally, one first power crystal grain and one second power crystal grain form one bridge arm of a three-phase full bridge; the first power crystal grain and the second power crystal grain comprise a first pole, a second pole and a grid;

the first pole of the first power crystal grain is connected with a power supply, the grid electrodes of the first power crystal grain and the second power crystal grain are both connected with a control signal, the second pole of the first power crystal grain is connected with the first pole of the second power crystal grain, and the second pole of the second power crystal grain is grounded.

Optionally, the first base island region includes a first edge, a second edge, a third edge, and a fourth edge that are connected end to end, and the second base island region includes a fifth edge, a sixth edge, a seventh edge, and an eighth edge that are connected end to end; the first edge and the seventh edge are parallel and adjacent to each other;

the lacing wire area comprises a first patterned structure, a second patterned structure and a third patterned structure;

the first patterning structure is arranged on the outer side of the third edge of the first island region; the second patterned structure is disposed between the first edge and the seventh edge; the third patterned structure is disposed outside the second edge, or the third patterned structure is disposed outside the fourth edge.

Optionally, a side of the first patterned structure away from the third edge is provided with a first recessed area;

the three-phase full-bridge packaged chip further comprises a first bonding pad, and the first bonding pad is arranged in the first concave area.

Optionally, three second base island regions are adjacently arranged;

the lacing wire area also comprises a fourth patterned structure, a fifth patterned structure and a sixth patterned structure;

a part of the fourth patterned structure is arranged between the sixth edge and the eighth edge of the adjacent second foundation island region, and the other part of the fourth patterned structure is arranged between the seventh edge of the second foundation island region at the outer side and the second patterned structure; the fifth patterning structure is arranged outside the fifth edge of the second foundation island region; the sixth patterned structure is disposed outside a sixth edge of the second foundation island region at the outside, or the sixth patterned structure is disposed outside an eighth edge of the second foundation island region at the outside.

Optionally, a side of the fifth patterned structure away from the fifth edge is provided with a second recessed region;

the three-phase full-bridge packaged chip further comprises a second bonding pad and a third bonding pad, and the second bonding pad and the third bonding pad are arranged in the second concave area.

Optionally, one first power crystal grain and one second power crystal grain form one bridge arm of a three-phase full bridge; the first power crystal grain and the second power crystal grain comprise a first pole, a second pole and a grid;

the first pole of the first power crystal grain is connected with the first base island area, the grid of the first power crystal grain is connected with a first bonding pad, the second pole of the first power crystal grain is connected with a second base island area, the first pole of the second power crystal grain is connected with the second base island area, the second pole of the second power crystal grain is connected with a second bonding pad, and the grid of the second power crystal grain is connected with a third bonding pad; the first pad and the third pad are connected to the control signal interface, and the second pad is grounded.

Optionally, the three-phase full-bridge packaged chip further comprises a packaging layer;

the packaging layer packages all parts of the substrate except the first base island region, the second base island region, the first bonding pad, the second bonding pad and the third bonding pad.

Optionally, the three-phase full-bridge packaged chip further comprises transition regions, and the transition regions are located between the tie bar regions, between the tie bar region and the first base island region, and between the tie bar region and the second base island region; the thickness of the transition region corresponding to the substrate is smaller than that of the first base island region corresponding to the substrate, and the thickness of the transition region corresponding to the substrate is smaller than that of the second base island region corresponding to the substrate.

Optionally, the area of the base corresponding to the lacing wire area is hollowed out.

The technical scheme of this embodiment, through the three-phase full-bridge package chip that utilizes basement, first power crystalline grain and the design of second power crystalline grain can reduce the design volume of the power module of full-bridge, utilizes the fixed circuit frame that bears first power crystalline grain and second power crystalline grain of basement design to replace the interconnecting link of the power module of part full-bridge, has simplified the line connection of the power module of full-bridge, realizes the encapsulation design of the no extension pin of highly integrated three-phase full-bridge package chip.

Drawings

To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.

Fig. 1 is a schematic structural diagram of an internal three-phase full-bridge packaged chip according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an equivalent circuit of a three-phase full-bridge packaged chip according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an internal structure of another three-phase full-bridge packaged chip according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an internal structure of another three-phase full-bridge packaged chip according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an internal structure of another three-phase full-bridge packaged chip according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides a three-phase full-bridge packaged chip, and fig. 1 is a schematic structural diagram of the interior of the three-phase full-bridge packaged chip provided by the embodiment of the invention. As shown in fig. 1, the three-phase full-bridge packaged chip includes a substrate 100, three first power dies 111, and three second power dies 121; the three first power crystal grains 111 form an upper bridge arm of a three-phase full bridge, and the three second power crystal grains 121 form a lower bridge arm of the three-phase full bridge; substrate 100 includes first base island region 110, second base island region 120, and tie bar region 130; the tie bar region 130 surrounds the first base island region 110 and surrounds the second base island region 120; three first power dies 111 are disposed in the first base island 110, and each second power die 121 is disposed in each second base island 120; three first power dies 111 are correspondingly connected to one second power die 121.

Specifically, the three-phase full-bridge packaged chip can convert direct current into three-phase alternating current. The three first power crystal grains 111 and the three second power crystal grains 121 are control cores of a three-phase full-bridge packaged chip, and the substrate 100 is a carrier for circuit connection of the three first power crystal grains 111 and the three second power crystal grains 121, so that the first power crystal grains 111 and the second power crystal grains 121 are electrically connected, and the substrate can also play a role in fixing the first power crystal grains 111 and the second power crystal grains 121 and a bridge connected with an external device.

In addition, three first power dies 111 are all disposed on the first base island region 110, and the first power dies 111 are electrically connected to the first base island region 110, that is, the first power dies 111 can realize signal transmission through connection with the first base island region 110. Three second power dies 121 are respectively disposed on each second ground island 120, and the second power dies 121 are electrically connected to the second ground island 120, i.e., the second power dies 121 can realize signal transmission through connection with the second ground island 120. The lacing region 130 may be fixedly attached to other areas disposed on the substrate 100 to improve stability of the other areas. For example, the tie bar region 130 is used to fix the first and second foundation islands 110 and 120 disposed on the substrate 100, for which the tie bar region 130 is disposed around the first and second foundation islands 110 and 120.

In summary, in the present disclosure, the substrate 100, the first power die 111, and the second power die 121 are used to design a three-phase full-bridge package chip, so as to reduce the design volume of the full-bridge power module, and the substrate 100 is used to design a circuit frame that fixedly carries the first power die 111 and the second power die 121 to replace a part of the connection circuit of the full-bridge power module, thereby simplifying the circuit connection of the full-bridge power module, and realizing the package design without the extension pins of the highly integrated three-phase full-bridge package chip.

Fig. 2 is a schematic structural diagram of an equivalent circuit of a three-phase full-bridge packaged chip according to an embodiment of the present invention. As shown in fig. 2, a first power crystal grain 111 and a second power crystal grain 121 form a bridge arm 101 of a three-phase full bridge; the first power die 111 and the second power die 121 each include a first pole D, a second pole S, and a gate G; a first pole D of the first power die 111 is connected to a power source VCC, gates G of the first power die 111 and the second power die 121 are both connected to a control signal, a second pole S of the first power die 111 is connected to the first pole D of the second power die 121, and the second pole S of the second power die 121 is grounded GND.

The first power crystal grain 111 and the second power crystal grain 121 may be Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs). The output current of each phase of the three-phase full-bridge packaging chip is output under the common control of an upper bridge arm of the three-phase full bridge and a lower bridge arm of the three-phase full bridge. The upper bridge arm of the three-phase full-bridge packaged chip is composed of three first power crystal grains 111 sharing an anode, and the three first power crystal grains are conducted in the positive half cycle of the power supply and output forward current. The lower arm of the three-phase full-bridge packaged chip is composed of three second power crystal grains 121 sharing a cathode, is conducted in the negative half cycle of the power supply, and outputs reverse current. The three first power crystal grains 111 are correspondingly connected with one second power crystal grain 121, so that the series connection of a group of common-cathode second power crystal grains 121 and a group of common-anode first power crystal grains 111 is realized, and the direct current is converted into three-phase alternating current. One first power crystal grain 111 and one second power crystal grain 121 form one bridge arm 101 of a three-phase full bridge, and an a-phase voltage, a B-phase voltage and a C-phase voltage can be respectively led out from the connection position of the first power crystal grain 111 and the second power crystal grain 121 in each bridge arm 101.

Fig. 3 is a schematic structural diagram of the interior of another three-phase full-bridge packaged chip according to an embodiment of the present invention, as shown in fig. 3, a first base island region includes a first edge 001, a second edge 002, a third edge 003, and a fourth edge 004 connected end to end, and a second base island region includes a fifth edge 005, a sixth edge 006, a seventh edge 007, and an eighth edge 008 connected end to end; the first edge 001 and the seventh edge 007 are parallel and adjacent; the lacing region includes a first patterned structure 131, a second patterned structure 132, and a third patterned structure 133; the first patterned structure 131 is disposed outside the third edge 003 of the first foundation island region; the second patterned structure 132 is disposed between the first edge 001 and the seventh edge 007; the third patterned structure 133 is disposed outside the second edge 002, or the third patterned structure 133 is disposed outside the fourth edge 004.

Specifically, the first foundation island region is a quadrilateral formed by connecting a first edge 001, a second edge 002, a third edge 003 and a fourth edge 004 end to end in sequence, for example, a first foundation island region of a rectangular structure. The second foundation island region is a quadrilateral, for example, a rectangular second foundation island region, which is formed by connecting the fifth edge 005, the sixth edge 006, the seventh edge 007 and the eighth edge 008 end to end in sequence. The first base island region is used for correspondingly arranging three power crystal grains, the second base island region is used for correspondingly arranging one power crystal grain, each first power crystal grain 111 on the first base island region is correspondingly connected with each second power crystal grain 121 arranged on the second base island region, the first edge 001 of the first base island region is parallel to and adjacently arranged with the seventh edge 007 of the second base island region, and therefore connection of the first power crystal grain 111 and the second power crystal grain 121 arranged on the first base island region and the second base island region is facilitated. The tie bar region disposed around the first base island region includes a first patterned structure 131, a second patterned structure 132, and a third patterned structure 133. The first patterned structure 131, the second patterned structure 132, the third patterned structure 133 and the first island region are disposed on the substrate in a specific positional relationship: the first patterned structure 131 is disposed outside the third edge 003 of the first foundation island region 110; the second patterned structure 132 is disposed between the first edge 001 and the seventh edge 007; the third patterned structure 133 is disposed outside the second edge 002, or the third patterned structure 133 is disposed outside the fourth edge 004. Thereby the first patterned structure 131, the second patterned structure 132 and the third patterned structure 133 surround the first base island region, and stable fixation of the first base island region is achieved.

With continued reference to fig. 3, optionally, a side of the first patterned structure 131 away from the third edge 003 is provided with a first recessed region 1311; the three-phase full-bridge packaged chip further comprises a first bonding pad, and the first bonding pad is arranged in the first recessed area 1311.

Specifically, a first recessed region 1311 is further disposed on the substrate of the three-phase full-bridge packaged chip, and a first pad is further disposed in the first recessed region 1311. The first pad is electrically connected to the first power die 111 disposed on the first pad island, and serves as a bridge for signal transmission between the first power die 111 disposed on the first pad island and an external device. The first recess 1311 is disposed on a side of the first patterned structure 131 far from the third edge 003, so that the first patterned structure 131 facilitates stable fixing of the first pad, and the first patterned structure 131 also ensures stable connection of the first pad and the first island region. It should be noted that: the thickness of the substrate corresponding to the first patterned structure 131 is less than the thickness of the first pad corresponding to the first recess 1311.

With continued reference to fig. 3, optionally, three second base island regions are adjacently disposed; the lacing region further comprises a fourth patterned structure 134, a fifth patterned structure 135 and a sixth patterned structure 136; a portion of the fourth patterned structure 134 is disposed between the sixth edge 006 and the eighth edge 008 of the adjacent second base island region, and another portion of the fourth patterned structure 134 is disposed between the seventh edge 007 and the second patterned structure 132 of the outer second base island region; the fifth patterned structure 135 is disposed outside the fifth edge 005 of the second foundation island region; the sixth patterned structure 136 is disposed outside the sixth edge 006 of the second base island region at the outside, or the sixth patterned structure 136 is disposed outside the eighth edge 008 of the second base island region at the outside.

Specifically, three adjacent second base island regions are disposed on the substrate of the three-phase full-bridge packaged chip, and the seventh edge 007 of each second base island region is parallel and adjacent to the first edge 001 of the first base island region, so that it can be seen that the second base island regions are disposed outside the first edge 001 of the first base island region. The lacing region further includes a fourth patterned structure 134, a fifth patterned structure 135, and a sixth patterned structure 136. The tie bar region disposed around the second base island region includes a second patterned structure 132, a fourth patterned structure 134, a fifth patterned structure 135, and a sixth patterned structure 136. The second patterned structure 132, the fourth patterned structure 134, the fifth patterned structure 135, the sixth patterned structure 136 and the second base island region are disposed on the substrate in a specific positional relationship: the second patterned structure 132 is disposed outside the seventh edges 007 of the three second base island regions, a portion of the fourth patterned structure 134 is disposed between the sixth edge 006 and the eighth edge 008 of the adjacent second base island regions, and another portion of the fourth patterned structure 134 is disposed between the seventh edge 007 of the outside second base island region and the second patterned structure 132; the fifth patterned structure 135 is disposed outside the fifth edge 005 of the second foundation island region; the sixth patterned structure 136 is disposed outside the sixth edge 006 of the second base island region at the outside, or the sixth patterned structure 136 is disposed outside the eighth edge 008 of the second base island region at the outside. Thereby the second patterned structure 132, the fourth patterned structure 134, the fifth patterned structure 135 and the sixth patterned structure 136 surround the second foundation island region, and stable fixation of the second foundation island region is achieved.

With continued reference to fig. 3, optionally, a side of the fifth patterned structure 135 away from the fifth edge 005 is provided with a second recessed region 1351; the three-phase full-bridge packaged chip further comprises a second bonding pad and a third bonding pad, and the second bonding pad and the third bonding pad are arranged in the second concave region 1351.

Specifically, a second recessed region 1351 is further disposed on the substrate of the three-phase full-bridge packaged chip, and a second pad and a third pad are further disposed in the second recessed region 1351. The second pad and the third pad are used to be electrically connected to the second power die 121 disposed on the second island region, and serve as a bridge for signal transmission between the second power die 121 disposed on the second island region and an external device. The second recess region 1351 is disposed on a side of the fifth patterned structure 135 away from the fifth edge 005, so that the fifth patterned structure 135 facilitates stable fixing of the second pad and the third pad, and the fifth patterned structure 135 also ensures stable connection of the second pad, the third pad and the second base island region. It should be noted that: the thickness of the substrate corresponding to the fifth patterned structure 135 is less than the thickness of the second pad and the third pad disposed corresponding to the first recess region 1311.

Fig. 4 is a schematic structural diagram of an internal structure of another three-phase full-bridge packaged chip according to an embodiment of the present invention, as shown in fig. 4, a first power crystal grain 111 and a second power crystal grain 121 form a bridge arm of a three-phase full bridge; the first power die 111 and the second power die 121 each include a first pole D, a second pole S, and a gate G; a first pole D of the first power die 111 is connected to the first base island 110, a gate G of the first power die 111 is connected to a first pad 140, a second pole S of the first power die 111 is connected to a second base island 120, a first pole D of the second power die 121 is connected to the second base island 120, a second pole S of the second power die 121 is connected to a second pad 150, and a gate G of the second power die 121 is connected to a third pad 160; the first body island 110 is connected to a power supply, the first pad 140 and the third pad 160 are connected to a control signal interface, and the second pad 150 is grounded.

Specifically, one first power crystal grain 111 and one second power crystal grain 121 form one bridge arm 100 of a three-phase full bridge, and an a-phase voltage, a B-phase voltage and a C-phase voltage can be respectively led out from the connection of the first power crystal grain 111 and the second power crystal grain 121 of each bridge arm. As shown in fig. 4, the first power die 111 and the second power die 121 are metal oxide semiconductor dies, wherein a first surface (bottom surface) of the metal oxide semiconductor die is a first pole D, a second surface (front surface) of the metal oxide semiconductor die is a second pole S, and a square area on the second surface of the metal oxide semiconductor die is a gate G. The first pole D of the first power die 111 is connected to the first ground island 110, and the first pole D of the first power die 111 may be soldered to the first ground island 110. The gate G of the first power die 111 is connected to a first pad 140, and one end of a copper wire or a gold wire may be soldered to the gate G of the first power die 111 and the other end of the copper wire or the gold wire may be soldered to the first pad 140. The second pole S of the first power die 111 is connected to a second ground island 120, and one end of a copper sheet or aluminum strip may be soldered to the first pole D of the second module and one end of the copper sheet or aluminum strip may be connected to the second ground island 120. The first pole D of the second power die 121 is connected to the second base island region 120, and the first pole D of the second power die 121 may be soldered to the second base island region 120. The second pole S of the second power die 121 is connected to a second pad 150, and one end of a copper wire or a gold wire may be soldered to the second pole S of the second power die 121, and the other end of the copper wire or the gold wire may be soldered to the second pad 150. The gate G of the second power die 121 is connected to a third pad 160, and one end of a copper wire or a gold wire may be soldered to the gate G of the second power die 121 and the other end of the copper wire or the gold wire may be soldered to the third pad 160. In addition, the first foundation island 110 is connected to a power source, the first pad 140 and the third pad 160 are connected to a control signal interface, and the second pad 150 is grounded.

As can be seen from the above connection relationship, the first pole D of the first power die 111 can be connected to a power source through the first ground island 110, the gate G of the first power die 111 can be connected to a control signal interface through the first pad 140, the gate G of the second power die 121 can be connected to the control signal interface through the third pad 160, the second pole S of the first power die 111 is connected to the first pole D of the second power die 121 through the second ground island 120, and the second pole S of the second power die 121 is connected to the ground GND through the second pad 150.

Optionally, the three-phase full-bridge packaged chip further comprises a packaging layer; the packaging layer packages all parts of the substrate except the first base island region, the second base island region, the first bonding pad, the second bonding pad and the third bonding pad.

The packaging layer can be made of epoxy resin, and the epoxy resin has excellent chemical resistance, strong adhesive force, good heat resistance and electrical insulation. Therefore, the epoxy resin is used as the packaging layer, all parts except the first base island region, the second base island region, the first bonding pad, the second bonding pad and the third bonding pad are packaged, and the part wrapped by the packaging layer can be well protected. Since the first power die and the second power die need to be disposed on the first base island region and the second base island region, respectively, and the first power die and the second power die need to be in contact and electrically connected with an external interface, the encapsulation layer does not need to wrap the first base island region and the second base island region. Similarly, the first pad is used as a bridge for signal transmission between the first power crystal grain arranged on the first foundation island region and an external device, and the second pad and the third pad are used as a bridge for signal transmission between the second power crystal grain arranged on the second foundation island region and the external device and need to be in contact with and electrically connected with an external interface, so that the packaging layer does not need to wrap the first pad, the second pad and the third pad. In addition, because the thickness of lacing wire district is less than first base island district, second base island district, first pad, second pad and third pad, utilize encapsulation layer encapsulation lacing wire district can reduce the stress in lacing wire district to realize the stress release in lacing wire district through the encapsulation layer.

Optionally, the three-phase full-bridge packaged chip further comprises transition regions, and the transition regions are located between the tie bar regions, between the tie bar region and the first base island region, and between the tie bar region and the second base island region; the thickness of the transition region corresponding to the substrate is smaller than that of the first base island region corresponding to the substrate, and the thickness of the transition region corresponding to the substrate is smaller than that of the second base island region corresponding to the substrate.

Wherein, the transition zone has the following specific functions: the first base island region, the second base island region and the tie bar region are connected. For example, the transition region is disposed between the tie bar region and the tie bar region, between the tie bar region and the first base island region, and between the tie bar region and the second base island region. In order to not affect the wiring arrangement of the power crystal grains carried by the first basic island region and the second basic island region in the later period (mainly preventing the contact short circuit of a lead and the transition region), the transition region is arranged between the tie bar regions, between the tie bar region and the first basic island region and between the tie bar region and the second basic island region, the thickness of the substrate corresponding to the transition region is smaller than that of the substrate corresponding to the first basic island region, and the thickness of the substrate corresponding to the transition region is smaller than that of the substrate corresponding to the second basic island region. Illustratively, the transition region has a thickness of 0.1mm ± 0.01mm, and the first and second ground island regions have a thickness of 0.2 mm. The transition area arranged on the substrate can be etched to the thickness of 0.1mm +/-0.01 mm by adopting a half etching process.

Fig. 5 is a schematic structural diagram of the interior of another three-phase full-bridge packaged chip according to an embodiment of the present invention, and as shown in fig. 5, an area in a tie bar area corresponding to a substrate is hollowed out.

Wherein, the area of the base corresponding to the lacing wire area is hollowed out (the shadow area is hollowed out). Illustratively, the inner regions of the first patterned structure 131, the second patterned structure 132, the third patterned structure 133, the fourth patterned structure 134, the fifth patterned structure 135 and the sixth patterned structure 136 are hollowed out. The base is arranged in a hollow manner corresponding to the area in the lacing wire area, and the area inside the lacing wire area can be etched by adopting an etching process. Therefore, the frame of the lacing wire area can be fixedly connected with other areas arranged on the substrate, so that the stability of the other areas is improved. In addition, the inner area of the lacing wire area is hollowed out, so that unnecessary areas are removed on the basis of ensuring normal electrical isolation, the reserved base area can reach more than 70% of the whole chip frame, and the quick heat dissipation of the whole chip frame is ensured.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.