阅读说明：本技术 半导体封装装置和半导体封装装置制造方法 (Semiconductor package device and semiconductor package device manufacturing method ) 是由 黄柏仁 于 2020-06-10 设计创作，主要内容包括：一种半导体封装装置,包括基板、芯片、导电组件、封胶层、及天线组件。芯片设置于基板,导电组件设置于基板,封胶层包覆芯片与导电组件,并露出芯片与导电组件的顶部,天线组件设置于封胶层,并与导电组件电性连接。本发明利用封胶层包覆晶片,並在封胶层上直接印刷天線結構,省去了天线基板的厚度,有效縮小封裝產品結合天線的厚度空間,滿足未來更小產品尺寸需求。(A semiconductor packaging device comprises a substrate, a chip, a conductive assembly, a sealing glue layer and an antenna assembly. The chip is arranged on the substrate, the conductive assembly is arranged on the substrate, the sealing adhesive layer coats the chip and the conductive assembly and exposes the top of the chip and the top of the conductive assembly, and the antenna assembly is arranged on the sealing adhesive layer and is electrically connected with the conductive assembly. The invention utilizes the sealing adhesive layer to coat the wafer, and the Chinese crop is directly printed on the sealing adhesive layer, thereby saving the thickness of the antenna substrate, effectively shortening the thickness margin of the Chinese crop pivoting into the Chinese crop, and ensuring that the requirement for reducing the size of the product for the see crop is not satisfied.)

1. A semiconductor package device, comprising:

a substrate;

the chip is arranged on the substrate;

the conductive assembly is arranged on the substrate;

the sealing adhesive layer coats the chip and the conductive assembly and exposes the top of the chip and the top of the conductive assembly; and

and the antenna component is arranged on the sealing adhesive layer and is electrically connected with the conductive component.

2. The semiconductor package device of claim 1, wherein the substrate has a circuit layer and a plurality of bonding pads electrically connected to the circuit layer, the chip and the conductive element being electrically connected to the circuit layer through the bonding pads.

3. The semiconductor package device of claim 1, further comprising an electronic component disposed on the substrate, the electronic component comprising a filter circuit or a passive component.

4. The semiconductor package device of claim 1, wherein the antenna element is directly attached to the encapsulant layer by screen printing.

5. The semiconductor package device of claim 1, further comprising a heat dissipation layer disposed on the chip, wherein the heat dissipation layer is directly attached to the surface of the chip exposed by the adhesive layer by screen printing.

6. A method of manufacturing a semiconductor package device, comprising:

providing a substrate;

arranging a chip on the substrate;

arranging a conductive component on the substrate;

forming an adhesive layer, and coating the chip and the conductive assembly;

grinding the sealing adhesive layer to expose the top of the chip and the conductive assembly; and

and arranging an antenna component on the sealing adhesive layer and electrically connecting with the conductive component.

7. The method of manufacturing a semiconductor package device according to claim 6, wherein the substrate has a circuit layer and a plurality of bonding pads electrically connected to the circuit layer, and the chip and the conductive element are electrically connected to the circuit layer through the bonding pads.

8. The method of claim 6, further comprising a heat dissipation layer disposed on the chip, wherein the heat dissipation layer is directly attached to the surface of the chip exposed by the encapsulant layer by screen printing, and the antenna assembly is directly attached to the encapsulant layer by screen printing.

9. The method of manufacturing a semiconductor package device according to claim 6, wherein the antenna element is coplanar with a bottom surface of the heat dissipation layer and a surface of the encapsulant layer.

10. The method of manufacturing a semiconductor package according to claim 6, wherein the conductive element is formed by stacking a plurality of copper balls.

Technical Field

The present invention relates to a semiconductor package device and a method for manufacturing the same, and more particularly, to a semiconductor package device directly printed on a top line on a sealing material layer and a method for manufacturing the same.

Background

An Antenna In Package (AiP) technology is based on an packaged material industrial process, the antenna is integrated with a chip in the package, shiitake function technology. However, the overhead wire requires that an additional circuit board with the overhead wire module be added to the wafer , causing an increase in the thickness of the packaged product-pivot, and an additional process outside of is required, resulting in an increase in cost.

Disclosure of Invention

In view of the above, in one embodiment of the present invention, a semiconductor package device and a method for manufacturing the semiconductor package device are provided to reduce the thickness of a packaged product and to have an antenna module.

An embodiment of the present invention discloses a semiconductor package device, including: the heat conduction carrier plate is provided with a circuit layer, and the bottom of the heat conduction carrier plate is provided with a welding ball connected with the circuit layer; the conductive element is formed on the circuit layer; the insulating layer is formed on the heat conduction carrier plate and exposes the conductive element; and the chip is arranged on the conductive element.

An embodiment of the present invention discloses a method for manufacturing a semiconductor package device, comprising: providing a heat-conducting carrier plate, wherein the heat-conducting carrier plate is provided with a circuit layer, and the circuit layer is provided with a first surface and a second surface opposite to the first surface; etching the heat-conducting carrier plate to expose the first surface; arranging a conductive element on the first surface, wherein the conductive element is provided with a conductive top surface; forming an insulating layer to cover the heat-conducting carrier plate and the conductive element; grinding the insulating layer to expose the conductive top surface; arranging a chip on the conductive top surface; etching the heat-conducting carrier plate to expose the second surface; and arranging solder balls to be connected with the circuit layer.

An embodiment of the invention discloses a semiconductor packaging device, which comprises a substrate; the chip is arranged on the substrate; the conductive assembly is arranged on the substrate; the sealing adhesive layer coats the chip and the conductive assembly and exposes the top of the chip and the top of the conductive assembly; and the antenna component is arranged on the sealing adhesive layer and is electrically connected with the conductive component.

Another embodiment of the present invention discloses a method for manufacturing a semiconductor package device, comprising providing a substrate; arranging a chip on the substrate; arranging a conductive component on the substrate; forming an adhesive layer, and coating the chip and the conductive assembly; grinding the sealing adhesive layer to expose the top of the chip and the conductive assembly; and arranging an antenna component on the sealing adhesive layer and electrically connected with the conductive component.

According to an embodiment of the present invention, the substrate has a circuit layer and a plurality of bonding pads electrically connected to the circuit layer, and the chip and the conductive element are electrically connected to the circuit layer through the bonding pads.

According to an embodiment of the present invention, the electronic device further includes an electronic device disposed on the substrate, and the electronic device includes a filter circuit or a passive device.

According to an embodiment of the invention, the antenna element is directly attached to the sealing adhesive layer through a screen printing method.

According to an embodiment of the present invention, the semiconductor package further includes a heat dissipation layer disposed on the chip, wherein the heat dissipation layer is directly attached to the surface of the chip exposed from the sealing adhesive layer by screen printing.

According to an embodiment of the invention, the antenna element and the bottom surface of the heat dissipation layer are coplanar with the surface of the sealing adhesive layer.

According to an embodiment of the present invention, the conductive element is formed by stacking a plurality of copper balls.

According to the embodiments of the present invention, since the wafer is coated with the sealing layer and is directly printed on the sealing layer, the thickness of the antenna substrate is omitted, the thickness space for pivoting the wafer is effectively cultivated, and the requirement for smaller product size reduction is satisfied. In addition, through the design of the adhesive layer, the purpose of directly printing the antenna is conveniently practiced, and the cost of the pivot crop is greatly reduced. Moreover, through the design of the body frame, the heat dissipation efficiency is further improved, and the reliability of the product is effectively improved.

Drawings

Fig. 1A is a cross-sectional view of a semiconductor package device according to an embodiment of the invention.

Fig. 1B shows a cross-sectional view of a semiconductor package device according to another embodiment of the invention.

Fig. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention.

Fig. 3A is a schematic top view of an array antenna according to an embodiment of the invention.

Fig. 3B is a graph showing simulation results of if the array antenna according to an embodiment of the present invention returns to a frequency.

Fig. 4A is a schematic top view of a patch antenna according to an embodiment of the invention.

Fig. 4B is a graph of simulation results of if the patch antenna according to an embodiment of the present invention returns to a frequency by a loss.

Description of the main elements

100A, 100B semiconductor package device

10 base plate

12 chips

14 electronic assembly

16A, 16B conductive assembly

17 sealant layer

19 antenna assembly

11 bonding pad

30. 40 feed point

32. 42 radiator

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

For the purpose of promoting an understanding and an enabling description of the invention, reference should now be made to the embodiments illustrated in the drawings and described in detail below, with the understanding that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific forms. Those of skill in the art may now appreciate that the invention may be practiced with modification of the specific details, such as those described in these and other embodiments, and that other structural, logical, and electrical changes may be made without departing from the spirit and scope of the present invention.

The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of the elements in the embodiments is for illustration and not for limitation. And the reference numerals in the drawings are repeated for simplicity of explanation, and do not necessarily indicate any relationship between the different embodiments. Wherein like reference numerals are used throughout the drawings and the description to refer to the same or like elements. The illustrations of the present specification are in simplified form and are not drawn to precise scale. For clarity and ease of description, directional terms (e.g., top, bottom, up, down, and diagonal) are used with respect to the accompanying drawings. The following description is intended to illustrate but not limit the scope of the invention, unless otherwise indicated by the scope of the claims appended hereto.

Further, in describing some embodiments of the invention, the specification may have presented the method and/or process of the invention as a particular sequence of steps. However, the methods and procedures are not limited to the particular sequence of steps described, as such may not necessarily be performed in the particular sequence of steps described. One skilled in the art will recognize that other sequences are possible. Therefore, the particular order of the steps set forth in the specification is not intended to limit the scope of the claims. Moreover, the claimed method and/or process is not limited by the order of steps performed, and one skilled in the art will recognize that the order of steps performed may be modified without departing from the spirit and scope of the claimed invention.

Fig. 1A is a cross-sectional view of a semiconductor package device according to an embodiment of the invention. The semiconductor package device 100A according to an embodiment of the invention includes a substrate 10, a chip 12, an electronic component 14, a conductive component 16A, a sealant layer 17, and an antenna component 19. The substrate 10 has a circuit layer (not shown) therein and a plurality of bonding pads 11 electrically connected to the circuit layer and respectively located on the upper surface and the lower surface of the substrate 10, and the substrate 10 may be a substrate with two or more circuit layers formed by a laminating method or a Build-up method. It is well known in the art, and therefore specific implementation details will not be described in detail to simplify the description. According to one embodiment of the present application, the substrate 10 can be made of different materials, such as silicon, polymer, and ceramic materials.

The chip 12 is disposed on the bonding pad 11 on the upper surface of the substrate 10, and is electrically connected to the circuit layer through the bonding pad 11. According to an embodiment of the present invention, the chip 12 may be various electronic components (electronic components) including integrated circuits such as active or passive components (active or passive elements), digital circuits or analog circuits (digital or analog circuits), for example, optoelectronic devices (optoelectronic devices), Micro-electromechanical Systems (MEMS), power amplification chips, power management chips, biometric devices, Micro-fluidic Systems (microfluidic Systems), or Physical sensors (Physical sensors) that measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process can be selectively used to process semiconductor chips such as image sensing devices, light-emitting diodes (LEDs), solar cells (solar cells), radio frequency components (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), fingerprint sensors, micro actuators (micro actuators), surface acoustic wave components (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads).

The electronic component 14 is disposed on the bonding pad 11 on the upper surface of the substrate 10, and is electrically connected to the circuit layer through the bonding pad 11. According to an embodiment of the invention, the electronic component 14 may include a filter circuit or a passive component, such as a resistor, a capacitor, an inductor, etc., to implement functions of filtering, voltage stabilization, signal amplification, etc. in cooperation with the chip 12. According to an embodiment of the present invention, the chip 12 and the electronic component 14 can be mounted on the substrate 10 by using Surface Mount Technology (SMT).

The conductive element 16A is disposed on the bonding pad 11 on the upper surface of the substrate 10, and is electrically connected to the circuit layer through the bonding pad 11. According to an embodiment of the present invention, the conductive element 16A may be a metal plug (plug) or a conductive pillar, and the material may be, for example, gold, silver, copper, aluminum, tungsten, tin, alloy or other suitable conductive material.

The encapsulant layer 17 is conformally formed on the substrate 10 to encapsulate the chip 12, the electronic component 14 and the conductive component 16A and expose the top of the chip 12 and the conductive component 16A. The sealant layer 17 may provide mechanical stability and protection against oxidation, humidity and other environmental conditions. According to an embodiment of the present invention, the molding compound layer 17 may be formed of a molding material (molding material). The encapsulant may include an acid-based resin (novolac-based resin), an epoxy-based resin (epoxy-based resin), a silicone-based resin (silicone-based resin), or other suitable coating agent. The encapsulating material may also include a suitable filler (filler), such as powdered silicon dioxide. The encapsulating material may be a pre-impregnated material, such as a pre-impregnated dielectric material.

The heat dissipation layer 18 is disposed on the chip 12 for dissipating heat from the chip 12. According to an embodiment of the present invention, the heat dissipation layer 18 may be made of an aluminum paste or a silver paste, and is directly attached to the surface of the chip 12 exposed by the sealing compound layer 17 by a Screen printing (Screen printing) method. According to other embodiments of the present invention, the material of the heat dissipation layer 18 may further include ceramic, graphene (graphene), graphite (graphite), Carbon Nanotubes (CNTs), carbon nanoballs (carbon nanoballs), or a combination thereof.

The antenna component 19 is disposed on the sealing adhesive layer 17 and electrically connected to the conductive component 16A. According to an embodiment of the present invention, the antenna element 19 may include a radiator having a feed end, the radiator is disposed on the sealing layer 17, and the ground layer of the antenna element 19 may share the ground layer of the electronic element 14. The antenna assembly 19 is partially disposed on the conductive assembly 16A, and the antenna assembly 19 can be directly attached to the sealing adhesive layer 17 by Screen printing (Screen printing), and the material of the antenna assembly can be aluminum glue or silver glue. In this embodiment, the bottom surfaces of the antenna element 19 and the heat dissipation layer 18 are coplanar with the surface of the sealant layer 17. In addition, the antenna component 19 may be an array antenna (array antenna) or a patch antenna (patch antenna). Since the layout area required for the array antenna is relatively large compared to the patch antenna, those skilled in the art can select the array antenna or the patch antenna to be used according to the functional requirements and the product size.

Fig. 1B shows a cross-sectional view of a semiconductor package device according to another embodiment of the invention. FIG. 1B is a schematic view showing a difference in FIG. 1A in that the conductive member 16A in FIG. 1A is replaced with a conductive member 16B. According to an embodiment of the present invention, the conductive element 16B may be formed by stacking a plurality of copper balls. The conductive element 16B is formed by stacking a plurality of copper balls, so that the process can be simplified and the cost can be reduced. In other embodiments, the conductive element 16B may be formed by laminating a plurality of solder balls.

Fig. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. Referring to fig. 2A, a substrate 10 is provided. The substrate 10 has a circuit layer and a plurality of bonding pads 11 electrically connected to the circuit layer and respectively located on the upper surface and the lower surface of the substrate 10, and the substrate 10 may be a substrate with two or more circuit layers formed by a laminating method or a Build-up method. It is well known in the art, and therefore specific implementation details will not be described in detail to simplify the description. According to one embodiment of the present application, the substrate 10 can be made of different materials, such as silicon, polymer, and ceramic materials.

Next, the chip 12 and the electronic component 14 are disposed on the bonding pad 11 on the upper Surface of the substrate 10, and according to an embodiment of the invention, the chip 12 and the electronic component 14 can be mounted on the substrate 10 by using Surface Mount Technology (SMT). The chip 12 may be various electronic components (electronic components) including integrated circuits such as active or passive components (active or passive elements), digital circuits, or analog circuits, for example, optoelectronic devices (optoelectronic devices), Micro-electromechanical Systems (MEMS), power amplification chips, power management chips, biometric devices, Micro-fluidic Systems (microfluidic Systems), or Physical sensors (Physical sensors) that measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process can be selectively used to process semiconductor chips such as image sensing devices, light-emitting diodes (LEDs), solar cells (solar cells), radio frequency components (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), fingerprint sensors, micro actuators (micro actuators), surface acoustic wave components (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads). The electronic component 14 is electrically connected to the circuit layer through the bonding pad 11. According to an embodiment of the invention, the electronic component 14 may include a filter circuit or a passive component, such as a resistor, a capacitor, an inductor, etc., to implement functions of filtering, voltage stabilization, signal amplification, etc. in cooperation with the chip 12.

Next, the conductive element 16A is formed on the bonding pad 11 on the upper surface of the substrate 10, and is electrically connected to the circuit layer through the bonding pad 11. According to an embodiment of the present invention, the conductive element 16A may be a metal plug (plug) or a conductive pillar, and the material of the conductive element 16A may be gold, silver, copper, aluminum, tungsten, tin, alloy or other suitable conductive materials, for example, according to another embodiment of the present invention, the conductive element 16A may be replaced with the conductive element 16B shown in fig. 1B, and is formed by stacking a plurality of copper balls.

Next, referring to fig. 2B, an adhesive layer 17 is conformally formed on the substrate 10 to encapsulate the chip 12, the electronic element 14 and the conductive element 16A. The sealant layer 17 may provide mechanical stability and protection against oxidation, humidity and other environmental conditions. According to an embodiment of the present invention, the molding compound layer 17 may be formed of a molding material (molding material). The encapsulant may include an acid-based resin (novolac-based resin), an epoxy-based resin (epoxy-based resin), a silicone-based resin (silicone-based resin), or other suitable coating agent. The encapsulating material may also include a suitable filler (filler), such as powdered silicon dioxide. The encapsulating material may be a pre-impregnated material, such as a pre-impregnated dielectric material.

Next, referring to fig. 2C, the encapsulant layer 17 is polished to expose the top of the chip 12, and a portion of the top of the conductive element 16A is polished away, so that the top of the conductive element 16A is aligned with the top of the chip 12 and the upper surface of the polished encapsulant layer 17. According to an embodiment of the present invention, the sealant 17 can be polished by an abrasive wheel through an abrasive method.

Next, referring to fig. 2D, a heat dissipation layer 18 is formed on the chip 12, and an antenna element 19 is formed on the sealing compound layer 17 and electrically connected to the conductive element 16, thereby completing the semiconductor package device according to an embodiment of the invention. According to an embodiment of the present invention, the material of the heat dissipation layer 18 may further include ceramic, graphene (graphene), graphite (graphite), Carbon Nanotubes (CNTs), carbon nanoballs (carbon nanoballs), or a combination thereof. The antenna element 19 may include a radiator having a feed end, the radiator is disposed on the molding compound 17, and the ground layer of the antenna element 19 may share the ground layer of the electronic element 14. The antenna element 19 may be partially disposed on the conductive element 16, and the antenna may be an array antenna (array antenna) or a patch antenna (patch antenna). According to another embodiment of the present invention, the heat dissipation layer 18 and the antenna assembly 19 can be made of an aluminum paste or a silver paste, and are respectively attached to the surfaces of the chip 12 and the encapsulation layer 17 by a Screen printing (Screen printing) method.

Fig. 3A is a schematic top view of an array antenna according to an embodiment of the invention. As shown, the feed point 30 is centrally located and the radiator 32 is rectangular. In the illustration, only four radiators 32 are shown, however, in practical applications, a person skilled in the art can select an appropriate number of radiators 32 according to the functional requirements and the product size. According to the embodiment shown in fig. 3A, the size of the array antenna may be less than 12 × 12 mm. Fig. 3B is a graph of simulation results of Return Loss (Return Loss) versus frequency of the array antenna according to an embodiment of the present invention. As shown in FIG. 3B, the usable bandwidth of the array antenna is between 27.54GHz and 28.58 GHz.

Fig. 4A is a schematic top view of a patch antenna according to an embodiment of the invention. As shown, the feed point 40 is located at the lower left corner, and the radiator 42 is rectangular. According to the embodiment shown in fig. 4A, the patch antenna may be smaller than 6.5 x 6.5 mm in size, which is smaller than the array antenna. Fig. 4B is a graph of simulation results of Return Loss (Return Loss) versus frequency of the patch antenna according to an embodiment of the present invention. As shown in fig. 4B, the usable bandwidth of the patch antenna is between 27.6GHz and 28.58 GHz.

According to the embodiments of the present invention, since the wafer is coated with the sealing layer and is directly printed on the sealing layer, the thickness of the antenna substrate is omitted, the thickness space for pivoting the wafer is effectively cultivated, and the requirement for smaller product size reduction is satisfied. In addition, through the design of the adhesive layer, the purpose of directly printing the antenna is conveniently practiced, and the cost of the pivot crop is greatly reduced. Moreover, through the design of the body frame, the heat dissipation efficiency is further improved, and the reliability of the product is effectively improved.

It will be apparent to those skilled in the art that other corresponding changes and modifications can be made according to the actual needs created by the inventive arrangements and inventive concepts herein, and such changes and modifications are intended to fall within the scope of the appended claims.